tjh.dev / kernel
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Merge tag 'pinctrl-v6.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
"Some assorted pin control fixes, the most interesting will be the
Intel patch fixing a classic problem: laptop touchpad IRQs...

- Some pin drive register fixes in the Mediatek driver.

- Return proper error code in the Aspeed driver, and revert and
ill-advised force-disablement patch that needs to be reworked.

- Fix AMD driver debug output.

- Fix potential NULL dereference in the Single driver.

- Fix a group definition error in the Qualcomm SM8450 LPASS driver.

- Restore pins used in direct IRQ mode in the Intel driver (This
fixes some laptop touchpads!)"

* tag 'pinctrl-v6.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: intel: Restore the pins that used to be in Direct IRQ mode
pinctrl: qcom: sm8450-lpass-lpi: correct swr_rx_data group
pinctrl: aspeed: Revert "Force to disable the function's signal"
pinctrl: single: fix potential NULL dereference
pinctrl: amd: Fix debug output for debounce time
pinctrl: aspeed: Fix confusing types in return value
pinctrl: mediatek: Fix the drive register definition of some Pins

Linus Torvalds 545c80ab 4cfd5afc

+30 -8
+11 -2
drivers/pinctrl/aspeed/pinctrl-aspeed.c
··· 93 93 static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx, 94 94 const struct aspeed_sig_expr *expr) 95 95 { 96 + int ret; 97 + 96 98 pr_debug("Disabling signal %s for %s\n", expr->signal, 97 99 expr->function); 98 100 99 - return aspeed_sig_expr_set(ctx, expr, false); 101 + ret = aspeed_sig_expr_eval(ctx, expr, true); 102 + if (ret < 0) 103 + return ret; 104 + 105 + if (ret) 106 + return aspeed_sig_expr_set(ctx, expr, false); 107 + 108 + return 0; 100 109 } 101 110 102 111 /** ··· 123 114 int ret = 0; 124 115 125 116 if (!exprs) 126 - return true; 117 + return -EINVAL; 127 118 128 119 while (*exprs && !ret) { 129 120 ret = aspeed_sig_expr_disable(ctx, *exprs);
+13 -3
drivers/pinctrl/intel/pinctrl-intel.c
··· 1709 1709 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); 1710 1710 1711 1711 #ifdef CONFIG_PM_SLEEP 1712 + static bool __intel_gpio_is_direct_irq(u32 value) 1713 + { 1714 + return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && 1715 + (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO); 1716 + } 1717 + 1712 1718 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1713 1719 { 1714 1720 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); ··· 1748 1742 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1749 1743 */ 1750 1744 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1751 - if ((value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && 1752 - (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO)) 1745 + if (__intel_gpio_is_direct_irq(value)) 1753 1746 return true; 1754 1747 1755 1748 return false; ··· 1878 1873 for (i = 0; i < pctrl->soc->npins; i++) { 1879 1874 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1880 1875 1881 - if (!intel_pinctrl_should_save(pctrl, desc->number)) 1876 + if (!(intel_pinctrl_should_save(pctrl, desc->number) || 1877 + /* 1878 + * If the firmware mangled the register contents too much, 1879 + * check the saved value for the Direct IRQ mode. 1880 + */ 1881 + __intel_gpio_is_direct_irq(pads[i].padcfg0))) 1882 1882 continue; 1883 1883 1884 1884 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
+2 -2
drivers/pinctrl/mediatek/pinctrl-mt8195.c
··· 659 659 PIN_FIELD_BASE(10, 10, 4, 0x010, 0x10, 9, 3), 660 660 PIN_FIELD_BASE(11, 11, 4, 0x000, 0x10, 24, 3), 661 661 PIN_FIELD_BASE(12, 12, 4, 0x010, 0x10, 12, 3), 662 - PIN_FIELD_BASE(13, 13, 4, 0x010, 0x10, 27, 3), 662 + PIN_FIELD_BASE(13, 13, 4, 0x000, 0x10, 27, 3), 663 663 PIN_FIELD_BASE(14, 14, 4, 0x010, 0x10, 15, 3), 664 664 PIN_FIELD_BASE(15, 15, 4, 0x010, 0x10, 0, 3), 665 665 PIN_FIELD_BASE(16, 16, 4, 0x010, 0x10, 18, 3), ··· 708 708 PIN_FIELD_BASE(78, 78, 3, 0x000, 0x10, 15, 3), 709 709 PIN_FIELD_BASE(79, 79, 3, 0x000, 0x10, 18, 3), 710 710 PIN_FIELD_BASE(80, 80, 3, 0x000, 0x10, 21, 3), 711 - PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 28, 3), 711 + PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 24, 3), 712 712 PIN_FIELD_BASE(82, 82, 3, 0x000, 0x10, 27, 3), 713 713 PIN_FIELD_BASE(83, 83, 3, 0x010, 0x10, 0, 3), 714 714 PIN_FIELD_BASE(84, 84, 3, 0x010, 0x10, 3, 3),
+1
drivers/pinctrl/pinctrl-amd.c
··· 365 365 366 366 } else { 367 367 debounce_enable = " ∅"; 368 + time = 0; 368 369 } 369 370 snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit); 370 371 seq_printf(s, "debounce %s (🕑 %sus)| ", debounce_enable, debounce_value);
+2
drivers/pinctrl/pinctrl-single.c
··· 372 372 if (!pcs->fmask) 373 373 return 0; 374 374 function = pinmux_generic_get_function(pctldev, fselector); 375 + if (!function) 376 + return -EINVAL; 375 377 func = function->data; 376 378 if (!func) 377 379 return -EINVAL;
+1 -1
drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
··· 105 105 static const char * const swr_tx_clk_groups[] = { "gpio0" }; 106 106 static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; 107 107 static const char * const swr_rx_clk_groups[] = { "gpio3" }; 108 - static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5", "gpio15" }; 108 + static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; 109 109 static const char * const dmic1_clk_groups[] = { "gpio6" }; 110 110 static const char * const dmic1_data_groups[] = { "gpio7" }; 111 111 static const char * const dmic2_clk_groups[] = { "gpio8" };