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Merge branch 'pci/controller/dwc-rockchip'

- Disable unused BAR 0 and BAR 1 for Root Port (Shawn Lin)

* pci/controller/dwc-rockchip:
PCI: dw-rockchip: Disable BAR 0 and BAR 1 for Root Port

+8
+8
drivers/pci/controller/dwc/pcie-dw-rockchip.c
··· 85 85 #define PCIE_LINKUP_MASK GENMASK(17, 16) 86 86 #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) 87 87 88 + #define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 89 + 88 90 struct rockchip_pcie { 89 91 struct dw_pcie pci; 90 92 void __iomem *apb_base; ··· 314 312 if (irq < 0) 315 313 return irq; 316 314 315 + pci->dbi_base2 = pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET; 316 + 317 317 ret = rockchip_pcie_init_irq_domain(rockchip); 318 318 if (ret < 0) 319 319 dev_err(dev, "failed to init irq domain\n"); ··· 325 321 326 322 rockchip_pcie_configure_l1ss(pci); 327 323 rockchip_pcie_enable_l0s(pci); 324 + 325 + /* Disable Root Ports BAR0 and BAR1 as they report bogus size */ 326 + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0); 327 + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0); 328 328 329 329 return 0; 330 330 }