tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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gpio: aspeed-sgpio: Convert IRQ functions to use llops callbacks

Update aspeed_sgpio_irq_handler() and aspeed_sgpio_setup_irqs() to use
the llops callbacks for register access instead of direct iowrite32().
This creates a unified hardware access layer, which is essential for
supporting SoCs with different register layouts like the AST2700.

Additionally, change the loop bounds to use ngpio instead of the static
ARRAY_SIZE(aspeed_sgpio_banks). This allows the driver to adapt to the
actual number of supported pins on the running SoC.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20260123-upstream_sgpio-v2-4-69cfd1631400@aspeedtech.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

authored by

Billy Tsai and committed by
Bartosz Golaszewski 43090d69 a3d37e0c

+10 -12
+10 -12
drivers/gpio/gpio-aspeed-sgpio.c
··· 319 319 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 320 320 struct irq_chip *ic = irq_desc_get_chip(desc); 321 321 struct aspeed_sgpio *data = gpiochip_get_data(gc); 322 - unsigned int i, p; 322 + unsigned int i, p, banks; 323 323 unsigned long reg; 324 324 325 325 chained_irq_enter(ic, desc); 326 326 327 - for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { 327 + banks = DIV_ROUND_UP(gc->ngpio, 64); 328 + for (i = 0; i < banks; i++) { 328 329 reg = data->pdata->llops->reg_bank_get(data, i << 6, reg_irq_status); 329 330 330 331 for_each_set_bit(p, &reg, 32) ··· 356 355 struct platform_device *pdev) 357 356 { 358 357 int rc, i; 359 - const struct aspeed_sgpio_bank *bank; 360 358 struct gpio_irq_chip *irq; 361 359 362 360 rc = platform_get_irq(pdev, 0); ··· 365 365 gpio->irq = rc; 366 366 367 367 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */ 368 - for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { 369 - bank = &aspeed_sgpio_banks[i]; 368 + for (i = 0; i < gpio->chip.ngpio; i += 2) { 370 369 /* disable irq enable bits */ 371 - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable)); 370 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_enable, 0); 372 371 /* clear status bits */ 373 - iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status)); 372 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_status, 1); 374 373 } 375 374 376 375 irq = &gpio->chip.irq; ··· 383 384 irq->num_parents = 1; 384 385 385 386 /* Apply default IRQ settings */ 386 - for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { 387 - bank = &aspeed_sgpio_banks[i]; 387 + for (i = 0; i < gpio->chip.ngpio; i += 2) { 388 388 /* set falling or level-low irq */ 389 - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0)); 389 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type0, 0); 390 390 /* trigger type is edge */ 391 - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1)); 391 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type1, 0); 392 392 /* single edge trigger */ 393 - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2)); 393 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type2, 0); 394 394 } 395 395 396 396 return 0;