Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A small set of fixes for problems found by smatch in new drivers that
we added this rc and a handful of driver fixes that came in during the
merge window"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
drivers: clk: st: Incorrect register offset used for lock_status
clk: mediatek: mt8173: Fix enabling of critical clocks
drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks
drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks
drivers: clk: st: Fix flexgen lock init
drivers: clk: st: Fix FSYN channel values
drivers: clk: st: Remove unused code
clk: qcom: Use parent rate when set rate to pixel RCG clock
clk: at91: do not leak resources
clk: stm32: Fix out-by-one error path in the index lookup
clk: iproc: fix bit manipulation arithmetic
clk: iproc: fix memory leak from clock name
+74
-50
+3
-1
drivers/clk/at91/clk-h32mx.c
+3
-1
drivers/clk/at91/clk-h32mx.c
+3
-1
drivers/clk/at91/clk-main.c
+3
-1
drivers/clk/at91/clk-main.c
···
171
171
irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
172
172
ret = request_irq(osc->irq, clk_main_osc_irq_handler,
173
173
IRQF_TRIGGER_HIGH, name, osc);
174
-
if (ret)
174
+
if (ret) {
175
+
kfree(osc);
175
176
return ERR_PTR(ret);
177
+
}
176
178
177
179
if (bypass)
178
180
pmc_write(pmc, AT91_CKGR_MOR,
+6
-2
drivers/clk/at91/clk-master.c
+6
-2
drivers/clk/at91/clk-master.c
···
165
165
irq_set_status_flags(master->irq, IRQ_NOAUTOEN);
166
166
ret = request_irq(master->irq, clk_master_irq_handler,
167
167
IRQF_TRIGGER_HIGH, "clk-master", master);
168
-
if (ret)
168
+
if (ret) {
169
+
kfree(master);
169
170
return ERR_PTR(ret);
171
+
}
170
172
171
173
clk = clk_register(NULL, &master->hw);
172
-
if (IS_ERR(clk))
174
+
if (IS_ERR(clk)) {
175
+
free_irq(master->irq, master);
173
176
kfree(master);
177
+
}
174
178
175
179
return clk;
176
180
}
+6
-2
drivers/clk/at91/clk-pll.c
+6
-2
drivers/clk/at91/clk-pll.c
···
346
346
irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
347
347
ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
348
348
id ? "clk-pllb" : "clk-plla", pll);
349
-
if (ret)
349
+
if (ret) {
350
+
kfree(pll);
350
351
return ERR_PTR(ret);
352
+
}
351
353
352
354
clk = clk_register(NULL, &pll->hw);
353
-
if (IS_ERR(clk))
355
+
if (IS_ERR(clk)) {
356
+
free_irq(pll->irq, pll);
354
357
kfree(pll);
358
+
}
355
359
356
360
return clk;
357
361
}
+6
-2
drivers/clk/at91/clk-system.c
+6
-2
drivers/clk/at91/clk-system.c
···
130
130
irq_set_status_flags(sys->irq, IRQ_NOAUTOEN);
131
131
ret = request_irq(sys->irq, clk_system_irq_handler,
132
132
IRQF_TRIGGER_HIGH, name, sys);
133
-
if (ret)
133
+
if (ret) {
134
+
kfree(sys);
134
135
return ERR_PTR(ret);
136
+
}
135
137
}
136
138
137
139
clk = clk_register(NULL, &sys->hw);
138
-
if (IS_ERR(clk))
140
+
if (IS_ERR(clk)) {
141
+
free_irq(sys->irq, sys);
139
142
kfree(sys);
143
+
}
140
144
141
145
return clk;
142
146
}
+6
-2
drivers/clk/at91/clk-utmi.c
+6
-2
drivers/clk/at91/clk-utmi.c
···
118
118
irq_set_status_flags(utmi->irq, IRQ_NOAUTOEN);
119
119
ret = request_irq(utmi->irq, clk_utmi_irq_handler,
120
120
IRQF_TRIGGER_HIGH, "clk-utmi", utmi);
121
-
if (ret)
121
+
if (ret) {
122
+
kfree(utmi);
122
123
return ERR_PTR(ret);
124
+
}
123
125
124
126
clk = clk_register(NULL, &utmi->hw);
125
-
if (IS_ERR(clk))
127
+
if (IS_ERR(clk)) {
128
+
free_irq(utmi->irq, utmi);
126
129
kfree(utmi);
130
+
}
127
131
128
132
return clk;
129
133
}
+1
-5
drivers/clk/bcm/clk-iproc-asiu.c
+1
-5
drivers/clk/bcm/clk-iproc-asiu.c
···
222
222
struct iproc_asiu_clk *asiu_clk;
223
223
const char *clk_name;
224
224
225
-
clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
226
-
if (WARN_ON(!clk_name))
227
-
goto err_clk_register;
228
-
229
225
ret = of_property_read_string_index(node, "clock-output-names",
230
226
i, &clk_name);
231
227
if (WARN_ON(ret))
···
255
259
256
260
err_clk_register:
257
261
for (i = 0; i < num_clks; i++)
258
-
kfree(asiu->clks[i].name);
262
+
clk_unregister(asiu->clk_data.clks[i]);
259
263
iounmap(asiu->gate_base);
260
264
261
265
err_iomap_gate:
+4
-9
drivers/clk/bcm/clk-iproc-pll.c
+4
-9
drivers/clk/bcm/clk-iproc-pll.c
···
366
366
val = readl(pll->pll_base + ctrl->ndiv_int.offset);
367
367
ndiv_int = (val >> ctrl->ndiv_int.shift) &
368
368
bit_mask(ctrl->ndiv_int.width);
369
-
ndiv = ndiv_int << ctrl->ndiv_int.shift;
369
+
ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift;
370
370
371
371
if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
372
372
val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
···
374
374
bit_mask(ctrl->ndiv_frac.width);
375
375
376
376
if (ndiv_frac != 0)
377
-
ndiv = (ndiv_int << ctrl->ndiv_int.shift) | ndiv_frac;
377
+
ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) |
378
+
ndiv_frac;
378
379
}
379
380
380
381
val = readl(pll->pll_base + ctrl->pdiv.offset);
···
656
655
memset(&init, 0, sizeof(init));
657
656
parent_name = node->name;
658
657
659
-
clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
660
-
if (WARN_ON(!clk_name))
661
-
goto err_clk_register;
662
-
663
658
ret = of_property_read_string_index(node, "clock-output-names",
664
659
i, &clk_name);
665
660
if (WARN_ON(ret))
···
687
690
return;
688
691
689
692
err_clk_register:
690
-
for (i = 0; i < num_clks; i++) {
691
-
kfree(pll->clks[i].name);
693
+
for (i = 0; i < num_clks; i++)
692
694
clk_unregister(pll->clk_data.clks[i]);
693
-
}
694
695
695
696
err_pll_register:
696
697
if (pll->asiu_base)
+1
-1
drivers/clk/clk-stm32f4.c
+1
-1
drivers/clk/clk-stm32f4.c
···
268
268
memcpy(table, stm32f42xx_gate_map, sizeof(table));
269
269
270
270
/* only bits set in table can be used as indices */
271
-
if (WARN_ON(secondary > 8 * sizeof(table) ||
271
+
if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
272
272
0 == (table[BIT_ULL_WORD(secondary)] &
273
273
BIT_ULL_MASK(secondary))))
274
274
return -EINVAL;
+21
-5
drivers/clk/mediatek/clk-mt8173.c
+21
-5
drivers/clk/mediatek/clk-mt8173.c
···
700
700
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
701
701
};
702
702
703
+
static struct clk_onecell_data *mt8173_top_clk_data __initdata;
704
+
static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
705
+
706
+
static void __init mtk_clk_enable_critical(void)
707
+
{
708
+
if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
709
+
return;
710
+
711
+
clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
712
+
clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
713
+
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
714
+
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
715
+
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
716
+
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
717
+
}
718
+
703
719
static void __init mtk_topckgen_init(struct device_node *node)
704
720
{
705
721
struct clk_onecell_data *clk_data;
···
728
712
return;
729
713
}
730
714
731
-
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
715
+
mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
732
716
733
717
mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
734
718
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
735
719
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
736
720
&mt8173_clk_lock, clk_data);
737
721
738
-
clk_prepare_enable(clk_data->clks[CLK_TOP_CCI400_SEL]);
739
-
740
722
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
741
723
if (r)
742
724
pr_err("%s(): could not register clock provider: %d\n",
743
725
__func__, r);
726
+
727
+
mtk_clk_enable_critical();
744
728
}
745
729
CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
746
730
···
834
818
{
835
819
struct clk_onecell_data *clk_data;
836
820
837
-
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
821
+
mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
838
822
if (!clk_data)
839
823
return;
840
824
841
825
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
842
826
843
-
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
827
+
mtk_clk_enable_critical();
844
828
}
845
829
CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
846
830
mtk_apmixedsys_init);
+3
-6
drivers/clk/qcom/clk-rcg2.c
+3
-6
drivers/clk/qcom/clk-rcg2.c
···
530
530
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
531
531
struct freq_tbl f = *rcg->freq_tbl;
532
532
const struct frac_entry *frac = frac_table_pixel;
533
-
unsigned long request, src_rate;
533
+
unsigned long request;
534
534
int delta = 100000;
535
535
u32 mask = BIT(rcg->hid_width) - 1;
536
536
u32 hid_div;
537
-
int index = qcom_find_src_index(hw, rcg->parent_map, f.src);
538
-
struct clk *parent = clk_get_parent_by_index(hw->clk, index);
539
537
540
538
for (; frac->num; frac++) {
541
539
request = (rate * frac->den) / frac->num;
542
540
543
-
src_rate = __clk_round_rate(parent, request);
544
-
if ((src_rate < (request - delta)) ||
545
-
(src_rate > (request + delta)))
541
+
if ((parent_rate < (request - delta)) ||
542
+
(parent_rate > (request + delta)))
546
543
continue;
547
544
548
545
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
+3
-1
drivers/clk/st/clk-flexgen.c
+3
-1
drivers/clk/st/clk-flexgen.c
···
190
190
191
191
init.name = name;
192
192
init.ops = &flexgen_ops;
193
-
init.flags = CLK_IS_BASIC | flexgen_flags;
193
+
init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | flexgen_flags;
194
194
init.parent_names = parent_names;
195
195
init.num_parents = num_parents;
196
196
···
302
302
rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
303
303
if (!rlock)
304
304
goto err;
305
+
306
+
spin_lock_init(rlock);
305
307
306
308
for (i = 0; i < clk_data->clk_num; i++) {
307
309
struct clk *clk;
+4
-8
drivers/clk/st/clkgen-fsyn.c
+4
-8
drivers/clk/st/clkgen-fsyn.c
···
340
340
CLKGEN_FIELD(0x30c, 0xf, 20),
341
341
CLKGEN_FIELD(0x310, 0xf, 20) },
342
342
.lockstatus_present = true,
343
-
.lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
343
+
.lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
344
344
.powerup_polarity = 1,
345
345
.standby_polarity = 1,
346
346
.pll_ops = &st_quadfs_pll_c32_ops,
···
489
489
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
490
490
u32 npda = CLKGEN_READ(pll, npda);
491
491
492
-
return !!npda;
492
+
return pll->data->powerup_polarity ? !npda : !!npda;
493
493
}
494
494
495
495
static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
···
635
635
636
636
init.name = name;
637
637
init.ops = quadfs->pll_ops;
638
-
init.flags = CLK_IS_BASIC;
638
+
init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
639
639
init.parent_names = &parent_name;
640
640
init.num_parents = 1;
641
641
···
774
774
if (fs->lock)
775
775
spin_lock_irqsave(fs->lock, flags);
776
776
777
-
CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
777
+
CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity);
778
778
779
779
if (fs->lock)
780
780
spin_unlock_irqrestore(fs->lock, flags);
···
1081
1081
{
1082
1082
.compatible = "st,stih407-quadfs660-D",
1083
1083
.data = &st_fs660c32_D_407
1084
-
},
1085
-
{
1086
-
.compatible = "st,stih407-quadfs660-D",
1087
-
.data = (void *)&st_fs660c32_D_407
1088
1084
},
1089
1085
{}
1090
1086
};
+6
-4
drivers/clk/st/clkgen-mux.c
+6
-4
drivers/clk/st/clkgen-mux.c
···
237
237
238
238
init.name = name;
239
239
init.ops = &clkgena_divmux_ops;
240
-
init.flags = CLK_IS_BASIC;
240
+
init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
241
241
init.parent_names = parent_names;
242
242
init.num_parents = num_parents;
243
243
···
513
513
0, &clk_name))
514
514
return;
515
515
516
-
clk = clk_register_divider_table(NULL, clk_name, parent_name, 0,
516
+
clk = clk_register_divider_table(NULL, clk_name, parent_name,
517
+
CLK_GET_RATE_NOCACHE,
517
518
reg + data->offset, data->shift, 1,
518
519
0, data->table, NULL);
519
520
if (IS_ERR(clk))
···
583
582
};
584
583
static struct clkgen_mux_data stih407_a9_mux_data = {
585
584
.offset = 0x1a4,
586
-
.shift = 1,
585
+
.shift = 0,
587
586
.width = 2,
588
587
};
589
588
···
787
786
&mux->hw, &clk_mux_ops,
788
787
&div->hw, &clk_divider_ops,
789
788
&gate->hw, &clk_gate_ops,
790
-
data->clk_flags);
789
+
data->clk_flags |
790
+
CLK_GET_RATE_NOCACHE);
791
791
if (IS_ERR(clk)) {
792
792
kfree(gate);
793
793
kfree(div);