tjh.dev / kernel
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clk: qcom: gcc-msm8660: use parent_hws/_data instead of parent_names

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220909105136.3733919-4-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson 4409ef7d 41872e9f

+164 -100
+164 -100
drivers/clk/qcom/gcc-msm8660.c
··· 34 34 .status_bit = 16, 35 35 .clkr.hw.init = &(struct clk_init_data){ 36 36 .name = "pll8", 37 - .parent_names = (const char *[]){ "pxo" }, 37 + .parent_data = &(const struct clk_parent_data){ 38 + .fw_name = "pxo", .name = "pxo_board", 39 + }, 38 40 .num_parents = 1, 39 41 .ops = &clk_pll_ops, 40 42 }, ··· 47 45 .enable_mask = BIT(8), 48 46 .hw.init = &(struct clk_init_data){ 49 47 .name = "pll8_vote", 50 - .parent_names = (const char *[]){ "pll8" }, 48 + .parent_hws = (const struct clk_hw*[]){ 49 + &pll8.clkr.hw 50 + }, 51 51 .num_parents = 1, 52 52 .ops = &clk_pll_vote_ops, 53 53 }, ··· 66 62 { P_PLL8, 3 } 67 63 }; 68 64 69 - static const char * const gcc_pxo_pll8[] = { 70 - "pxo", 71 - "pll8_vote", 65 + static const struct clk_parent_data gcc_pxo_pll8[] = { 66 + { .fw_name = "pxo", .name = "pxo_board" }, 67 + { .hw = &pll8_vote.hw }, 72 68 }; 73 69 74 70 static const struct parent_map gcc_pxo_pll8_cxo_map[] = { ··· 77 73 { P_CXO, 5 } 78 74 }; 79 75 80 - static const char * const gcc_pxo_pll8_cxo[] = { 81 - "pxo", 82 - "pll8_vote", 83 - "cxo", 76 + static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { 77 + { .fw_name = "pxo", .name = "pxo_board" }, 78 + { .hw = &pll8_vote.hw }, 79 + { .fw_name = "cxo", .name = "cxo_board" }, 84 80 }; 85 81 86 82 static struct freq_tbl clk_tbl_gsbi_uart[] = { ··· 126 122 .enable_mask = BIT(11), 127 123 .hw.init = &(struct clk_init_data){ 128 124 .name = "gsbi1_uart_src", 129 - .parent_names = gcc_pxo_pll8, 125 + .parent_data = gcc_pxo_pll8, 130 126 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 131 127 .ops = &clk_rcg_ops, 132 128 .flags = CLK_SET_PARENT_GATE, ··· 142 138 .enable_mask = BIT(9), 143 139 .hw.init = &(struct clk_init_data){ 144 140 .name = "gsbi1_uart_clk", 145 - .parent_names = (const char *[]){ 146 - "gsbi1_uart_src", 141 + .parent_hws = (const struct clk_hw*[]){ 142 + &gsbi1_uart_src.clkr.hw 147 143 }, 148 144 .num_parents = 1, 149 145 .ops = &clk_branch_ops, ··· 177 173 .enable_mask = BIT(11), 178 174 .hw.init = &(struct clk_init_data){ 179 175 .name = "gsbi2_uart_src", 180 - .parent_names = gcc_pxo_pll8, 176 + .parent_data = gcc_pxo_pll8, 181 177 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 182 178 .ops = &clk_rcg_ops, 183 179 .flags = CLK_SET_PARENT_GATE, ··· 193 189 .enable_mask = BIT(9), 194 190 .hw.init = &(struct clk_init_data){ 195 191 .name = "gsbi2_uart_clk", 196 - .parent_names = (const char *[]){ 197 - "gsbi2_uart_src", 192 + .parent_hws = (const struct clk_hw*[]){ 193 + &gsbi2_uart_src.clkr.hw 198 194 }, 199 195 .num_parents = 1, 200 196 .ops = &clk_branch_ops, ··· 228 224 .enable_mask = BIT(11), 229 225 .hw.init = &(struct clk_init_data){ 230 226 .name = "gsbi3_uart_src", 231 - .parent_names = gcc_pxo_pll8, 227 + .parent_data = gcc_pxo_pll8, 232 228 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 233 229 .ops = &clk_rcg_ops, 234 230 .flags = CLK_SET_PARENT_GATE, ··· 244 240 .enable_mask = BIT(9), 245 241 .hw.init = &(struct clk_init_data){ 246 242 .name = "gsbi3_uart_clk", 247 - .parent_names = (const char *[]){ 248 - "gsbi3_uart_src", 243 + .parent_hws = (const struct clk_hw*[]){ 244 + &gsbi3_uart_src.clkr.hw 249 245 }, 250 246 .num_parents = 1, 251 247 .ops = &clk_branch_ops, ··· 279 275 .enable_mask = BIT(11), 280 276 .hw.init = &(struct clk_init_data){ 281 277 .name = "gsbi4_uart_src", 282 - .parent_names = gcc_pxo_pll8, 278 + .parent_data = gcc_pxo_pll8, 283 279 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 284 280 .ops = &clk_rcg_ops, 285 281 .flags = CLK_SET_PARENT_GATE, ··· 295 291 .enable_mask = BIT(9), 296 292 .hw.init = &(struct clk_init_data){ 297 293 .name = "gsbi4_uart_clk", 298 - .parent_names = (const char *[]){ 299 - "gsbi4_uart_src", 294 + .parent_hws = (const struct clk_hw*[]){ 295 + &gsbi4_uart_src.clkr.hw 300 296 }, 301 297 .num_parents = 1, 302 298 .ops = &clk_branch_ops, ··· 330 326 .enable_mask = BIT(11), 331 327 .hw.init = &(struct clk_init_data){ 332 328 .name = "gsbi5_uart_src", 333 - .parent_names = gcc_pxo_pll8, 329 + .parent_data = gcc_pxo_pll8, 334 330 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 335 331 .ops = &clk_rcg_ops, 336 332 .flags = CLK_SET_PARENT_GATE, ··· 346 342 .enable_mask = BIT(9), 347 343 .hw.init = &(struct clk_init_data){ 348 344 .name = "gsbi5_uart_clk", 349 - .parent_names = (const char *[]){ 350 - "gsbi5_uart_src", 345 + .parent_hws = (const struct clk_hw*[]){ 346 + &gsbi5_uart_src.clkr.hw 351 347 }, 352 348 .num_parents = 1, 353 349 .ops = &clk_branch_ops, ··· 381 377 .enable_mask = BIT(11), 382 378 .hw.init = &(struct clk_init_data){ 383 379 .name = "gsbi6_uart_src", 384 - .parent_names = gcc_pxo_pll8, 380 + .parent_data = gcc_pxo_pll8, 385 381 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 386 382 .ops = &clk_rcg_ops, 387 383 .flags = CLK_SET_PARENT_GATE, ··· 397 393 .enable_mask = BIT(9), 398 394 .hw.init = &(struct clk_init_data){ 399 395 .name = "gsbi6_uart_clk", 400 - .parent_names = (const char *[]){ 401 - "gsbi6_uart_src", 396 + .parent_hws = (const struct clk_hw*[]){ 397 + &gsbi6_uart_src.clkr.hw 402 398 }, 403 399 .num_parents = 1, 404 400 .ops = &clk_branch_ops, ··· 432 428 .enable_mask = BIT(11), 433 429 .hw.init = &(struct clk_init_data){ 434 430 .name = "gsbi7_uart_src", 435 - .parent_names = gcc_pxo_pll8, 431 + .parent_data = gcc_pxo_pll8, 436 432 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 437 433 .ops = &clk_rcg_ops, 438 434 .flags = CLK_SET_PARENT_GATE, ··· 448 444 .enable_mask = BIT(9), 449 445 .hw.init = &(struct clk_init_data){ 450 446 .name = "gsbi7_uart_clk", 451 - .parent_names = (const char *[]){ 452 - "gsbi7_uart_src", 447 + .parent_hws = (const struct clk_hw*[]){ 448 + &gsbi7_uart_src.clkr.hw 453 449 }, 454 450 .num_parents = 1, 455 451 .ops = &clk_branch_ops, ··· 483 479 .enable_mask = BIT(11), 484 480 .hw.init = &(struct clk_init_data){ 485 481 .name = "gsbi8_uart_src", 486 - .parent_names = gcc_pxo_pll8, 482 + .parent_data = gcc_pxo_pll8, 487 483 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 488 484 .ops = &clk_rcg_ops, 489 485 .flags = CLK_SET_PARENT_GATE, ··· 499 495 .enable_mask = BIT(9), 500 496 .hw.init = &(struct clk_init_data){ 501 497 .name = "gsbi8_uart_clk", 502 - .parent_names = (const char *[]){ "gsbi8_uart_src" }, 498 + .parent_hws = (const struct clk_hw*[]){ 499 + &gsbi8_uart_src.clkr.hw 500 + }, 503 501 .num_parents = 1, 504 502 .ops = &clk_branch_ops, 505 503 .flags = CLK_SET_RATE_PARENT, ··· 534 528 .enable_mask = BIT(11), 535 529 .hw.init = &(struct clk_init_data){ 536 530 .name = "gsbi9_uart_src", 537 - .parent_names = gcc_pxo_pll8, 531 + .parent_data = gcc_pxo_pll8, 538 532 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 539 533 .ops = &clk_rcg_ops, 540 534 .flags = CLK_SET_PARENT_GATE, ··· 550 544 .enable_mask = BIT(9), 551 545 .hw.init = &(struct clk_init_data){ 552 546 .name = "gsbi9_uart_clk", 553 - .parent_names = (const char *[]){ "gsbi9_uart_src" }, 547 + .parent_hws = (const struct clk_hw*[]){ 548 + &gsbi9_uart_src.clkr.hw 549 + }, 554 550 .num_parents = 1, 555 551 .ops = &clk_branch_ops, 556 552 .flags = CLK_SET_RATE_PARENT, ··· 585 577 .enable_mask = BIT(11), 586 578 .hw.init = &(struct clk_init_data){ 587 579 .name = "gsbi10_uart_src", 588 - .parent_names = gcc_pxo_pll8, 580 + .parent_data = gcc_pxo_pll8, 589 581 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 590 582 .ops = &clk_rcg_ops, 591 583 .flags = CLK_SET_PARENT_GATE, ··· 601 593 .enable_mask = BIT(9), 602 594 .hw.init = &(struct clk_init_data){ 603 595 .name = "gsbi10_uart_clk", 604 - .parent_names = (const char *[]){ "gsbi10_uart_src" }, 596 + .parent_hws = (const struct clk_hw*[]){ 597 + &gsbi10_uart_src.clkr.hw 598 + }, 605 599 .num_parents = 1, 606 600 .ops = &clk_branch_ops, 607 601 .flags = CLK_SET_RATE_PARENT, ··· 636 626 .enable_mask = BIT(11), 637 627 .hw.init = &(struct clk_init_data){ 638 628 .name = "gsbi11_uart_src", 639 - .parent_names = gcc_pxo_pll8, 629 + .parent_data = gcc_pxo_pll8, 640 630 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 641 631 .ops = &clk_rcg_ops, 642 632 .flags = CLK_SET_PARENT_GATE, ··· 652 642 .enable_mask = BIT(9), 653 643 .hw.init = &(struct clk_init_data){ 654 644 .name = "gsbi11_uart_clk", 655 - .parent_names = (const char *[]){ "gsbi11_uart_src" }, 645 + .parent_hws = (const struct clk_hw*[]){ 646 + &gsbi11_uart_src.clkr.hw 647 + }, 656 648 .num_parents = 1, 657 649 .ops = &clk_branch_ops, 658 650 .flags = CLK_SET_RATE_PARENT, ··· 687 675 .enable_mask = BIT(11), 688 676 .hw.init = &(struct clk_init_data){ 689 677 .name = "gsbi12_uart_src", 690 - .parent_names = gcc_pxo_pll8, 678 + .parent_data = gcc_pxo_pll8, 691 679 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 692 680 .ops = &clk_rcg_ops, 693 681 .flags = CLK_SET_PARENT_GATE, ··· 703 691 .enable_mask = BIT(9), 704 692 .hw.init = &(struct clk_init_data){ 705 693 .name = "gsbi12_uart_clk", 706 - .parent_names = (const char *[]){ "gsbi12_uart_src" }, 694 + .parent_hws = (const struct clk_hw*[]){ 695 + &gsbi12_uart_src.clkr.hw 696 + }, 707 697 .num_parents = 1, 708 698 .ops = &clk_branch_ops, 709 699 .flags = CLK_SET_RATE_PARENT, ··· 751 737 .enable_mask = BIT(11), 752 738 .hw.init = &(struct clk_init_data){ 753 739 .name = "gsbi1_qup_src", 754 - .parent_names = gcc_pxo_pll8, 740 + .parent_data = gcc_pxo_pll8, 755 741 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 756 742 .ops = &clk_rcg_ops, 757 743 .flags = CLK_SET_PARENT_GATE, ··· 767 753 .enable_mask = BIT(9), 768 754 .hw.init = &(struct clk_init_data){ 769 755 .name = "gsbi1_qup_clk", 770 - .parent_names = (const char *[]){ "gsbi1_qup_src" }, 756 + .parent_hws = (const struct clk_hw*[]){ 757 + &gsbi1_qup_src.clkr.hw 758 + }, 771 759 .num_parents = 1, 772 760 .ops = &clk_branch_ops, 773 761 .flags = CLK_SET_RATE_PARENT, ··· 802 786 .enable_mask = BIT(11), 803 787 .hw.init = &(struct clk_init_data){ 804 788 .name = "gsbi2_qup_src", 805 - .parent_names = gcc_pxo_pll8, 789 + .parent_data = gcc_pxo_pll8, 806 790 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 807 791 .ops = &clk_rcg_ops, 808 792 .flags = CLK_SET_PARENT_GATE, ··· 818 802 .enable_mask = BIT(9), 819 803 .hw.init = &(struct clk_init_data){ 820 804 .name = "gsbi2_qup_clk", 821 - .parent_names = (const char *[]){ "gsbi2_qup_src" }, 805 + .parent_hws = (const struct clk_hw*[]){ 806 + &gsbi2_qup_src.clkr.hw 807 + }, 822 808 .num_parents = 1, 823 809 .ops = &clk_branch_ops, 824 810 .flags = CLK_SET_RATE_PARENT, ··· 853 835 .enable_mask = BIT(11), 854 836 .hw.init = &(struct clk_init_data){ 855 837 .name = "gsbi3_qup_src", 856 - .parent_names = gcc_pxo_pll8, 838 + .parent_data = gcc_pxo_pll8, 857 839 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 858 840 .ops = &clk_rcg_ops, 859 841 .flags = CLK_SET_PARENT_GATE, ··· 869 851 .enable_mask = BIT(9), 870 852 .hw.init = &(struct clk_init_data){ 871 853 .name = "gsbi3_qup_clk", 872 - .parent_names = (const char *[]){ "gsbi3_qup_src" }, 854 + .parent_hws = (const struct clk_hw*[]){ 855 + &gsbi3_qup_src.clkr.hw 856 + }, 873 857 .num_parents = 1, 874 858 .ops = &clk_branch_ops, 875 859 .flags = CLK_SET_RATE_PARENT, ··· 904 884 .enable_mask = BIT(11), 905 885 .hw.init = &(struct clk_init_data){ 906 886 .name = "gsbi4_qup_src", 907 - .parent_names = gcc_pxo_pll8, 887 + .parent_data = gcc_pxo_pll8, 908 888 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 909 889 .ops = &clk_rcg_ops, 910 890 .flags = CLK_SET_PARENT_GATE, ··· 920 900 .enable_mask = BIT(9), 921 901 .hw.init = &(struct clk_init_data){ 922 902 .name = "gsbi4_qup_clk", 923 - .parent_names = (const char *[]){ "gsbi4_qup_src" }, 903 + .parent_hws = (const struct clk_hw*[]){ 904 + &gsbi4_qup_src.clkr.hw 905 + }, 924 906 .num_parents = 1, 925 907 .ops = &clk_branch_ops, 926 908 .flags = CLK_SET_RATE_PARENT, ··· 955 933 .enable_mask = BIT(11), 956 934 .hw.init = &(struct clk_init_data){ 957 935 .name = "gsbi5_qup_src", 958 - .parent_names = gcc_pxo_pll8, 936 + .parent_data = gcc_pxo_pll8, 959 937 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 960 938 .ops = &clk_rcg_ops, 961 939 .flags = CLK_SET_PARENT_GATE, ··· 971 949 .enable_mask = BIT(9), 972 950 .hw.init = &(struct clk_init_data){ 973 951 .name = "gsbi5_qup_clk", 974 - .parent_names = (const char *[]){ "gsbi5_qup_src" }, 952 + .parent_hws = (const struct clk_hw*[]){ 953 + &gsbi5_qup_src.clkr.hw 954 + }, 975 955 .num_parents = 1, 976 956 .ops = &clk_branch_ops, 977 957 .flags = CLK_SET_RATE_PARENT, ··· 1006 982 .enable_mask = BIT(11), 1007 983 .hw.init = &(struct clk_init_data){ 1008 984 .name = "gsbi6_qup_src", 1009 - .parent_names = gcc_pxo_pll8, 985 + .parent_data = gcc_pxo_pll8, 1010 986 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1011 987 .ops = &clk_rcg_ops, 1012 988 .flags = CLK_SET_PARENT_GATE, ··· 1022 998 .enable_mask = BIT(9), 1023 999 .hw.init = &(struct clk_init_data){ 1024 1000 .name = "gsbi6_qup_clk", 1025 - .parent_names = (const char *[]){ "gsbi6_qup_src" }, 1001 + .parent_hws = (const struct clk_hw*[]){ 1002 + &gsbi6_qup_src.clkr.hw 1003 + }, 1026 1004 .num_parents = 1, 1027 1005 .ops = &clk_branch_ops, 1028 1006 .flags = CLK_SET_RATE_PARENT, ··· 1057 1031 .enable_mask = BIT(11), 1058 1032 .hw.init = &(struct clk_init_data){ 1059 1033 .name = "gsbi7_qup_src", 1060 - .parent_names = gcc_pxo_pll8, 1034 + .parent_data = gcc_pxo_pll8, 1061 1035 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1062 1036 .ops = &clk_rcg_ops, 1063 1037 .flags = CLK_SET_PARENT_GATE, ··· 1073 1047 .enable_mask = BIT(9), 1074 1048 .hw.init = &(struct clk_init_data){ 1075 1049 .name = "gsbi7_qup_clk", 1076 - .parent_names = (const char *[]){ "gsbi7_qup_src" }, 1050 + .parent_hws = (const struct clk_hw*[]){ 1051 + &gsbi7_qup_src.clkr.hw 1052 + }, 1077 1053 .num_parents = 1, 1078 1054 .ops = &clk_branch_ops, 1079 1055 .flags = CLK_SET_RATE_PARENT, ··· 1108 1080 .enable_mask = BIT(11), 1109 1081 .hw.init = &(struct clk_init_data){ 1110 1082 .name = "gsbi8_qup_src", 1111 - .parent_names = gcc_pxo_pll8, 1083 + .parent_data = gcc_pxo_pll8, 1112 1084 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1113 1085 .ops = &clk_rcg_ops, 1114 1086 .flags = CLK_SET_PARENT_GATE, ··· 1124 1096 .enable_mask = BIT(9), 1125 1097 .hw.init = &(struct clk_init_data){ 1126 1098 .name = "gsbi8_qup_clk", 1127 - .parent_names = (const char *[]){ "gsbi8_qup_src" }, 1099 + .parent_hws = (const struct clk_hw*[]){ 1100 + &gsbi8_qup_src.clkr.hw 1101 + }, 1128 1102 .num_parents = 1, 1129 1103 .ops = &clk_branch_ops, 1130 1104 .flags = CLK_SET_RATE_PARENT, ··· 1159 1129 .enable_mask = BIT(11), 1160 1130 .hw.init = &(struct clk_init_data){ 1161 1131 .name = "gsbi9_qup_src", 1162 - .parent_names = gcc_pxo_pll8, 1132 + .parent_data = gcc_pxo_pll8, 1163 1133 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1164 1134 .ops = &clk_rcg_ops, 1165 1135 .flags = CLK_SET_PARENT_GATE, ··· 1175 1145 .enable_mask = BIT(9), 1176 1146 .hw.init = &(struct clk_init_data){ 1177 1147 .name = "gsbi9_qup_clk", 1178 - .parent_names = (const char *[]){ "gsbi9_qup_src" }, 1148 + .parent_hws = (const struct clk_hw*[]){ 1149 + &gsbi9_qup_src.clkr.hw 1150 + }, 1179 1151 .num_parents = 1, 1180 1152 .ops = &clk_branch_ops, 1181 1153 .flags = CLK_SET_RATE_PARENT, ··· 1210 1178 .enable_mask = BIT(11), 1211 1179 .hw.init = &(struct clk_init_data){ 1212 1180 .name = "gsbi10_qup_src", 1213 - .parent_names = gcc_pxo_pll8, 1181 + .parent_data = gcc_pxo_pll8, 1214 1182 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1215 1183 .ops = &clk_rcg_ops, 1216 1184 .flags = CLK_SET_PARENT_GATE, ··· 1226 1194 .enable_mask = BIT(9), 1227 1195 .hw.init = &(struct clk_init_data){ 1228 1196 .name = "gsbi10_qup_clk", 1229 - .parent_names = (const char *[]){ "gsbi10_qup_src" }, 1197 + .parent_hws = (const struct clk_hw*[]){ 1198 + &gsbi10_qup_src.clkr.hw 1199 + }, 1230 1200 .num_parents = 1, 1231 1201 .ops = &clk_branch_ops, 1232 1202 .flags = CLK_SET_RATE_PARENT, ··· 1261 1227 .enable_mask = BIT(11), 1262 1228 .hw.init = &(struct clk_init_data){ 1263 1229 .name = "gsbi11_qup_src", 1264 - .parent_names = gcc_pxo_pll8, 1230 + .parent_data = gcc_pxo_pll8, 1265 1231 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1266 1232 .ops = &clk_rcg_ops, 1267 1233 .flags = CLK_SET_PARENT_GATE, ··· 1277 1243 .enable_mask = BIT(9), 1278 1244 .hw.init = &(struct clk_init_data){ 1279 1245 .name = "gsbi11_qup_clk", 1280 - .parent_names = (const char *[]){ "gsbi11_qup_src" }, 1246 + .parent_hws = (const struct clk_hw*[]){ 1247 + &gsbi11_qup_src.clkr.hw 1248 + }, 1281 1249 .num_parents = 1, 1282 1250 .ops = &clk_branch_ops, 1283 1251 .flags = CLK_SET_RATE_PARENT, ··· 1312 1276 .enable_mask = BIT(11), 1313 1277 .hw.init = &(struct clk_init_data){ 1314 1278 .name = "gsbi12_qup_src", 1315 - .parent_names = gcc_pxo_pll8, 1279 + .parent_data = gcc_pxo_pll8, 1316 1280 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1317 1281 .ops = &clk_rcg_ops, 1318 1282 .flags = CLK_SET_PARENT_GATE, ··· 1328 1292 .enable_mask = BIT(9), 1329 1293 .hw.init = &(struct clk_init_data){ 1330 1294 .name = "gsbi12_qup_clk", 1331 - .parent_names = (const char *[]){ "gsbi12_qup_src" }, 1295 + .parent_hws = (const struct clk_hw*[]){ 1296 + &gsbi12_qup_src.clkr.hw 1297 + }, 1332 1298 .num_parents = 1, 1333 1299 .ops = &clk_branch_ops, 1334 1300 .flags = CLK_SET_RATE_PARENT, ··· 1376 1338 .enable_mask = BIT(11), 1377 1339 .hw.init = &(struct clk_init_data){ 1378 1340 .name = "gp0_src", 1379 - .parent_names = gcc_pxo_pll8_cxo, 1341 + .parent_data = gcc_pxo_pll8_cxo, 1380 1342 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1381 1343 .ops = &clk_rcg_ops, 1382 1344 .flags = CLK_SET_PARENT_GATE, ··· 1392 1354 .enable_mask = BIT(9), 1393 1355 .hw.init = &(struct clk_init_data){ 1394 1356 .name = "gp0_clk", 1395 - .parent_names = (const char *[]){ "gp0_src" }, 1357 + .parent_hws = (const struct clk_hw*[]){ 1358 + &gp0_src.clkr.hw 1359 + }, 1396 1360 .num_parents = 1, 1397 1361 .ops = &clk_branch_ops, 1398 1362 .flags = CLK_SET_RATE_PARENT, ··· 1427 1387 .enable_mask = BIT(11), 1428 1388 .hw.init = &(struct clk_init_data){ 1429 1389 .name = "gp1_src", 1430 - .parent_names = gcc_pxo_pll8_cxo, 1390 + .parent_data = gcc_pxo_pll8_cxo, 1431 1391 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1432 1392 .ops = &clk_rcg_ops, 1433 1393 .flags = CLK_SET_RATE_GATE, ··· 1443 1403 .enable_mask = BIT(9), 1444 1404 .hw.init = &(struct clk_init_data){ 1445 1405 .name = "gp1_clk", 1446 - .parent_names = (const char *[]){ "gp1_src" }, 1406 + .parent_hws = (const struct clk_hw*[]){ 1407 + &gp1_src.clkr.hw 1408 + }, 1447 1409 .num_parents = 1, 1448 1410 .ops = &clk_branch_ops, 1449 1411 .flags = CLK_SET_RATE_PARENT, ··· 1478 1436 .enable_mask = BIT(11), 1479 1437 .hw.init = &(struct clk_init_data){ 1480 1438 .name = "gp2_src", 1481 - .parent_names = gcc_pxo_pll8_cxo, 1439 + .parent_data = gcc_pxo_pll8_cxo, 1482 1440 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1483 1441 .ops = &clk_rcg_ops, 1484 1442 .flags = CLK_SET_RATE_GATE, ··· 1494 1452 .enable_mask = BIT(9), 1495 1453 .hw.init = &(struct clk_init_data){ 1496 1454 .name = "gp2_clk", 1497 - .parent_names = (const char *[]){ "gp2_src" }, 1455 + .parent_hws = (const struct clk_hw*[]){ 1456 + &gp2_src.clkr.hw 1457 + }, 1498 1458 .num_parents = 1, 1499 1459 .ops = &clk_branch_ops, 1500 1460 .flags = CLK_SET_RATE_PARENT, ··· 1532 1488 .clkr.hw = { 1533 1489 .init = &(struct clk_init_data){ 1534 1490 .name = "prng_src", 1535 - .parent_names = gcc_pxo_pll8, 1491 + .parent_data = gcc_pxo_pll8, 1536 1492 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1537 1493 .ops = &clk_rcg_ops, 1538 1494 }, ··· 1548 1504 .enable_mask = BIT(10), 1549 1505 .hw.init = &(struct clk_init_data){ 1550 1506 .name = "prng_clk", 1551 - .parent_names = (const char *[]){ "prng_src" }, 1507 + .parent_hws = (const struct clk_hw*[]){ 1508 + &prng_src.clkr.hw 1509 + }, 1552 1510 .num_parents = 1, 1553 1511 .ops = &clk_branch_ops, 1554 1512 }, ··· 1593 1547 .enable_mask = BIT(11), 1594 1548 .hw.init = &(struct clk_init_data){ 1595 1549 .name = "sdc1_src", 1596 - .parent_names = gcc_pxo_pll8, 1550 + .parent_data = gcc_pxo_pll8, 1597 1551 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1598 1552 .ops = &clk_rcg_ops, 1599 1553 }, ··· 1608 1562 .enable_mask = BIT(9), 1609 1563 .hw.init = &(struct clk_init_data){ 1610 1564 .name = "sdc1_clk", 1611 - .parent_names = (const char *[]){ "sdc1_src" }, 1565 + .parent_hws = (const struct clk_hw*[]){ 1566 + &sdc1_src.clkr.hw 1567 + }, 1612 1568 .num_parents = 1, 1613 1569 .ops = &clk_branch_ops, 1614 1570 .flags = CLK_SET_RATE_PARENT, ··· 1643 1595 .enable_mask = BIT(11), 1644 1596 .hw.init = &(struct clk_init_data){ 1645 1597 .name = "sdc2_src", 1646 - .parent_names = gcc_pxo_pll8, 1598 + .parent_data = gcc_pxo_pll8, 1647 1599 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1648 1600 .ops = &clk_rcg_ops, 1649 1601 }, ··· 1658 1610 .enable_mask = BIT(9), 1659 1611 .hw.init = &(struct clk_init_data){ 1660 1612 .name = "sdc2_clk", 1661 - .parent_names = (const char *[]){ "sdc2_src" }, 1613 + .parent_hws = (const struct clk_hw*[]){ 1614 + &sdc2_src.clkr.hw 1615 + }, 1662 1616 .num_parents = 1, 1663 1617 .ops = &clk_branch_ops, 1664 1618 .flags = CLK_SET_RATE_PARENT, ··· 1693 1643 .enable_mask = BIT(11), 1694 1644 .hw.init = &(struct clk_init_data){ 1695 1645 .name = "sdc3_src", 1696 - .parent_names = gcc_pxo_pll8, 1646 + .parent_data = gcc_pxo_pll8, 1697 1647 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1698 1648 .ops = &clk_rcg_ops, 1699 1649 }, ··· 1708 1658 .enable_mask = BIT(9), 1709 1659 .hw.init = &(struct clk_init_data){ 1710 1660 .name = "sdc3_clk", 1711 - .parent_names = (const char *[]){ "sdc3_src" }, 1661 + .parent_hws = (const struct clk_hw*[]){ 1662 + &sdc3_src.clkr.hw 1663 + }, 1712 1664 .num_parents = 1, 1713 1665 .ops = &clk_branch_ops, 1714 1666 .flags = CLK_SET_RATE_PARENT, ··· 1743 1691 .enable_mask = BIT(11), 1744 1692 .hw.init = &(struct clk_init_data){ 1745 1693 .name = "sdc4_src", 1746 - .parent_names = gcc_pxo_pll8, 1694 + .parent_data = gcc_pxo_pll8, 1747 1695 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1748 1696 .ops = &clk_rcg_ops, 1749 1697 }, ··· 1758 1706 .enable_mask = BIT(9), 1759 1707 .hw.init = &(struct clk_init_data){ 1760 1708 .name = "sdc4_clk", 1761 - .parent_names = (const char *[]){ "sdc4_src" }, 1709 + .parent_hws = (const struct clk_hw*[]){ 1710 + &sdc4_src.clkr.hw 1711 + }, 1762 1712 .num_parents = 1, 1763 1713 .ops = &clk_branch_ops, 1764 1714 .flags = CLK_SET_RATE_PARENT, ··· 1793 1739 .enable_mask = BIT(11), 1794 1740 .hw.init = &(struct clk_init_data){ 1795 1741 .name = "sdc5_src", 1796 - .parent_names = gcc_pxo_pll8, 1742 + .parent_data = gcc_pxo_pll8, 1797 1743 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1798 1744 .ops = &clk_rcg_ops, 1799 1745 }, ··· 1808 1754 .enable_mask = BIT(9), 1809 1755 .hw.init = &(struct clk_init_data){ 1810 1756 .name = "sdc5_clk", 1811 - .parent_names = (const char *[]){ "sdc5_src" }, 1757 + .parent_hws = (const struct clk_hw*[]){ 1758 + &sdc5_src.clkr.hw 1759 + }, 1812 1760 .num_parents = 1, 1813 1761 .ops = &clk_branch_ops, 1814 1762 .flags = CLK_SET_RATE_PARENT, ··· 1848 1792 .enable_mask = BIT(11), 1849 1793 .hw.init = &(struct clk_init_data){ 1850 1794 .name = "tsif_ref_src", 1851 - .parent_names = gcc_pxo_pll8, 1795 + .parent_data = gcc_pxo_pll8, 1852 1796 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1853 1797 .ops = &clk_rcg_ops, 1854 1798 .flags = CLK_SET_RATE_GATE, ··· 1864 1808 .enable_mask = BIT(9), 1865 1809 .hw.init = &(struct clk_init_data){ 1866 1810 .name = "tsif_ref_clk", 1867 - .parent_names = (const char *[]){ "tsif_ref_src" }, 1811 + .parent_hws = (const struct clk_hw*[]){ 1812 + &tsif_ref_src.clkr.hw 1813 + }, 1868 1814 .num_parents = 1, 1869 1815 .ops = &clk_branch_ops, 1870 1816 .flags = CLK_SET_RATE_PARENT, ··· 1904 1846 .enable_mask = BIT(11), 1905 1847 .hw.init = &(struct clk_init_data){ 1906 1848 .name = "usb_hs1_xcvr_src", 1907 - .parent_names = gcc_pxo_pll8, 1849 + .parent_data = gcc_pxo_pll8, 1908 1850 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1909 1851 .ops = &clk_rcg_ops, 1910 1852 .flags = CLK_SET_RATE_GATE, ··· 1920 1862 .enable_mask = BIT(9), 1921 1863 .hw.init = &(struct clk_init_data){ 1922 1864 .name = "usb_hs1_xcvr_clk", 1923 - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 1865 + .parent_hws = (const struct clk_hw*[]){ 1866 + &usb_hs1_xcvr_src.clkr.hw 1867 + }, 1924 1868 .num_parents = 1, 1925 1869 .ops = &clk_branch_ops, 1926 1870 .flags = CLK_SET_RATE_PARENT, ··· 1955 1895 .enable_mask = BIT(11), 1956 1896 .hw.init = &(struct clk_init_data){ 1957 1897 .name = "usb_fs1_xcvr_fs_src", 1958 - .parent_names = gcc_pxo_pll8, 1898 + .parent_data = gcc_pxo_pll8, 1959 1899 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1960 1900 .ops = &clk_rcg_ops, 1961 1901 .flags = CLK_SET_RATE_GATE, 1962 1902 }, 1963 1903 } 1964 1904 }; 1965 - 1966 - static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; 1967 1905 1968 1906 static struct clk_branch usb_fs1_xcvr_fs_clk = { 1969 1907 .halt_reg = 0x2fcc, ··· 1971 1913 .enable_mask = BIT(9), 1972 1914 .hw.init = &(struct clk_init_data){ 1973 1915 .name = "usb_fs1_xcvr_fs_clk", 1974 - .parent_names = usb_fs1_xcvr_fs_src_p, 1975 - .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), 1916 + .parent_hws = (const struct clk_hw*[]){ 1917 + &usb_fs1_xcvr_fs_src.clkr.hw, 1918 + }, 1919 + .num_parents = 1, 1976 1920 .ops = &clk_branch_ops, 1977 1921 .flags = CLK_SET_RATE_PARENT, 1978 1922 }, ··· 1988 1928 .enable_reg = 0x296c, 1989 1929 .enable_mask = BIT(4), 1990 1930 .hw.init = &(struct clk_init_data){ 1991 - .parent_names = usb_fs1_xcvr_fs_src_p, 1992 - .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), 1931 + .parent_hws = (const struct clk_hw*[]){ 1932 + &usb_fs1_xcvr_fs_src.clkr.hw, 1933 + }, 1934 + .num_parents = 1, 1993 1935 .name = "usb_fs1_system_clk", 1994 1936 .ops = &clk_branch_ops, 1995 1937 .flags = CLK_SET_RATE_PARENT, ··· 2024 1962 .enable_mask = BIT(11), 2025 1963 .hw.init = &(struct clk_init_data){ 2026 1964 .name = "usb_fs2_xcvr_fs_src", 2027 - .parent_names = gcc_pxo_pll8, 1965 + .parent_data = gcc_pxo_pll8, 2028 1966 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2029 1967 .ops = &clk_rcg_ops, 2030 1968 .flags = CLK_SET_RATE_GATE, 2031 1969 }, 2032 1970 } 2033 1971 }; 2034 - 2035 - static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; 2036 1972 2037 1973 static struct clk_branch usb_fs2_xcvr_fs_clk = { 2038 1974 .halt_reg = 0x2fcc, ··· 2040 1980 .enable_mask = BIT(9), 2041 1981 .hw.init = &(struct clk_init_data){ 2042 1982 .name = "usb_fs2_xcvr_fs_clk", 2043 - .parent_names = usb_fs2_xcvr_fs_src_p, 2044 - .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), 1983 + .parent_hws = (const struct clk_hw*[]){ 1984 + &usb_fs2_xcvr_fs_src.clkr.hw, 1985 + }, 1986 + .num_parents = 1, 2045 1987 .ops = &clk_branch_ops, 2046 1988 .flags = CLK_SET_RATE_PARENT, 2047 1989 }, ··· 2058 1996 .enable_mask = BIT(4), 2059 1997 .hw.init = &(struct clk_init_data){ 2060 1998 .name = "usb_fs2_system_clk", 2061 - .parent_names = usb_fs2_xcvr_fs_src_p, 2062 - .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), 1999 + .parent_hws = (const struct clk_hw*[]){ 2000 + &usb_fs2_xcvr_fs_src.clkr.hw, 2001 + }, 2002 + .num_parents = 1, 2063 2003 .ops = &clk_branch_ops, 2064 2004 .flags = CLK_SET_RATE_PARENT, 2065 2005 },