Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add xcc specific functions
Add more XCC specific functions and use them from IP block functions.
RLC, CP functions are further split to have xcc specific versions.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lijo Lazar
and committed by
Alex Deucher
44b5cf2e
880f8b3f
+182
-125
+182
-125
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+182
-125
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
···
955
955
}
956
956
}
957
957
958
-
static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
958
+
static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,
959
+
int xcc_id)
959
960
{
960
961
u32 tmp;
961
-
int i, j, num_xcc;
962
-
963
-
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
964
-
965
-
gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
966
-
adev->gfx.config.db_debug2 = RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);
962
+
int i;
967
963
968
964
/* XXX SH_MEM regs */
969
965
/* where to put LDS, scratch, GPUVM in FSA64 space */
970
966
mutex_lock(&adev->srbm_mutex);
971
967
for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
972
-
for (j = 0; j < num_xcc; j++) {
973
-
soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, j));
974
-
/* CP and shaders */
975
-
if (i == 0) {
976
-
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
977
-
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
978
-
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
979
-
!!adev->gmc.noretry);
980
-
WREG32_SOC15_RLC(GC, GET_INST(GC, j), regSH_MEM_CONFIG, tmp);
981
-
WREG32_SOC15_RLC(GC, GET_INST(GC, j), regSH_MEM_BASES, 0);
982
-
} else {
983
-
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
984
-
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
985
-
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
986
-
!!adev->gmc.noretry);
987
-
WREG32_SOC15_RLC(GC, GET_INST(GC, j), regSH_MEM_CONFIG, tmp);
988
-
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
989
-
(adev->gmc.private_aperture_start >> 48));
990
-
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
991
-
(adev->gmc.shared_aperture_start >> 48));
992
-
WREG32_SOC15_RLC(GC, GET_INST(GC, j), regSH_MEM_BASES, tmp);
993
-
}
968
+
soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
969
+
/* CP and shaders */
970
+
if (i == 0) {
971
+
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
972
+
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
973
+
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
974
+
!!adev->gmc.noretry);
975
+
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
976
+
regSH_MEM_CONFIG, tmp);
977
+
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
978
+
regSH_MEM_BASES, 0);
979
+
} else {
980
+
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
981
+
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
982
+
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
983
+
!!adev->gmc.noretry);
984
+
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
985
+
regSH_MEM_CONFIG, tmp);
986
+
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
987
+
(adev->gmc.private_aperture_start >>
988
+
48));
989
+
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
990
+
(adev->gmc.shared_aperture_start >>
991
+
48));
992
+
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
993
+
regSH_MEM_BASES, tmp);
994
994
}
995
995
}
996
996
soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
997
997
998
998
mutex_unlock(&adev->srbm_mutex);
999
999
1000
-
for (i = 0; i < num_xcc; i++) {
1001
-
gfx_v9_4_3_xcc_init_compute_vmid(adev, i);
1002
-
gfx_v9_4_3_xcc_init_gds_vmid(adev, i);
1003
-
}
1000
+
gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id);
1001
+
gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id);
1002
+
}
1003
+
1004
+
static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
1005
+
{
1006
+
int i, num_xcc;
1007
+
1008
+
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1009
+
1010
+
gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
1011
+
adev->gfx.config.db_debug2 =
1012
+
RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);
1013
+
1014
+
for (i = 0; i < num_xcc; i++)
1015
+
gfx_v9_4_3_xcc_constants_init(adev, i);
1004
1016
}
1005
1017
1006
1018
static void
···
1179
1167
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);
1180
1168
}
1181
1169
1170
+
static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id)
1171
+
{
1172
+
WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1173
+
RLC_ENABLE_F32, 0);
1174
+
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1175
+
gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id);
1176
+
}
1177
+
1182
1178
static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev)
1183
1179
{
1184
1180
int i, num_xcc;
1185
1181
1186
1182
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1187
-
for (i = 0; i < num_xcc; i++) {
1188
-
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), RLC_CNTL, RLC_ENABLE_F32, 0);
1189
-
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, i);
1190
-
gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, i);
1191
-
}
1183
+
for (i = 0; i < num_xcc; i++)
1184
+
gfx_v9_4_3_xcc_rlc_stop(adev, i);
1185
+
}
1186
+
1187
+
static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id)
1188
+
{
1189
+
WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1190
+
SOFT_RESET_RLC, 1);
1191
+
udelay(50);
1192
+
WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1193
+
SOFT_RESET_RLC, 0);
1194
+
udelay(50);
1192
1195
}
1193
1196
1194
1197
static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev)
···
1211
1184
int i, num_xcc;
1212
1185
1213
1186
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1214
-
for (i = 0; i < num_xcc; i++) {
1215
-
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1216
-
udelay(50);
1217
-
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1187
+
for (i = 0; i < num_xcc; i++)
1188
+
gfx_v9_4_3_xcc_rlc_reset(adev, i);
1189
+
}
1190
+
1191
+
static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id)
1192
+
{
1193
+
WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1194
+
RLC_ENABLE_F32, 1);
1195
+
udelay(50);
1196
+
1197
+
/* carrizo do enable cp interrupt after cp inited */
1198
+
if (!(adev->flags & AMD_IS_APU)) {
1199
+
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1218
1200
udelay(50);
1219
1201
}
1220
1202
}
···
1237
1201
1238
1202
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1239
1203
for (i = 0; i < num_xcc; i++) {
1240
-
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), RLC_CNTL, RLC_ENABLE_F32, 1);
1241
-
udelay(50);
1242
-
1243
-
/* carrizo do enable cp interrupt after cp inited */
1244
-
if (!(adev->flags & AMD_IS_APU)) {
1245
-
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, i);
1246
-
udelay(50);
1247
-
}
1248
-
1204
+
gfx_v9_4_3_xcc_rlc_start(adev, i);
1249
1205
#ifdef AMDGPU_RLC_DEBUG_RETRY
1250
1206
/* RLC_GPM_GENERAL_6 : RLC Ucode version */
1251
1207
rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);
···
1288
1260
return 0;
1289
1261
}
1290
1262
1263
+
static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id)
1264
+
{
1265
+
int r;
1266
+
1267
+
gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
1268
+
1269
+
/* disable CG */
1270
+
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);
1271
+
1272
+
gfx_v9_4_3_xcc_init_pg(adev, xcc_id);
1273
+
1274
+
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1275
+
/* legacy rlc firmware loading */
1276
+
r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id);
1277
+
if (r)
1278
+
return r;
1279
+
}
1280
+
1281
+
gfx_v9_4_3_xcc_rlc_start(adev, xcc_id);
1282
+
1283
+
return 0;
1284
+
}
1285
+
1291
1286
static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
1292
1287
{
1293
1288
int r, i, num_xcc;
1294
1289
1295
-
adev->gfx.rlc.funcs->stop(adev);
1296
-
1297
1290
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1298
1291
for (i = 0; i < num_xcc; i++) {
1299
-
/* disable CG */
1300
-
WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CGCG_CGLS_CTRL, 0);
1301
-
1302
-
gfx_v9_4_3_xcc_init_pg(adev, i);
1303
-
1304
-
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1305
-
/* legacy rlc firmware loading */
1306
-
r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, i);
1307
-
if (r)
1308
-
return r;
1309
-
}
1292
+
r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
1293
+
if (r)
1294
+
return r;
1310
1295
}
1311
-
1312
-
adev->gfx.rlc.funcs->start(adev);
1313
1296
1314
1297
return 0;
1315
1298
}
···
1884
1845
return r;
1885
1846
}
1886
1847
1848
+
static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)
1849
+
{
1850
+
struct amdgpu_ring *ring;
1851
+
int r, j;
1852
+
1853
+
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1854
+
1855
+
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1856
+
gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id);
1857
+
1858
+
r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id);
1859
+
if (r)
1860
+
return r;
1861
+
}
1862
+
1863
+
if (adev->gfx.partition_mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)
1864
+
gfx_v9_4_3_switch_compute_partition(adev,
1865
+
amdgpu_user_partt_mode);
1866
+
1867
+
/* set the virtual and physical id based on partition_mode */
1868
+
gfx_v9_4_3_xcc_program_xcc_id(adev, xcc_id);
1869
+
1870
+
r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id);
1871
+
if (r)
1872
+
return r;
1873
+
1874
+
r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id);
1875
+
if (r)
1876
+
return r;
1877
+
1878
+
for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1879
+
ring = &adev->gfx.compute_ring
1880
+
[j + xcc_id * adev->gfx.num_compute_rings];
1881
+
r = amdgpu_ring_test_helper(ring);
1882
+
if (r)
1883
+
return r;
1884
+
}
1885
+
1886
+
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1887
+
1888
+
return 0;
1889
+
}
1890
+
1887
1891
static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
1888
1892
{
1889
-
int r, i, j, num_xcc;
1890
-
struct amdgpu_ring *ring;
1893
+
int r, i, num_xcc;
1891
1894
1892
1895
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1893
1896
for (i = 0; i < num_xcc; i++) {
1894
-
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, i);
1895
-
1896
-
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1897
-
gfx_v9_4_3_xcc_disable_gpa_mode(adev, i);
1898
-
1899
-
r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, i);
1900
-
if (r)
1901
-
return r;
1902
-
}
1903
-
1904
-
if (adev->gfx.partition_mode ==
1905
-
AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)
1906
-
gfx_v9_4_3_switch_compute_partition(
1907
-
adev, amdgpu_user_partt_mode);
1908
-
1909
-
/* set the virtual and physical id based on partition_mode */
1910
-
gfx_v9_4_3_xcc_program_xcc_id(adev, i);
1911
-
1912
-
r = gfx_v9_4_3_xcc_kiq_resume(adev, i);
1897
+
r = gfx_v9_4_3_xcc_cp_resume(adev, i);
1913
1898
if (r)
1914
1899
return r;
1915
-
1916
-
r = gfx_v9_4_3_xcc_kcq_resume(adev, i);
1917
-
if (r)
1918
-
return r;
1919
-
1920
-
for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1921
-
ring = &adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings];
1922
-
r = amdgpu_ring_test_helper(ring);
1923
-
if (r)
1924
-
return r;
1925
-
}
1926
-
1927
-
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, i);
1928
1900
}
1929
1901
1930
1902
return 0;
···
1945
1895
int xcc_id)
1946
1896
{
1947
1897
gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id);
1898
+
}
1899
+
1900
+
static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
1901
+
{
1902
+
if (amdgpu_gfx_disable_kcq(adev, xcc_id))
1903
+
DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id);
1904
+
1905
+
/* Use deinitialize sequence from CAIL when unbinding device
1906
+
* from driver, otherwise KIQ is hanging when binding back
1907
+
*/
1908
+
if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1909
+
mutex_lock(&adev->srbm_mutex);
1910
+
soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me,
1911
+
adev->gfx.kiq[xcc_id].ring.pipe,
1912
+
adev->gfx.kiq[xcc_id].ring.queue, 0,
1913
+
GET_INST(GC, xcc_id));
1914
+
gfx_v9_4_3_xcc_kiq_fini_register(&adev->gfx.kiq[xcc_id].ring,
1915
+
xcc_id);
1916
+
soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1917
+
mutex_unlock(&adev->srbm_mutex);
1918
+
}
1919
+
1920
+
gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
1921
+
1922
+
/* Skip suspend with A+A reset */
1923
+
if (adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) {
1924
+
dev_dbg(adev->dev, "Device in reset. Skipping RLC halt\n");
1925
+
return;
1926
+
}
1927
+
1928
+
gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
1948
1929
}
1949
1930
1950
1931
static int gfx_v9_4_3_hw_init(void *handle)
···
2008
1927
2009
1928
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2010
1929
for (i = 0; i < num_xcc; i++) {
2011
-
if (amdgpu_gfx_disable_kcq(adev, i))
2012
-
DRM_ERROR("XCD %d KCQ disable failed\n", i);
2013
-
2014
-
/* Use deinitialize sequence from CAIL when unbinding device
2015
-
* from driver, otherwise KIQ is hanging when binding back
2016
-
*/
2017
-
if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
2018
-
mutex_lock(&adev->srbm_mutex);
2019
-
soc15_grbm_select(adev, adev->gfx.kiq[i].ring.me,
2020
-
adev->gfx.kiq[i].ring.pipe,
2021
-
adev->gfx.kiq[i].ring.queue, 0, GET_INST(GC, i));
2022
-
gfx_v9_4_3_xcc_kiq_fini_register(&adev->gfx.kiq[i].ring,
2023
-
i);
2024
-
soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, i));
2025
-
mutex_unlock(&adev->srbm_mutex);
2026
-
}
2027
-
2028
-
gfx_v9_4_3_xcc_cp_enable(adev, false, i);
1930
+
gfx_v9_4_3_xcc_fini(adev, i);
2029
1931
}
2030
1932
2031
-
/* Skip suspend with A+A reset */
2032
-
if (adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) {
2033
-
dev_dbg(adev->dev, "Device in reset. Skipping RLC halt\n");
2034
-
return 0;
2035
-
}
2036
-
2037
-
adev->gfx.rlc.funcs->stop(adev);
2038
1933
return 0;
2039
1934
}
2040
1935