Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.10-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
- more intc updates [Yuriv]
- fix module build when unwinder is turned off
- IO Coherency Programming model updates
- other miscellaneous
* tag 'arc-4.10-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: Revert "ARC: mm: IOC: Don't enable IOC by default"
ARC: mm: split arc_cache_init to allow __init reaping of bulk
ARCv2: IOC: Use actual memory size to setup aperture size
ARCv2: IOC: Adhere to progamming model guidelines to avoid DMA corruption
ARCv2: IOC: refactor the IOC and SLC operations into own functions
ARC: module: Fix !CONFIG_ARC_DW2_UNWIND builds
ARCv2: save r30 on kernel entry as gcc uses it for code-gen
ARCv2: IRQ: Call entry/exit functions for chained handlers in MCIP
ARC: IRQ: Use hwirq instead of virq in mask/unmask
ARC: mmu: clarify the MMUv3 programming model
+151
-47
+1
-1
arch/arc/Kconfig
+1
-1
arch/arc/Kconfig
+5
-4
arch/arc/include/asm/cache.h
+5
-4
arch/arc/include/asm/cache.h
···
67
67
#define ARC_REG_IC_PTAG_HI 0x1F
68
68
69
69
/* Bit val in IC_CTRL */
70
-
#define IC_CTRL_CACHE_DISABLE 0x1
70
+
#define IC_CTRL_DIS 0x1
71
71
72
72
/* Data cache related Auxiliary registers */
73
73
#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
···
80
80
#define ARC_REG_DC_PTAG_HI 0x5F
81
81
82
82
/* Bit val in DC_CTRL */
83
-
#define DC_CTRL_INV_MODE_FLUSH 0x40
84
-
#define DC_CTRL_FLUSH_STATUS 0x100
83
+
#define DC_CTRL_DIS 0x001
84
+
#define DC_CTRL_INV_MODE_FLUSH 0x040
85
+
#define DC_CTRL_FLUSH_STATUS 0x100
85
86
86
87
/*System-level cache (L2 cache) related Auxiliary registers */
87
88
#define ARC_REG_SLC_CFG 0x901
···
93
92
#define ARC_REG_SLC_RGN_END 0x916
94
93
95
94
/* Bit val in SLC_CONTROL */
95
+
#define SLC_CTRL_DIS 0x001
96
96
#define SLC_CTRL_IM 0x040
97
-
#define SLC_CTRL_DISABLE 0x001
98
97
#define SLC_CTRL_BUSY 0x100
99
98
#define SLC_CTRL_RGN_OP_INV 0x200
100
99
+2
arch/arc/include/asm/entry-arcv2.h
+2
arch/arc/include/asm/entry-arcv2.h
+2
-2
arch/arc/include/asm/module.h
+2
-2
arch/arc/include/asm/module.h
···
14
14
15
15
#include <asm-generic/module.h>
16
16
17
-
#ifdef CONFIG_ARC_DW2_UNWIND
18
17
struct mod_arch_specific {
18
+
#ifdef CONFIG_ARC_DW2_UNWIND
19
19
void *unw_info;
20
20
int unw_sec_idx;
21
+
#endif
21
22
const char *secstr;
22
23
};
23
-
#endif
24
24
25
25
#define MODULE_PROC_FAMILY "ARC700"
26
26
+1
-1
arch/arc/include/asm/ptrace.h
+1
-1
arch/arc/include/asm/ptrace.h
+1
arch/arc/include/asm/setup.h
+1
arch/arc/include/asm/setup.h
+3
-3
arch/arc/kernel/intc-arcv2.c
+3
-3
arch/arc/kernel/intc-arcv2.c
···
77
77
78
78
static void arcv2_irq_mask(struct irq_data *data)
79
79
{
80
-
write_aux_reg(AUX_IRQ_SELECT, data->irq);
80
+
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
81
81
write_aux_reg(AUX_IRQ_ENABLE, 0);
82
82
}
83
83
84
84
static void arcv2_irq_unmask(struct irq_data *data)
85
85
{
86
-
write_aux_reg(AUX_IRQ_SELECT, data->irq);
86
+
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
87
87
write_aux_reg(AUX_IRQ_ENABLE, 1);
88
88
}
89
89
90
90
void arcv2_irq_enable(struct irq_data *data)
91
91
{
92
92
/* set default priority */
93
-
write_aux_reg(AUX_IRQ_SELECT, data->irq);
93
+
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
94
94
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
95
95
96
96
/*
+2
-2
arch/arc/kernel/intc-compact.c
+2
-2
arch/arc/kernel/intc-compact.c
···
57
57
unsigned int ienb;
58
58
59
59
ienb = read_aux_reg(AUX_IENABLE);
60
-
ienb &= ~(1 << data->irq);
60
+
ienb &= ~(1 << data->hwirq);
61
61
write_aux_reg(AUX_IENABLE, ienb);
62
62
}
63
63
···
66
66
unsigned int ienb;
67
67
68
68
ienb = read_aux_reg(AUX_IENABLE);
69
-
ienb |= (1 << data->irq);
69
+
ienb |= (1 << data->hwirq);
70
70
write_aux_reg(AUX_IENABLE, ienb);
71
71
}
72
72
+4
arch/arc/kernel/mcip.c
+4
arch/arc/kernel/mcip.c
···
10
10
11
11
#include <linux/smp.h>
12
12
#include <linux/irq.h>
13
+
#include <linux/irqchip/chained_irq.h>
13
14
#include <linux/spinlock.h>
14
15
#include <soc/arc/mcip.h>
15
16
#include <asm/irqflags-arcv2.h>
···
222
221
static void idu_cascade_isr(struct irq_desc *desc)
223
222
{
224
223
struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
224
+
struct irq_chip *core_chip = irq_desc_get_chip(desc);
225
225
irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
226
226
irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
227
227
228
+
chained_irq_enter(core_chip, desc);
228
229
generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
230
+
chained_irq_exit(core_chip, desc);
229
231
}
230
232
231
233
static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
+3
-1
arch/arc/kernel/module.c
+3
-1
arch/arc/kernel/module.c
···
32
32
#ifdef CONFIG_ARC_DW2_UNWIND
33
33
mod->arch.unw_sec_idx = 0;
34
34
mod->arch.unw_info = NULL;
35
-
mod->arch.secstr = secstr;
36
35
#endif
36
+
mod->arch.secstr = secstr;
37
37
return 0;
38
38
}
39
39
···
113
113
114
114
}
115
115
116
+
#ifdef CONFIG_ARC_DW2_UNWIND
116
117
if (strcmp(module->arch.secstr+sechdrs[tgtsec].sh_name, ".eh_frame") == 0)
117
118
module->arch.unw_sec_idx = tgtsec;
119
+
#endif
118
120
119
121
return 0;
120
122
+122
-33
arch/arc/mm/cache.c
+122
-33
arch/arc/mm/cache.c
···
23
23
24
24
static int l2_line_sz;
25
25
static int ioc_exists;
26
-
int slc_enable = 1, ioc_enable = 0;
26
+
int slc_enable = 1, ioc_enable = 1;
27
27
unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
28
28
unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
29
29
···
271
271
272
272
/*
273
273
* For ARC700 MMUv3 I-cache and D-cache flushes
274
-
* Also reused for HS38 aliasing I-cache configuration
274
+
* - ARC700 programming model requires paddr and vaddr be passed in seperate
275
+
* AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the
276
+
* caches actually alias or not.
277
+
* - For HS38, only the aliasing I-cache configuration uses the PTAG reg
278
+
* (non aliasing I-cache version doesn't; while D-cache can't possibly alias)
275
279
*/
276
280
static inline
277
281
void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
···
462
458
__after_dc_op(op);
463
459
}
464
460
461
+
static inline void __dc_disable(void)
462
+
{
463
+
const int r = ARC_REG_DC_CTRL;
464
+
465
+
__dc_entire_op(OP_FLUSH_N_INV);
466
+
write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);
467
+
}
468
+
469
+
static void __dc_enable(void)
470
+
{
471
+
const int r = ARC_REG_DC_CTRL;
472
+
473
+
write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
474
+
}
475
+
465
476
/* For kernel mappings cache operation: index is same as paddr */
466
477
#define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
467
478
···
502
483
#else
503
484
504
485
#define __dc_entire_op(op)
486
+
#define __dc_disable()
487
+
#define __dc_enable()
505
488
#define __dc_line_op(paddr, vaddr, sz, op)
506
489
#define __dc_line_op_k(paddr, sz, op)
507
490
···
616
595
617
596
spin_unlock_irqrestore(&lock, flags);
618
597
#endif
598
+
}
599
+
600
+
noinline static void slc_entire_op(const int op)
601
+
{
602
+
unsigned int ctrl, r = ARC_REG_SLC_CTRL;
603
+
604
+
ctrl = read_aux_reg(r);
605
+
606
+
if (!(op & OP_FLUSH)) /* i.e. OP_INV */
607
+
ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
608
+
else
609
+
ctrl |= SLC_CTRL_IM;
610
+
611
+
write_aux_reg(r, ctrl);
612
+
613
+
write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
614
+
615
+
/* Important to wait for flush to complete */
616
+
while (read_aux_reg(r) & SLC_CTRL_BUSY);
617
+
}
618
+
619
+
static inline void arc_slc_disable(void)
620
+
{
621
+
const int r = ARC_REG_SLC_CTRL;
622
+
623
+
slc_entire_op(OP_FLUSH_N_INV);
624
+
write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);
625
+
}
626
+
627
+
static inline void arc_slc_enable(void)
628
+
{
629
+
const int r = ARC_REG_SLC_CTRL;
630
+
631
+
write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
619
632
}
620
633
621
634
/***********************************************************
···
978
923
return 0;
979
924
}
980
925
981
-
void arc_cache_init(void)
926
+
/*
927
+
* IO-Coherency (IOC) setup rules:
928
+
*
929
+
* 1. Needs to be at system level, so only once by Master core
930
+
* Non-Masters need not be accessing caches at that time
931
+
* - They are either HALT_ON_RESET and kick started much later or
932
+
* - if run on reset, need to ensure that arc_platform_smp_wait_to_boot()
933
+
* doesn't perturb caches or coherency unit
934
+
*
935
+
* 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
936
+
* otherwise any straggler data might behave strangely post IOC enabling
937
+
*
938
+
* 3. All Caches need to be disabled when setting up IOC to elide any in-flight
939
+
* Coherency transactions
940
+
*/
941
+
noinline void __init arc_ioc_setup(void)
982
942
{
983
-
unsigned int __maybe_unused cpu = smp_processor_id();
984
-
char str[256];
943
+
unsigned int ap_sz;
985
944
986
-
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
945
+
/* Flush + invalidate + disable L1 dcache */
946
+
__dc_disable();
947
+
948
+
/* Flush + invalidate SLC */
949
+
if (read_aux_reg(ARC_REG_SLC_BCR))
950
+
slc_entire_op(OP_FLUSH_N_INV);
951
+
952
+
/* IOC Aperture start: TDB: handle non default CONFIG_LINUX_LINK_BASE */
953
+
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
987
954
988
955
/*
989
-
* Only master CPU needs to execute rest of function:
990
-
* - Assume SMP so all cores will have same cache config so
991
-
* any geomtry checks will be same for all
992
-
* - IOC setup / dma callbacks only need to be setup once
956
+
* IOC Aperture size:
957
+
* decoded as 2 ^ (SIZE + 2) KB: so setting 0x11 implies 512M
958
+
* TBD: fix for PGU + 1GB of low mem
959
+
* TBD: fix for PAE
993
960
*/
994
-
if (cpu)
995
-
return;
961
+
ap_sz = order_base_2(arc_get_mem_sz()/1024) - 2;
962
+
write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, ap_sz);
963
+
964
+
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
965
+
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
966
+
967
+
/* Re-enable L1 dcache */
968
+
__dc_enable();
969
+
}
970
+
971
+
void __init arc_cache_init_master(void)
972
+
{
973
+
unsigned int __maybe_unused cpu = smp_processor_id();
996
974
997
975
if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
998
976
struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
···
1073
985
}
1074
986
}
1075
987
1076
-
if (is_isa_arcv2() && l2_line_sz && !slc_enable) {
988
+
/* Note that SLC disable not formally supported till HS 3.0 */
989
+
if (is_isa_arcv2() && l2_line_sz && !slc_enable)
990
+
arc_slc_disable();
1077
991
1078
-
/* IM set : flush before invalidate */
1079
-
write_aux_reg(ARC_REG_SLC_CTRL,
1080
-
read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_IM);
1081
-
1082
-
write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
1083
-
1084
-
/* Important to wait for flush to complete */
1085
-
while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
1086
-
write_aux_reg(ARC_REG_SLC_CTRL,
1087
-
read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE);
1088
-
}
992
+
if (is_isa_arcv2() && ioc_enable)
993
+
arc_ioc_setup();
1089
994
1090
995
if (is_isa_arcv2() && ioc_enable) {
1091
-
/* IO coherency base - 0x8z */
1092
-
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
1093
-
/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
1094
-
write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11);
1095
-
/* Enable partial writes */
1096
-
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
1097
-
/* Enable IO coherency */
1098
-
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
1099
-
1100
996
__dma_cache_wback_inv = __dma_cache_wback_inv_ioc;
1101
997
__dma_cache_inv = __dma_cache_inv_ioc;
1102
998
__dma_cache_wback = __dma_cache_wback_ioc;
···
1093
1021
__dma_cache_inv = __dma_cache_inv_l1;
1094
1022
__dma_cache_wback = __dma_cache_wback_l1;
1095
1023
}
1024
+
}
1025
+
1026
+
void __ref arc_cache_init(void)
1027
+
{
1028
+
unsigned int __maybe_unused cpu = smp_processor_id();
1029
+
char str[256];
1030
+
1031
+
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
1032
+
1033
+
/*
1034
+
* Only master CPU needs to execute rest of function:
1035
+
* - Assume SMP so all cores will have same cache config so
1036
+
* any geomtry checks will be same for all
1037
+
* - IOC setup / dma callbacks only need to be setup once
1038
+
*/
1039
+
if (!cpu)
1040
+
arc_cache_init_master();
1096
1041
}