Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: Use the central UBWC config database
As discussed a lot in the past, the UBWC config must be coherent across
a number of IP blocks (currently display and GPU, but it also may/will
concern camera/video as the drivers evolve).
So far, we've been trying to keep the values reasonable in each of the
two drivers separately, but it really make sense to do so centrally,
especially given certain fields (e.g. HBB) may need to be gathered
dynamically.
To reduce room for error, move to fetching the config from a central
source, so that the data programmed into the hardware is consistent
across all multimedia blocks that request it.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660963/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Konrad Dybcio
and committed by
Rob Clark
45a29741
227d4ce0
+74
-322
+1
drivers/gpu/drm/msm/Kconfig
+1
drivers/gpu/drm/msm/Kconfig
+3
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+3
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
···
10
10
#include "dpu_hw_sspp.h"
11
11
#include "dpu_kms.h"
12
12
13
-
#include "msm_mdss.h"
14
-
15
13
#include <drm/drm_file.h>
16
14
#include <drm/drm_managed.h>
15
+
16
+
#include <linux/soc/qcom/ubwc.h>
17
17
18
18
#define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087
19
19
···
684
684
struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
685
685
const struct dpu_sspp_cfg *cfg,
686
686
void __iomem *addr,
687
-
const struct msm_mdss_data *mdss_data,
687
+
const struct qcom_ubwc_cfg_data *mdss_data,
688
688
const struct dpu_mdss_version *mdss_rev)
689
689
{
690
690
struct dpu_hw_sspp *hw_pipe;
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
···
308
308
struct dpu_hw_sspp {
309
309
struct dpu_hw_blk base;
310
310
struct dpu_hw_blk_reg_map hw;
311
-
const struct msm_mdss_data *ubwc;
311
+
const struct qcom_ubwc_cfg_data *ubwc;
312
312
313
313
/* Pipe */
314
314
enum dpu_sspp idx;
···
325
325
struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
326
326
const struct dpu_sspp_cfg *cfg,
327
327
void __iomem *addr,
328
-
const struct msm_mdss_data *mdss_data,
328
+
const struct qcom_ubwc_cfg_data *mdss_data,
329
329
const struct dpu_mdss_version *mdss_rev);
330
330
331
331
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
+4
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+4
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
···
20
20
#include <drm/drm_vblank.h>
21
21
#include <drm/drm_writeback.h>
22
22
23
+
#include <linux/soc/qcom/ubwc.h>
24
+
23
25
#include "msm_drv.h"
24
26
#include "msm_mmu.h"
25
-
#include "msm_mdss.h"
26
27
#include "msm_gem.h"
27
28
#include "disp/msm_disp_snapshot.h"
28
29
···
1190
1189
goto err_pm_put;
1191
1190
}
1192
1191
1193
-
dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent);
1192
+
dpu_kms->mdss = qcom_ubwc_config_get_data();
1194
1193
if (IS_ERR(dpu_kms->mdss)) {
1195
1194
rc = PTR_ERR(dpu_kms->mdss);
1196
-
DPU_ERROR("failed to get MDSS data: %d\n", rc);
1195
+
DPU_ERROR("failed to get UBWC config data: %d\n", rc);
1197
1196
goto err_pm_put;
1198
1197
}
1199
1198
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+2
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+2
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+58
-280
drivers/gpu/drm/msm/msm_mdss.c
+58
-280
drivers/gpu/drm/msm/msm_mdss.c
···
16
16
#include <linux/pm_runtime.h>
17
17
#include <linux/reset.h>
18
18
19
-
#include "msm_mdss.h"
19
+
#include <linux/soc/qcom/ubwc.h>
20
+
20
21
#include "msm_kms.h"
21
22
22
23
#include <generated/mdss.xml.h>
23
24
24
25
#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
25
26
26
-
#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
27
+
struct msm_mdss_data {
28
+
u32 reg_bus_bw;
29
+
};
27
30
28
31
struct msm_mdss {
29
32
struct device *dev;
···
39
36
unsigned long enabled_mask;
40
37
struct irq_domain *domain;
41
38
} irq_controller;
42
-
const struct msm_mdss_data *mdss_data;
39
+
const struct qcom_ubwc_cfg_data *mdss_data;
40
+
u32 reg_bus_bw;
43
41
struct icc_path *mdp_path[2];
44
42
u32 num_mdp_paths;
45
43
struct icc_path *reg_bus_path;
···
169
165
170
166
static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
171
167
{
172
-
const struct msm_mdss_data *data = msm_mdss->mdss_data;
168
+
const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
173
169
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
174
170
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
175
171
···
184
180
185
181
static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
186
182
{
187
-
const struct msm_mdss_data *data = msm_mdss->mdss_data;
183
+
const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
188
184
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |
189
185
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
190
186
···
202
198
203
199
static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
204
200
{
205
-
const struct msm_mdss_data *data = msm_mdss->mdss_data;
201
+
const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
206
202
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
207
203
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
208
204
···
228
224
229
225
static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss)
230
226
{
231
-
const struct msm_mdss_data *data = msm_mdss->mdss_data;
227
+
const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
232
228
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
233
229
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
234
230
···
244
240
writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
245
241
}
246
242
247
-
#define MDSS_HW_MAJ_MIN \
248
-
(MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK)
249
-
250
-
#define MDSS_HW_MSM8996 0x1007
251
-
#define MDSS_HW_MSM8937 0x100e
252
-
#define MDSS_HW_MSM8953 0x1010
253
-
#define MDSS_HW_MSM8998 0x3000
254
-
#define MDSS_HW_SDM660 0x3002
255
-
#define MDSS_HW_SDM630 0x3003
256
-
257
-
/*
258
-
* MDP5 platforms use generic qcom,mdp5 compat string, so we have to generate this data
259
-
*/
260
-
static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss)
261
-
{
262
-
struct msm_mdss_data *data;
263
-
u32 hw_rev;
264
-
265
-
data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL);
266
-
if (!data)
267
-
return NULL;
268
-
269
-
hw_rev = readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION);
270
-
hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev);
271
-
272
-
if (hw_rev == MDSS_HW_MSM8996 ||
273
-
hw_rev == MDSS_HW_MSM8937 ||
274
-
hw_rev == MDSS_HW_MSM8953 ||
275
-
hw_rev == MDSS_HW_MSM8998 ||
276
-
hw_rev == MDSS_HW_SDM660 ||
277
-
hw_rev == MDSS_HW_SDM630) {
278
-
data->ubwc_dec_version = UBWC_1_0;
279
-
data->ubwc_enc_version = UBWC_1_0;
280
-
}
281
-
282
-
if (hw_rev == MDSS_HW_MSM8996 ||
283
-
hw_rev == MDSS_HW_MSM8998)
284
-
data->highest_bank_bit = 15;
285
-
else
286
-
data->highest_bank_bit = 14;
287
-
288
-
return data;
289
-
}
290
-
291
-
const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev)
292
-
{
293
-
struct msm_mdss *mdss;
294
-
295
-
if (!dev)
296
-
return ERR_PTR(-EINVAL);
297
-
298
-
mdss = dev_get_drvdata(dev);
299
-
300
-
/*
301
-
* We could not do it at the probe time, since hw revision register was
302
-
* not readable. Fill data structure now for the MDP5 platforms.
303
-
*/
304
-
if (!mdss->mdss_data && mdss->is_mdp5)
305
-
mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss);
306
-
307
-
return mdss->mdss_data;
308
-
}
309
-
310
243
static int msm_mdss_enable(struct msm_mdss *msm_mdss)
311
244
{
312
245
int ret, i;
···
256
315
for (i = 0; i < msm_mdss->num_mdp_paths; i++)
257
316
icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
258
317
259
-
if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)
260
-
icc_set_bw(msm_mdss->reg_bus_path, 0,
261
-
msm_mdss->mdss_data->reg_bus_bw);
262
-
else
263
-
icc_set_bw(msm_mdss->reg_bus_path, 0,
264
-
DEFAULT_REG_BW);
318
+
icc_set_bw(msm_mdss->reg_bus_path, 0,
319
+
msm_mdss->reg_bus_bw);
265
320
266
321
ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
267
322
if (ret) {
···
396
459
397
460
static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
398
461
{
462
+
const struct msm_mdss_data *mdss_data;
399
463
struct msm_mdss *msm_mdss;
400
464
int ret;
401
465
int irq;
···
409
471
if (!msm_mdss)
410
472
return ERR_PTR(-ENOMEM);
411
473
412
-
msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev);
474
+
msm_mdss->mdss_data = qcom_ubwc_config_get_data();
475
+
if (IS_ERR(msm_mdss->mdss_data))
476
+
return ERR_CAST(msm_mdss->mdss_data);
477
+
478
+
mdss_data = of_device_get_match_data(&pdev->dev);
479
+
if (!mdss_data)
480
+
return ERR_PTR(-EINVAL);
481
+
482
+
msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw;
413
483
414
484
msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
415
485
if (IS_ERR(msm_mdss->mmio))
···
536
590
msm_mdss_destroy(mdss);
537
591
}
538
592
539
-
static const struct msm_mdss_data msm8998_data = {
540
-
.ubwc_enc_version = UBWC_1_0,
541
-
.ubwc_dec_version = UBWC_1_0,
542
-
.highest_bank_bit = 15,
543
-
.reg_bus_bw = 76800,
544
-
};
545
-
546
-
static const struct msm_mdss_data qcm2290_data = {
547
-
/* no UBWC */
548
-
.highest_bank_bit = 15,
549
-
.reg_bus_bw = 76800,
550
-
};
551
-
552
-
static const struct msm_mdss_data sa8775p_data = {
553
-
.ubwc_enc_version = UBWC_4_0,
554
-
.ubwc_dec_version = UBWC_4_0,
555
-
.ubwc_swizzle = 4,
556
-
.ubwc_bank_spread = true,
557
-
.highest_bank_bit = 13,
558
-
.macrotile_mode = true,
559
-
.reg_bus_bw = 74000,
560
-
};
561
-
562
-
static const struct msm_mdss_data sar2130p_data = {
563
-
.ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
564
-
.ubwc_dec_version = UBWC_4_3,
565
-
.ubwc_swizzle = 6,
566
-
.ubwc_bank_spread = true,
567
-
.highest_bank_bit = 13,
568
-
.macrotile_mode = 1,
569
-
.reg_bus_bw = 74000,
570
-
};
571
-
572
-
static const struct msm_mdss_data sc7180_data = {
573
-
.ubwc_enc_version = UBWC_2_0,
574
-
.ubwc_dec_version = UBWC_2_0,
575
-
.ubwc_swizzle = 6,
576
-
.ubwc_bank_spread = true,
577
-
.highest_bank_bit = 14,
578
-
.reg_bus_bw = 76800,
579
-
};
580
-
581
-
static const struct msm_mdss_data sc7280_data = {
582
-
.ubwc_enc_version = UBWC_3_0,
583
-
.ubwc_dec_version = UBWC_4_0,
584
-
.ubwc_swizzle = 6,
585
-
.ubwc_bank_spread = true,
586
-
.highest_bank_bit = 14,
587
-
.macrotile_mode = true,
588
-
.reg_bus_bw = 74000,
589
-
};
590
-
591
-
static const struct msm_mdss_data sc8180x_data = {
592
-
.ubwc_enc_version = UBWC_3_0,
593
-
.ubwc_dec_version = UBWC_3_0,
594
-
.highest_bank_bit = 16,
595
-
.macrotile_mode = true,
596
-
.reg_bus_bw = 76800,
597
-
};
598
-
599
-
static const struct msm_mdss_data sc8280xp_data = {
600
-
.ubwc_enc_version = UBWC_4_0,
601
-
.ubwc_dec_version = UBWC_4_0,
602
-
.ubwc_swizzle = 6,
603
-
.ubwc_bank_spread = true,
604
-
.highest_bank_bit = 16,
605
-
.macrotile_mode = true,
606
-
.reg_bus_bw = 76800,
607
-
};
608
-
609
-
static const struct msm_mdss_data sdm670_data = {
610
-
.ubwc_enc_version = UBWC_2_0,
611
-
.ubwc_dec_version = UBWC_2_0,
612
-
.highest_bank_bit = 14,
613
-
.reg_bus_bw = 76800,
614
-
};
615
-
616
-
static const struct msm_mdss_data sdm845_data = {
617
-
.ubwc_enc_version = UBWC_2_0,
618
-
.ubwc_dec_version = UBWC_2_0,
619
-
.highest_bank_bit = 15,
620
-
.reg_bus_bw = 76800,
621
-
};
622
-
623
-
static const struct msm_mdss_data sm6350_data = {
624
-
.ubwc_enc_version = UBWC_2_0,
625
-
.ubwc_dec_version = UBWC_2_0,
626
-
.ubwc_swizzle = 6,
627
-
.ubwc_bank_spread = true,
628
-
.highest_bank_bit = 14,
629
-
.reg_bus_bw = 76800,
630
-
};
631
-
632
-
static const struct msm_mdss_data sm7150_data = {
633
-
.ubwc_enc_version = UBWC_2_0,
634
-
.ubwc_dec_version = UBWC_2_0,
635
-
.highest_bank_bit = 14,
636
-
.reg_bus_bw = 76800,
637
-
};
638
-
639
-
static const struct msm_mdss_data sm8150_data = {
640
-
.ubwc_enc_version = UBWC_3_0,
641
-
.ubwc_dec_version = UBWC_3_0,
642
-
.highest_bank_bit = 15,
643
-
.reg_bus_bw = 76800,
644
-
};
645
-
646
-
static const struct msm_mdss_data sm6115_data = {
647
-
.ubwc_enc_version = UBWC_1_0,
648
-
.ubwc_dec_version = UBWC_2_0,
649
-
.ubwc_swizzle = 7,
650
-
.ubwc_bank_spread = true,
651
-
.highest_bank_bit = 14,
652
-
.reg_bus_bw = 76800,
653
-
};
654
-
655
-
static const struct msm_mdss_data sm6125_data = {
656
-
.ubwc_enc_version = UBWC_1_0,
657
-
.ubwc_dec_version = UBWC_3_0,
658
-
.ubwc_swizzle = 1,
659
-
.highest_bank_bit = 14,
660
-
};
661
-
662
-
static const struct msm_mdss_data sm6150_data = {
663
-
.ubwc_enc_version = UBWC_2_0,
664
-
.ubwc_dec_version = UBWC_2_0,
665
-
.highest_bank_bit = 14,
666
-
.reg_bus_bw = 76800,
667
-
};
668
-
669
-
static const struct msm_mdss_data sm8250_data = {
670
-
.ubwc_enc_version = UBWC_4_0,
671
-
.ubwc_dec_version = UBWC_4_0,
672
-
.ubwc_swizzle = 6,
673
-
.ubwc_bank_spread = true,
674
-
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
675
-
.highest_bank_bit = 16,
676
-
.macrotile_mode = true,
677
-
.reg_bus_bw = 76800,
678
-
};
679
-
680
-
static const struct msm_mdss_data sm8350_data = {
681
-
.ubwc_enc_version = UBWC_4_0,
682
-
.ubwc_dec_version = UBWC_4_0,
683
-
.ubwc_swizzle = 6,
684
-
.ubwc_bank_spread = true,
685
-
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
686
-
.highest_bank_bit = 16,
687
-
.macrotile_mode = true,
688
-
.reg_bus_bw = 74000,
689
-
};
690
-
691
-
static const struct msm_mdss_data sm8550_data = {
692
-
.ubwc_enc_version = UBWC_4_0,
693
-
.ubwc_dec_version = UBWC_4_3,
694
-
.ubwc_swizzle = 6,
695
-
.ubwc_bank_spread = true,
696
-
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
697
-
.highest_bank_bit = 16,
698
-
.macrotile_mode = true,
593
+
static const struct msm_mdss_data data_57k = {
699
594
.reg_bus_bw = 57000,
700
595
};
701
596
702
-
static const struct msm_mdss_data sm8750_data = {
703
-
.ubwc_enc_version = UBWC_5_0,
704
-
.ubwc_dec_version = UBWC_5_0,
705
-
.ubwc_swizzle = 6,
706
-
.ubwc_bank_spread = true,
707
-
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
708
-
.highest_bank_bit = 16,
709
-
.macrotile_mode = true,
710
-
.reg_bus_bw = 57000,
597
+
static const struct msm_mdss_data data_74k = {
598
+
.reg_bus_bw = 74000,
711
599
};
712
600
713
-
static const struct msm_mdss_data x1e80100_data = {
714
-
.ubwc_enc_version = UBWC_4_0,
715
-
.ubwc_dec_version = UBWC_4_3,
716
-
.ubwc_swizzle = 6,
717
-
.ubwc_bank_spread = true,
718
-
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
719
-
.highest_bank_bit = 16,
720
-
.macrotile_mode = true,
721
-
/* TODO: Add reg_bus_bw with real value */
601
+
static const struct msm_mdss_data data_76k8 = {
602
+
.reg_bus_bw = 76800,
603
+
};
604
+
605
+
static const struct msm_mdss_data data_153k6 = {
606
+
.reg_bus_bw = 153600,
722
607
};
723
608
724
609
static const struct of_device_id mdss_dt_match[] = {
725
-
{ .compatible = "qcom,mdss" },
726
-
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
727
-
{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
728
-
{ .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
729
-
{ .compatible = "qcom,sar2130p-mdss", .data = &sar2130p_data },
730
-
{ .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
731
-
{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
732
-
{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
733
-
{ .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
734
-
{ .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
735
-
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
736
-
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
737
-
{ .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
738
-
{ .compatible = "qcom,sm6150-mdss", .data = &sm6150_data },
739
-
{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
740
-
{ .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
741
-
{ .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },
742
-
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
743
-
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
744
-
{ .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
745
-
{ .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
746
-
{ .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
747
-
{ .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
748
-
{ .compatible = "qcom,sm8750-mdss", .data = &sm8750_data},
749
-
{ .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
610
+
{ .compatible = "qcom,mdss", .data = &data_153k6 },
611
+
{ .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
612
+
{ .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
613
+
{ .compatible = "qcom,sa8775p-mdss", .data = &data_74k },
614
+
{ .compatible = "qcom,sar2130p-mdss", .data = &data_74k },
615
+
{ .compatible = "qcom,sdm670-mdss", .data = &data_76k8 },
616
+
{ .compatible = "qcom,sdm845-mdss", .data = &data_76k8 },
617
+
{ .compatible = "qcom,sc7180-mdss", .data = &data_76k8 },
618
+
{ .compatible = "qcom,sc7280-mdss", .data = &data_74k },
619
+
{ .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 },
620
+
{ .compatible = "qcom,sc8280xp-mdss", .data = &data_76k8 },
621
+
{ .compatible = "qcom,sm6115-mdss", .data = &data_76k8 },
622
+
{ .compatible = "qcom,sm6125-mdss", .data = &data_76k8 },
623
+
{ .compatible = "qcom,sm6150-mdss", .data = &data_76k8 },
624
+
{ .compatible = "qcom,sm6350-mdss", .data = &data_76k8 },
625
+
{ .compatible = "qcom,sm6375-mdss", .data = &data_76k8 },
626
+
{ .compatible = "qcom,sm7150-mdss", .data = &data_76k8 },
627
+
{ .compatible = "qcom,sm8150-mdss", .data = &data_76k8 },
628
+
{ .compatible = "qcom,sm8250-mdss", .data = &data_76k8 },
629
+
{ .compatible = "qcom,sm8350-mdss", .data = &data_74k },
630
+
{ .compatible = "qcom,sm8450-mdss", .data = &data_74k },
631
+
{ .compatible = "qcom,sm8550-mdss", .data = &data_57k },
632
+
{ .compatible = "qcom,sm8650-mdss", .data = &data_57k },
633
+
{ .compatible = "qcom,sm8750-mdss", .data = &data_57k },
634
+
/* TODO: x1e8: Add reg_bus_bw with real value */
635
+
{ .compatible = "qcom,x1e80100-mdss", .data = &data_153k6 },
750
636
{}
751
637
};
752
638
MODULE_DEVICE_TABLE(of, mdss_dt_match);
-29
drivers/gpu/drm/msm/msm_mdss.h
-29
drivers/gpu/drm/msm/msm_mdss.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* Copyright (c) 2018, The Linux Foundation
4
-
*/
5
-
6
-
#ifndef __MSM_MDSS_H__
7
-
#define __MSM_MDSS_H__
8
-
9
-
struct msm_mdss_data {
10
-
u32 ubwc_enc_version;
11
-
/* can be read from register 0x58 */
12
-
u32 ubwc_dec_version;
13
-
u32 ubwc_swizzle;
14
-
u32 highest_bank_bit;
15
-
bool ubwc_bank_spread;
16
-
bool macrotile_mode;
17
-
u32 reg_bus_bw;
18
-
};
19
-
20
-
#define UBWC_1_0 0x10000000
21
-
#define UBWC_2_0 0x20000000
22
-
#define UBWC_3_0 0x30000000
23
-
#define UBWC_4_0 0x40000000
24
-
#define UBWC_4_3 0x40030000
25
-
#define UBWC_5_0 0x50000000
26
-
27
-
const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev);
28
-
29
-
#endif /* __MSM_MDSS_H__ */
+1
-1
include/linux/soc/qcom/ubwc.h
+1
-1
include/linux/soc/qcom/ubwc.h
···
53
53
#define UBWC_4_3 0x40030000
54
54
#define UBWC_5_0 0x50000000
55
55
56
-
#ifdef CONFIG_QCOM_UBWC_CONFIG
56
+
#if IS_ENABLED(CONFIG_QCOM_UBWC_CONFIG)
57
57
const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
58
58
#else
59
59
static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)