tjh.dev / kernel
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 updates from Will Deacon:
"There's a little less than normal, probably due to LPC & Christmas/New
Year meaning that a few series weren't quite ready or reviewed in
time. It's still useful across the board, despite the only real
feature being support for the LS64 feature enabling 64-byte atomic
accesses to endpoints that support it.

ACPI:
- Add interrupt signalling support to the AGDI handler
- Add Catalin and myself to the arm64 ACPI MAINTAINERS entry

CPU features:
- Drop Kconfig options for PAN and LSE (these are detected at runtime)
- Add support for 64-byte single-copy atomic instructions (LS64/LS64V)
- Reduce MTE overhead when executing in the kernel on Ampere CPUs
- Ensure POR_EL0 value exposed via ptrace is up-to-date
- Fix error handling on GCS allocation failure

CPU frequency:
- Add CPU hotplug support to the FIE setup in the AMU driver

Entry code:
- Minor optimisations and cleanups to the syscall entry path
- Preparatory rework for moving to the generic syscall entry code

Hardware errata:
- Work around Spectre-BHB on TSV110 processors
- Work around broken CMO propagation on some systems with the SI-L1
interconnect

Miscellaneous:
- Disable branch profiling for arch/arm64/ to avoid issues with
noinstr
- Minor fixes and cleanups (kexec + ubsan, WARN_ONCE() instead of
WARN_ON(), reduction of boolean expression)
- Fix custom __READ_ONCE() implementation for LTO builds when
operating on non-atomic types

Perf and PMUs:
- Support for CMN-600AE
- Be stricter about supported hardware in the CMN driver
- Support for DSU-110 and DSU-120
- Support for the cycles event in the DSU driver (alongside the
dedicated cycles counter)
- Use IRQF_NO_THREAD instead of IRQF_ONESHOT in the cxlpmu driver
- Use !bitmap_empty() as a faster alternative to bitmap_weight()
- Fix SPE error handling when failing to resume profiling

Selftests:
- Add support for the FORCE_TARGETS option to the arm64 kselftests
- Avoid nolibc-specific my_syscall() function
- Add basic test for the LS64 HWCAP
- Extend fp-pidbench to cover additional workload patterns"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (43 commits)
perf/arm-cmn: Reject unsupported hardware configurations
perf: arm_spe: Properly set hw.state on failures
arm64/gcs: Fix error handling in arch_set_shadow_stack_status()
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: poe: fix stale POR_EL0 values for ptrace
kselftest/arm64: Raise default number of loops in fp-pidbench
kselftest/arm64: Add a no-SVE loop after SVE in fp-pidbench
perf/cxlpmu: Replace IRQF_ONESHOT with IRQF_NO_THREAD
arm64: mte: Set TCMA1 whenever MTE is present in the kernel
arm64/ptrace: Return early for ptrace_report_syscall_entry() error
arm64/ptrace: Split report_syscall()
arm64: Remove unused _TIF_WORK_MASK
kselftest/arm64: Add missing file in .gitignore
arm64: errata: Workaround for SI L1 downstream coherency issue
kselftest/arm64: Add HWCAP test for FEAT_LS64
arm64: Add support for FEAT_{LS64, LS64_V}
KVM: arm64: Enable FEAT_{LS64, LS64_V} in the supported guest
arm64: Provide basic EL2 setup for FEAT_{LS64, LS64_V} usage at EL0/1
KVM: arm64: Handle DABT caused by LS64* instructions on unsupported memory
KVM: arm64: Add documentation for KVM_EXIT_ARM_LDST64B
...

Linus Torvalds 45bf4bc8 9f722cb7

+628 -216
+12
Documentation/arch/arm64/booting.rst
··· 556 556 557 557 - MDCR_EL3.TPM (bit 6) must be initialized to 0b0 558 558 559 + For CPUs with support for 64-byte loads and stores without status (FEAT_LS64): 560 + 561 + - If the kernel is entered at EL1 and EL2 is present: 562 + 563 + - HCRX_EL2.EnALS (bit 1) must be initialised to 0b1. 564 + 565 + For CPUs with support for 64-byte stores with status (FEAT_LS64_V): 566 + 567 + - If the kernel is entered at EL1 and EL2 is present: 568 + 569 + - HCRX_EL2.EnASR (bit 2) must be initialised to 0b1. 570 + 559 571 The requirements described above for CPU mode, caches, MMUs, architected 560 572 timers, coherency and system registers apply to all CPUs. All CPUs must 561 573 enter the kernel in the same exception level. Where the values documented
+7
Documentation/arch/arm64/elf_hwcaps.rst
··· 444 444 HWCAP3_LSFE 445 445 Functionality implied by ID_AA64ISAR3_EL1.LSFE == 0b0001 446 446 447 + HWCAP3_LS64 448 + Functionality implied by ID_AA64ISAR1_EL1.LS64 == 0b0001. Note that 449 + the function of instruction ld64b/st64b requires support by CPU, system 450 + and target (device) memory location and HWCAP3_LS64 implies the support 451 + of CPU. User should only use ld64b/st64b on supported target (device) 452 + memory location, otherwise fallback to the non-atomic alternatives. 453 + 447 454 448 455 4. Unused AT_HWCAP bits 449 456 -----------------------
+1
Documentation/arch/arm64/silicon-errata.rst
··· 212 212 +----------------+-----------------+-----------------+-----------------------------+ 213 213 | ARM | GIC-700 | #2941627 | ARM64_ERRATUM_2941627 | 214 214 +----------------+-----------------+-----------------+-----------------------------+ 215 + | ARM | SI L1 | #4311569 | ARM64_ERRATUM_4311569 | 215 216 +----------------+-----------------+-----------------+-----------------------------+ 216 217 | Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 | 217 218 +----------------+-----------------+-----------------+-----------------------------+
+36 -7
Documentation/virt/kvm/api.rst
··· 1303 1303 information or because there is no device mapped at the accessed IPA, then 1304 1304 userspace can ask the kernel to inject an external abort using the address 1305 1305 from the exiting fault on the VCPU. It is a programming error to set 1306 - ext_dabt_pending after an exit which was not either KVM_EXIT_MMIO or 1307 - KVM_EXIT_ARM_NISV. This feature is only available if the system supports 1308 - KVM_CAP_ARM_INJECT_EXT_DABT. This is a helper which provides commonality in 1309 - how userspace reports accesses for the above cases to guests, across different 1310 - userspace implementations. Nevertheless, userspace can still emulate all Arm 1311 - exceptions by manipulating individual registers using the KVM_SET_ONE_REG API. 1306 + ext_dabt_pending after an exit which was not either KVM_EXIT_MMIO, 1307 + KVM_EXIT_ARM_NISV, or KVM_EXIT_ARM_LDST64B. This feature is only available if 1308 + the system supports KVM_CAP_ARM_INJECT_EXT_DABT. This is a helper which 1309 + provides commonality in how userspace reports accesses for the above cases to 1310 + guests, across different userspace implementations. Nevertheless, userspace 1311 + can still emulate all Arm exceptions by manipulating individual registers 1312 + using the KVM_SET_ONE_REG API. 1312 1313 1313 1314 See KVM_GET_VCPU_EVENTS for the data structure. 1314 1315 ··· 7051 7050 7052 7051 :: 7053 7052 7054 - /* KVM_EXIT_ARM_NISV */ 7053 + /* KVM_EXIT_ARM_NISV / KVM_EXIT_ARM_LDST64B */ 7055 7054 struct { 7056 7055 __u64 esr_iss; 7057 7056 __u64 fault_ipa; 7058 7057 } arm_nisv; 7058 + 7059 + - KVM_EXIT_ARM_NISV: 7059 7060 7060 7061 Used on arm64 systems. If a guest accesses memory not in a memslot, 7061 7062 KVM will typically return to userspace and ask it to do MMIO emulation on its ··· 7091 7088 Note that although KVM_CAP_ARM_NISV_TO_USER will be reported if 7092 7089 queried outside of a protected VM context, the feature will not be 7093 7090 exposed if queried on a protected VM file descriptor. 7091 + 7092 + - KVM_EXIT_ARM_LDST64B: 7093 + 7094 + Used on arm64 systems. When a guest using a LD64B, ST64B, ST64BV, ST64BV0, 7095 + outside of a memslot, KVM will return to userspace with KVM_EXIT_ARM_LDST64B, 7096 + exposing the relevant ESR_EL2 information and faulting IPA, similarly to 7097 + KVM_EXIT_ARM_NISV. 7098 + 7099 + Userspace is supposed to fully emulate the instructions, which includes: 7100 + 7101 + - fetch of the operands for a store, including ACCDATA_EL1 in the case 7102 + of a ST64BV0 instruction 7103 + - deal with the endianness if the guest is big-endian 7104 + - emulate the access, including the delivery of an exception if the 7105 + access didn't succeed 7106 + - provide a return value in the case of ST64BV/ST64BV0 7107 + - return the data in the case of a load 7108 + - increment PC if the instruction was successfully executed 7109 + 7110 + Note that there is no expectation of performance for this emulation, as it 7111 + involves a large number of interaction with the guest state. It is, however, 7112 + expected that the instruction's semantics are preserved, specially the 7113 + single-copy atomicity property of the 64 byte access. 7114 + 7115 + This exit reason must be handled if userspace sets ID_AA64ISAR1_EL1.LS64 to a 7116 + non-zero value, indicating that FEAT_LS64* is enabled. 7094 7117 7095 7118 :: 7096 7119
+2
MAINTAINERS
··· 336 336 M: Lorenzo Pieralisi <lpieralisi@kernel.org> 337 337 M: Hanjun Guo <guohanjun@huawei.com> 338 338 M: Sudeep Holla <sudeep.holla@kernel.org> 339 + M: Catalin Marinas <catalin.marinas@arm.com> 340 + M: Will Deacon <will@kernel.org> 339 341 L: linux-acpi@vger.kernel.org 340 342 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 341 343 S: Maintained
-2
arch/arm/include/asm/syscall.h
··· 92 92 (nr & __NR_SYSCALL_MASK); 93 93 } 94 94 95 - #define SYSCALL_MAX_ARGS 7 96 - 97 95 static inline void syscall_get_arguments(struct task_struct *task, 98 96 struct pt_regs *regs, 99 97 unsigned long *args)
+4
arch/arm64/Kbuild
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 + 3 + # Branch profiling isn't noinstr-safe 4 + subdir-ccflags-$(CONFIG_TRACE_BRANCH_PROFILING) += -DDISABLE_BRANCH_PROFILING 5 + 2 6 obj-y += kernel/ mm/ net/ 3 7 obj-$(CONFIG_KVM) += kvm/ 4 8 obj-$(CONFIG_XEN) += xen/
+19 -33
arch/arm64/Kconfig
··· 1155 1155 1156 1156 If unsure, say Y. 1157 1157 1158 + config ARM64_ERRATUM_4311569 1159 + bool "SI L1: 4311569: workaround for premature CMO completion erratum" 1160 + default y 1161 + help 1162 + This option adds the workaround for ARM SI L1 erratum 4311569. 1163 + 1164 + The erratum of SI L1 can cause an early response to a combined write 1165 + and cache maintenance operation (WR+CMO) before the operation is fully 1166 + completed to the Point of Serialization (POS). 1167 + This can result in a non-I/O coherent agent observing stale data, 1168 + potentially leading to system instability or incorrect behavior. 1169 + 1170 + Enabling this option implements a software workaround by inserting a 1171 + second loop of Cache Maintenance Operation (CMO) immediately following the 1172 + end of function to do CMOs. This ensures that the data is correctly serialized 1173 + before the buffer is handed off to a non-coherent agent. 1174 + 1175 + If unsure, say Y. 1176 + 1158 1177 config CAVIUM_ERRATUM_22375 1159 1178 bool "Cavium erratum 22375, 24313" 1160 1179 default y ··· 1699 1680 config ARM64_SW_TTBR0_PAN 1700 1681 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1701 1682 depends on !KCSAN 1702 - select ARM64_PAN 1703 1683 help 1704 1684 Enabling this option prevents the kernel from accessing 1705 1685 user-space memory directly by pointing TTBR0_EL1 to a reserved ··· 1876 1858 Kernels built with this configuration option enabled continue 1877 1859 to work on pre-ARMv8.1 hardware and the performance impact is 1878 1860 minimal. If unsure, say Y. 1879 - 1880 - config ARM64_PAN 1881 - bool "Enable support for Privileged Access Never (PAN)" 1882 - default y 1883 - help 1884 - Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1885 - prevents the kernel or hypervisor from accessing user-space (EL0) 1886 - memory directly. 1887 - 1888 - Choosing this option will cause any unprotected (not using 1889 - copy_to_user et al) memory access to fail with a permission fault. 1890 - 1891 - The feature is detected at runtime, and will remain as a 'nop' 1892 - instruction if the cpu does not implement the feature. 1893 - 1894 - config ARM64_LSE_ATOMICS 1895 - bool 1896 - default ARM64_USE_LSE_ATOMICS 1897 - 1898 - config ARM64_USE_LSE_ATOMICS 1899 - bool "Atomic instructions" 1900 - default y 1901 - help 1902 - As part of the Large System Extensions, ARMv8.1 introduces new 1903 - atomic instructions that are designed specifically to scale in 1904 - very large systems. 1905 - 1906 - Say Y here to make use of these instructions for the in-kernel 1907 - atomic routines. This incurs a small overhead on CPUs that do 1908 - not support these instructions. 1909 1861 1910 1862 endmenu # "ARMv8.1 architectural features" 1911 1863 ··· 2113 2125 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2114 2126 depends on AS_HAS_ARMV8_5 2115 2127 # Required for tag checking in the uaccess routines 2116 - select ARM64_PAN 2117 2128 select ARCH_HAS_SUBPAGE_FAULTS 2118 2129 select ARCH_USES_HIGH_VMA_FLAGS 2119 2130 select ARCH_USES_PG_ARCH_2 ··· 2144 2157 config ARM64_EPAN 2145 2158 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2146 2159 default y 2147 - depends on ARM64_PAN 2148 2160 help 2149 2161 Enhanced Privileged Access Never (EPAN) allows Privileged 2150 2162 Access Never to be used with Execute-only mappings.
+10
arch/arm64/include/asm/assembler.h
··· 381 381 .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup 382 382 sub \tmp, \linesz, #1 383 383 bic \start, \start, \tmp 384 + alternative_if ARM64_WORKAROUND_4311569 385 + mov \tmp, \start 386 + alternative_else_nop_endif 384 387 .Ldcache_op\@: 385 388 .ifc \op, cvau 386 389 __dcache_op_workaround_clean_cache \op, \start ··· 405 402 add \start, \start, \linesz 406 403 cmp \start, \end 407 404 b.lo .Ldcache_op\@ 405 + alternative_if ARM64_WORKAROUND_4311569 406 + .ifnc \op, cvau 407 + mov \start, \tmp 408 + mov \tmp, xzr 409 + cbnz \start, .Ldcache_op\@ 410 + .endif 411 + alternative_else_nop_endif 408 412 dsb \domain 409 413 410 414 _cond_uaccess_extable .Ldcache_op\@, \fixup
-2
arch/arm64/include/asm/cpucaps.h
··· 19 19 "cap must be < ARM64_NCAPS"); 20 20 21 21 switch (cap) { 22 - case ARM64_HAS_PAN: 23 - return IS_ENABLED(CONFIG_ARM64_PAN); 24 22 case ARM64_HAS_EPAN: 25 23 return IS_ENABLED(CONFIG_ARM64_EPAN); 26 24 case ARM64_SVE:
+11 -1
arch/arm64/include/asm/el2_setup.h
··· 83 83 /* Enable GCS if supported */ 84 84 mrs_s x1, SYS_ID_AA64PFR1_EL1 85 85 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 86 - cbz x1, .Lset_hcrx_\@ 86 + cbz x1, .Lskip_gcs_hcrx_\@ 87 87 orr x0, x0, #HCRX_EL2_GCSEn 88 + 89 + .Lskip_gcs_hcrx_\@: 90 + /* Enable LS64, LS64_V if supported */ 91 + mrs_s x1, SYS_ID_AA64ISAR1_EL1 92 + ubfx x1, x1, #ID_AA64ISAR1_EL1_LS64_SHIFT, #4 93 + cbz x1, .Lset_hcrx_\@ 94 + orr x0, x0, #HCRX_EL2_EnALS 95 + cmp x1, #ID_AA64ISAR1_EL1_LS64_LS64_V 96 + b.lt .Lset_hcrx_\@ 97 + orr x0, x0, #HCRX_EL2_EnASR 88 98 89 99 .Lset_hcrx_\@: 90 100 msr_s SYS_HCRX_EL2, x0
+8
arch/arm64/include/asm/esr.h
··· 124 124 #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) 125 125 #define ESR_ELx_FSC_SECC (0x18) 126 126 #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) 127 + #define ESR_ELx_FSC_EXCL_ATOMIC (0x35) 127 128 #define ESR_ELx_FSC_ADDRSZ (0x00) 128 129 129 130 /* ··· 487 486 (esr == ESR_ELx_FSC_ACCESS_L(2)) || 488 487 (esr == ESR_ELx_FSC_ACCESS_L(1)) || 489 488 (esr == ESR_ELx_FSC_ACCESS_L(0)); 489 + } 490 + 491 + static inline bool esr_fsc_is_excl_atomic_fault(unsigned long esr) 492 + { 493 + esr = esr & ESR_ELx_FSC; 494 + 495 + return esr == ESR_ELx_FSC_EXCL_ATOMIC; 490 496 } 491 497 492 498 static inline bool esr_fsc_is_addr_sz_fault(unsigned long esr)
+1
arch/arm64/include/asm/hwcap.h
··· 179 179 #define KERNEL_HWCAP_MTE_FAR __khwcap3_feature(MTE_FAR) 180 180 #define KERNEL_HWCAP_MTE_STORE_ONLY __khwcap3_feature(MTE_STORE_ONLY) 181 181 #define KERNEL_HWCAP_LSFE __khwcap3_feature(LSFE) 182 + #define KERNEL_HWCAP_LS64 __khwcap3_feature(LS64) 182 183 183 184 /* 184 185 * This yields a mask that user programs can use to figure out what
-23
arch/arm64/include/asm/insn.h
··· 671 671 enum aarch64_insn_register Rn, 672 672 enum aarch64_insn_register Rd, 673 673 u8 lsb); 674 - #ifdef CONFIG_ARM64_LSE_ATOMICS 675 674 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result, 676 675 enum aarch64_insn_register address, 677 676 enum aarch64_insn_register value, ··· 682 683 enum aarch64_insn_register value, 683 684 enum aarch64_insn_size_type size, 684 685 enum aarch64_insn_mem_order_type order); 685 - #else 686 - static inline 687 - u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result, 688 - enum aarch64_insn_register address, 689 - enum aarch64_insn_register value, 690 - enum aarch64_insn_size_type size, 691 - enum aarch64_insn_mem_atomic_op op, 692 - enum aarch64_insn_mem_order_type order) 693 - { 694 - return AARCH64_BREAK_FAULT; 695 - } 696 - 697 - static inline 698 - u32 aarch64_insn_gen_cas(enum aarch64_insn_register result, 699 - enum aarch64_insn_register address, 700 - enum aarch64_insn_register value, 701 - enum aarch64_insn_size_type size, 702 - enum aarch64_insn_mem_order_type order) 703 - { 704 - return AARCH64_BREAK_FAULT; 705 - } 706 - #endif 707 686 u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type); 708 687 u32 aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type); 709 688 u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
+7
arch/arm64/include/asm/kvm_emulate.h
··· 47 47 void kvm_inject_undefined(struct kvm_vcpu *vcpu); 48 48 int kvm_inject_serror_esr(struct kvm_vcpu *vcpu, u64 esr); 49 49 int kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr); 50 + int kvm_inject_dabt_excl_atomic(struct kvm_vcpu *vcpu, u64 addr); 50 51 void kvm_inject_size_fault(struct kvm_vcpu *vcpu); 51 52 52 53 static inline int kvm_inject_sea_dabt(struct kvm_vcpu *vcpu, u64 addr) ··· 679 678 680 679 if (kvm_has_sctlr2(kvm)) 681 680 vcpu->arch.hcrx_el2 |= HCRX_EL2_SCTLR2En; 681 + 682 + if (kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64)) 683 + vcpu->arch.hcrx_el2 |= HCRX_EL2_EnALS; 684 + 685 + if (kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V)) 686 + vcpu->arch.hcrx_el2 |= HCRX_EL2_EnASR; 682 687 } 683 688 } 684 689 #endif /* __ARM64_KVM_EMULATE_H__ */
-9
arch/arm64/include/asm/lse.h
··· 4 4 5 5 #include <asm/atomic_ll_sc.h> 6 6 7 - #ifdef CONFIG_ARM64_LSE_ATOMICS 8 - 9 7 #define __LSE_PREAMBLE ".arch_extension lse\n" 10 8 11 9 #include <linux/compiler_types.h> ··· 25 27 #define ARM64_LSE_ATOMIC_INSN(llsc, lse) \ 26 28 ALTERNATIVE(llsc, __LSE_PREAMBLE lse, ARM64_HAS_LSE_ATOMICS) 27 29 28 - #else /* CONFIG_ARM64_LSE_ATOMICS */ 29 - 30 - #define __lse_ll_sc_body(op, ...) __ll_sc_##op(__VA_ARGS__) 31 - 32 - #define ARM64_LSE_ATOMIC_INSN(llsc, lse) llsc 33 - 34 - #endif /* CONFIG_ARM64_LSE_ATOMICS */ 35 30 #endif /* __ASM_LSE_H */
+1 -1
arch/arm64/include/asm/rwonce.h
··· 58 58 default: \ 59 59 atomic = 0; \ 60 60 } \ 61 - atomic ? (typeof(*__x))__u.__val : (*(volatile typeof(__x))__x);\ 61 + atomic ? (typeof(*__x))__u.__val : (*(volatile typeof(*__x) *)__x);\ 62 62 }) 63 63 64 64 #endif /* !BUILD_VDSO */
+12 -6
arch/arm64/include/asm/syscall.h
··· 77 77 } 78 78 } 79 79 80 - #define SYSCALL_MAX_ARGS 6 81 - 82 80 static inline void syscall_get_arguments(struct task_struct *task, 83 81 struct pt_regs *regs, 84 82 unsigned long *args) 85 83 { 86 84 args[0] = regs->orig_x0; 87 - args++; 88 - 89 - memcpy(args, &regs->regs[1], 5 * sizeof(args[0])); 85 + args[1] = regs->regs[1]; 86 + args[2] = regs->regs[2]; 87 + args[3] = regs->regs[3]; 88 + args[4] = regs->regs[4]; 89 + args[5] = regs->regs[5]; 90 90 } 91 91 92 92 static inline void syscall_set_arguments(struct task_struct *task, 93 93 struct pt_regs *regs, 94 94 const unsigned long *args) 95 95 { 96 - memcpy(&regs->regs[0], args, 6 * sizeof(args[0])); 96 + regs->regs[0] = args[0]; 97 + regs->regs[1] = args[1]; 98 + regs->regs[2] = args[2]; 99 + regs->regs[3] = args[3]; 100 + regs->regs[4] = args[4]; 101 + regs->regs[5] = args[5]; 102 + 97 103 /* 98 104 * Also copy the first argument into orig_x0 99 105 * so that syscall_get_arguments() would return it
-6
arch/arm64/include/asm/thread_info.h
··· 106 106 #define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) 107 107 #define _TIF_TSC_SIGSEGV (1 << TIF_TSC_SIGSEGV) 108 108 109 - #define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY | \ 110 - _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \ 111 - _TIF_UPROBE | _TIF_MTE_ASYNC_FAULT | \ 112 - _TIF_NOTIFY_SIGNAL | _TIF_SIGPENDING | \ 113 - _TIF_PATCH_PENDING) 114 - 115 109 #define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ 116 110 _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \ 117 111 _TIF_SYSCALL_EMU)
+2 -4
arch/arm64/include/asm/uaccess.h
··· 124 124 125 125 static inline void __uaccess_disable_hw_pan(void) 126 126 { 127 - asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, 128 - CONFIG_ARM64_PAN)); 127 + asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN)); 129 128 } 130 129 131 130 static inline void __uaccess_enable_hw_pan(void) 132 131 { 133 - asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, 134 - CONFIG_ARM64_PAN)); 132 + asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN)); 135 133 } 136 134 137 135 static inline void uaccess_disable_privileged(void)
+1
arch/arm64/include/uapi/asm/hwcap.h
··· 146 146 #define HWCAP3_MTE_FAR (1UL << 0) 147 147 #define HWCAP3_MTE_STORE_ONLY (1UL << 1) 148 148 #define HWCAP3_LSFE (1UL << 2) 149 + #define HWCAP3_LS64 (1UL << 3) 149 150 150 151 #endif /* _UAPI__ASM_HWCAP_H */
+31
arch/arm64/kernel/cpu_errata.c
··· 141 141 return (ctr_real != sys) && (ctr_raw != sys); 142 142 } 143 143 144 + #ifdef CONFIG_ARM64_ERRATUM_4311569 145 + static DEFINE_STATIC_KEY_FALSE(arm_si_l1_workaround_4311569); 146 + static int __init early_arm_si_l1_workaround_4311569_cfg(char *arg) 147 + { 148 + static_branch_enable(&arm_si_l1_workaround_4311569); 149 + pr_info("Enabling cache maintenance workaround for ARM SI-L1 erratum 4311569\n"); 150 + 151 + return 0; 152 + } 153 + early_param("arm_si_l1_workaround_4311569", early_arm_si_l1_workaround_4311569_cfg); 154 + 155 + /* 156 + * We have some earlier use cases to call cache maintenance operation functions, for example, 157 + * dcache_inval_poc() and dcache_clean_poc() in head.S, before making decision to turn on this 158 + * workaround. Since the scope of this workaround is limited to non-coherent DMA agents, its 159 + * safe to have the workaround off by default. 160 + */ 161 + static bool 162 + need_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities *entry, int scope) 163 + { 164 + return static_branch_unlikely(&arm_si_l1_workaround_4311569); 165 + } 166 + #endif 167 + 144 168 static void 145 169 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 146 170 { ··· 892 868 .desc = "SSBS not fully self-synchronizing", 893 869 .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, 894 870 ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), 871 + }, 872 + #endif 873 + #ifdef CONFIG_ARM64_ERRATUM_4311569 874 + { 875 + .capability = ARM64_WORKAROUND_4311569, 876 + .type = ARM64_CPUCAP_SYSTEM_FEATURE, 877 + .matches = need_arm_si_l1_workaround_4311569, 895 878 }, 896 879 #endif 897 880 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
+28 -6
arch/arm64/kernel/cpufeature.c
··· 240 240 }; 241 241 242 242 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 243 + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LS64_SHIFT, 4, 0), 243 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 244 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 245 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), ··· 2165 2164 return cpu_supports_bbml2_noabort(); 2166 2165 } 2167 2166 2168 - #ifdef CONFIG_ARM64_PAN 2169 2167 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2170 2168 { 2171 2169 /* ··· 2176 2176 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2177 2177 set_pstate_pan(1); 2178 2178 } 2179 - #endif /* CONFIG_ARM64_PAN */ 2180 2179 2181 2180 #ifdef CONFIG_ARM64_RAS_EXTN 2182 2181 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) ··· 2258 2259 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2259 2260 } 2260 2261 #endif /* CONFIG_ARM64_E0PD */ 2262 + 2263 + static void cpu_enable_ls64(struct arm64_cpu_capabilities const *cap) 2264 + { 2265 + sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnALS, SCTLR_EL1_EnALS); 2266 + } 2267 + 2268 + static void cpu_enable_ls64_v(struct arm64_cpu_capabilities const *cap) 2269 + { 2270 + sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnASR, 0); 2271 + } 2261 2272 2262 2273 #ifdef CONFIG_ARM64_PSEUDO_NMI 2263 2274 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, ··· 2550 2541 .matches = has_cpuid_feature, 2551 2542 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2552 2543 }, 2553 - #ifdef CONFIG_ARM64_PAN 2554 2544 { 2555 2545 .desc = "Privileged Access Never", 2556 2546 .capability = ARM64_HAS_PAN, ··· 2558 2550 .cpu_enable = cpu_enable_pan, 2559 2551 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2560 2552 }, 2561 - #endif /* CONFIG_ARM64_PAN */ 2562 2553 #ifdef CONFIG_ARM64_EPAN 2563 2554 { 2564 2555 .desc = "Enhanced Privileged Access Never", ··· 2567 2560 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2568 2561 }, 2569 2562 #endif /* CONFIG_ARM64_EPAN */ 2570 - #ifdef CONFIG_ARM64_LSE_ATOMICS 2571 2563 { 2572 2564 .desc = "LSE atomic instructions", 2573 2565 .capability = ARM64_HAS_LSE_ATOMICS, ··· 2574 2568 .matches = has_cpuid_feature, 2575 2569 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2576 2570 }, 2577 - #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2578 2571 { 2579 2572 .desc = "Virtualization Host Extensions", 2580 2573 .capability = ARM64_HAS_VIRT_HOST_EXTN, ··· 3153 3148 .matches = has_cpuid_feature, 3154 3149 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3155 3150 }, 3151 + { 3152 + .desc = "LS64", 3153 + .capability = ARM64_HAS_LS64, 3154 + .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3155 + .matches = has_cpuid_feature, 3156 + .cpu_enable = cpu_enable_ls64, 3157 + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64) 3158 + }, 3159 + { 3160 + .desc = "LS64_V", 3161 + .capability = ARM64_HAS_LS64_V, 3162 + .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3163 + .matches = has_cpuid_feature, 3164 + .cpu_enable = cpu_enable_ls64_v, 3165 + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3166 + }, 3156 3167 {}, 3157 3168 }; 3158 3169 ··· 3288 3267 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3289 3268 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3290 3269 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3270 + HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), 3291 3271 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3292 3272 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3293 3273 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE),
+1
arch/arm64/kernel/cpuinfo.c
··· 81 81 [KERNEL_HWCAP_PACA] = "paca", 82 82 [KERNEL_HWCAP_PACG] = "pacg", 83 83 [KERNEL_HWCAP_GCS] = "gcs", 84 + [KERNEL_HWCAP_LS64] = "ls64", 84 85 [KERNEL_HWCAP_DCPODP] = "dcpodp", 85 86 [KERNEL_HWCAP_SVE2] = "sve2", 86 87 [KERNEL_HWCAP_SVEAES] = "sveaes",
+1 -1
arch/arm64/kernel/kexec_image.c
··· 41 41 struct arm64_image_header *h; 42 42 u64 flags, value; 43 43 bool be_image, be_kernel; 44 - struct kexec_buf kbuf; 44 + struct kexec_buf kbuf = {}; 45 45 unsigned long text_offset, kernel_segment_number; 46 46 struct kexec_segment *kernel_segment; 47 47 int ret;
+1 -4
arch/arm64/kernel/probes/uprobes.c
··· 103 103 * insn itself is trapped, then detect the case with the help of 104 104 * invalid fault code which is being set in arch_uprobe_pre_xol 105 105 */ 106 - if (t->thread.fault_code != UPROBE_INV_FAULT_CODE) 107 - return true; 108 - 109 - return false; 106 + return t->thread.fault_code != UPROBE_INV_FAULT_CODE; 110 107 } 111 108 112 109 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
+1
arch/arm64/kernel/proton-pack.c
··· 887 887 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 888 888 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 889 889 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 890 + MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 890 891 {}, 891 892 }; 892 893 static const struct midr_range spectre_bhb_k24_list[] = {
+37 -13
arch/arm64/kernel/ptrace.c
··· 1484 1484 if (!system_supports_poe()) 1485 1485 return -EINVAL; 1486 1486 1487 + if (target == current) 1488 + current->thread.por_el0 = read_sysreg_s(SYS_POR_EL0); 1489 + 1487 1490 return membuf_write(&to, &target->thread.por_el0, 1488 1491 sizeof(target->thread.por_el0)); 1489 1492 } ··· 2344 2341 PTRACE_SYSCALL_EXIT, 2345 2342 }; 2346 2343 2347 - static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir) 2344 + static __always_inline unsigned long ptrace_save_reg(struct pt_regs *regs, 2345 + enum ptrace_syscall_dir dir, 2346 + int *regno) 2348 2347 { 2349 - int regno; 2350 2348 unsigned long saved_reg; 2351 2349 2352 2350 /* ··· 2366 2362 * - Syscall stops behave differently to seccomp and pseudo-step traps 2367 2363 * (the latter do not nobble any registers). 2368 2364 */ 2369 - regno = (is_compat_task() ? 12 : 7); 2370 - saved_reg = regs->regs[regno]; 2371 - regs->regs[regno] = dir; 2365 + *regno = (is_compat_task() ? 12 : 7); 2366 + saved_reg = regs->regs[*regno]; 2367 + regs->regs[*regno] = dir; 2372 2368 2373 - if (dir == PTRACE_SYSCALL_ENTER) { 2374 - if (ptrace_report_syscall_entry(regs)) 2375 - forget_syscall(regs); 2376 - regs->regs[regno] = saved_reg; 2377 - } else if (!test_thread_flag(TIF_SINGLESTEP)) { 2369 + return saved_reg; 2370 + } 2371 + 2372 + static int report_syscall_entry(struct pt_regs *regs) 2373 + { 2374 + unsigned long saved_reg; 2375 + int regno, ret; 2376 + 2377 + saved_reg = ptrace_save_reg(regs, PTRACE_SYSCALL_ENTER, &regno); 2378 + ret = ptrace_report_syscall_entry(regs); 2379 + if (ret) 2380 + forget_syscall(regs); 2381 + regs->regs[regno] = saved_reg; 2382 + 2383 + return ret; 2384 + } 2385 + 2386 + static void report_syscall_exit(struct pt_regs *regs) 2387 + { 2388 + unsigned long saved_reg; 2389 + int regno; 2390 + 2391 + saved_reg = ptrace_save_reg(regs, PTRACE_SYSCALL_EXIT, &regno); 2392 + if (!test_thread_flag(TIF_SINGLESTEP)) { 2378 2393 ptrace_report_syscall_exit(regs, 0); 2379 2394 regs->regs[regno] = saved_reg; 2380 2395 } else { ··· 2411 2388 int syscall_trace_enter(struct pt_regs *regs) 2412 2389 { 2413 2390 unsigned long flags = read_thread_flags(); 2391 + int ret; 2414 2392 2415 2393 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { 2416 - report_syscall(regs, PTRACE_SYSCALL_ENTER); 2417 - if (flags & _TIF_SYSCALL_EMU) 2394 + ret = report_syscall_entry(regs); 2395 + if (ret || (flags & _TIF_SYSCALL_EMU)) 2418 2396 return NO_SYSCALL; 2419 2397 } 2420 2398 ··· 2442 2418 trace_sys_exit(regs, syscall_get_return_value(current, regs)); 2443 2419 2444 2420 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) 2445 - report_syscall(regs, PTRACE_SYSCALL_EXIT); 2421 + report_syscall_exit(regs); 2446 2422 2447 2423 rseq_syscall(regs); 2448 2424 }
+63 -3
arch/arm64/kernel/topology.c
··· 272 272 273 273 cpumask_or(amu_fie_cpus, amu_fie_cpus, cpus); 274 274 275 - topology_set_scale_freq_source(&amu_sfd, amu_fie_cpus); 275 + topology_set_scale_freq_source(&amu_sfd, cpus); 276 276 277 277 pr_debug("CPUs[%*pbl]: counters will be used for FIE.", 278 278 cpumask_pr_args(cpus)); ··· 284 284 struct cpufreq_policy *policy = data; 285 285 286 286 if (val == CPUFREQ_CREATE_POLICY) 287 - amu_fie_setup(policy->related_cpus); 287 + amu_fie_setup(policy->cpus); 288 288 289 289 /* 290 290 * We don't need to handle CPUFREQ_REMOVE_POLICY event as the AMU ··· 303 303 .notifier_call = init_amu_fie_callback, 304 304 }; 305 305 306 + static int cpuhp_topology_online(unsigned int cpu) 307 + { 308 + struct cpufreq_policy *policy = cpufreq_cpu_policy(cpu); 309 + 310 + /* Those are cheap checks */ 311 + 312 + /* 313 + * Skip this CPU if: 314 + * - it has no cpufreq policy assigned yet, 315 + * - no policy exists that spans CPUs with AMU counters, or 316 + * - it was already handled. 317 + */ 318 + if (unlikely(!policy) || !cpumask_available(amu_fie_cpus) || 319 + cpumask_test_cpu(cpu, amu_fie_cpus)) 320 + return 0; 321 + 322 + /* 323 + * Only proceed if all already-online CPUs in this policy 324 + * support AMU counters. 325 + */ 326 + if (unlikely(!cpumask_subset(policy->cpus, amu_fie_cpus))) 327 + return 0; 328 + 329 + /* 330 + * If the new online CPU cannot pass this check, all the CPUs related to 331 + * the same policy should be clear from amu_fie_cpus mask, otherwise they 332 + * may use different source of the freq scale. 333 + */ 334 + if (!freq_counters_valid(cpu)) { 335 + topology_clear_scale_freq_source(SCALE_FREQ_SOURCE_ARCH, 336 + policy->related_cpus); 337 + cpumask_andnot(amu_fie_cpus, amu_fie_cpus, policy->related_cpus); 338 + return 0; 339 + } 340 + 341 + cpumask_set_cpu(cpu, amu_fie_cpus); 342 + 343 + topology_set_scale_freq_source(&amu_sfd, cpumask_of(cpu)); 344 + 345 + pr_debug("CPU[%u]: counter will be used for FIE.", cpu); 346 + 347 + return 0; 348 + } 349 + 306 350 static int __init init_amu_fie(void) 307 351 { 308 - return cpufreq_register_notifier(&init_amu_fie_notifier, 352 + int ret; 353 + 354 + ret = cpufreq_register_notifier(&init_amu_fie_notifier, 309 355 CPUFREQ_POLICY_NOTIFIER); 356 + if (ret) 357 + return ret; 358 + 359 + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, 360 + "arm64/topology:online", 361 + cpuhp_topology_online, 362 + NULL); 363 + if (ret < 0) { 364 + cpufreq_unregister_notifier(&init_amu_fie_notifier, 365 + CPUFREQ_POLICY_NOTIFIER); 366 + return ret; 367 + } 368 + 369 + return 0; 310 370 } 311 371 core_initcall(init_amu_fie); 312 372
-7
arch/arm64/kvm/at.c
··· 1704 1704 } 1705 1705 } 1706 1706 1707 - #ifdef CONFIG_ARM64_LSE_ATOMICS 1708 1707 static int __lse_swap_desc(u64 __user *ptep, u64 old, u64 new) 1709 1708 { 1710 1709 u64 tmp = old; ··· 1728 1729 1729 1730 return ret; 1730 1731 } 1731 - #else 1732 - static int __lse_swap_desc(u64 __user *ptep, u64 old, u64 new) 1733 - { 1734 - return -EINVAL; 1735 - } 1736 - #endif 1737 1732 1738 1733 static int __llsc_swap_desc(u64 __user *ptep, u64 old, u64 new) 1739 1734 {
+1 -3
arch/arm64/kvm/hyp/entry.S
··· 126 126 127 127 add x1, x1, #VCPU_CONTEXT 128 128 129 - alternative_cb ARM64_ALWAYS_SYSTEM, kvm_pan_patch_el2_entry 130 - nop 131 - alternative_cb_end 129 + ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN) 132 130 133 131 // Store the guest regs x2 and x3 134 132 stp x2, x3, [x1, #CPU_XREG_OFFSET(2)]
+34
arch/arm64/kvm/inject_fault.c
··· 253 253 return 1; 254 254 } 255 255 256 + static int kvm_inject_nested_excl_atomic(struct kvm_vcpu *vcpu, u64 addr) 257 + { 258 + u64 esr = FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_DABT_LOW) | 259 + FIELD_PREP(ESR_ELx_FSC, ESR_ELx_FSC_EXCL_ATOMIC) | 260 + ESR_ELx_IL; 261 + 262 + vcpu_write_sys_reg(vcpu, addr, FAR_EL2); 263 + return kvm_inject_nested_sync(vcpu, esr); 264 + } 265 + 266 + /** 267 + * kvm_inject_dabt_excl_atomic - inject a data abort for unsupported exclusive 268 + * or atomic access 269 + * @vcpu: The VCPU to receive the data abort 270 + * @addr: The address to report in the DFAR 271 + * 272 + * It is assumed that this code is called from the VCPU thread and that the 273 + * VCPU therefore is not currently executing guest code. 274 + */ 275 + int kvm_inject_dabt_excl_atomic(struct kvm_vcpu *vcpu, u64 addr) 276 + { 277 + u64 esr; 278 + 279 + if (is_nested_ctxt(vcpu) && (vcpu_read_sys_reg(vcpu, HCR_EL2) & HCR_VM)) 280 + return kvm_inject_nested_excl_atomic(vcpu, addr); 281 + 282 + __kvm_inject_sea(vcpu, false, addr); 283 + esr = vcpu_read_sys_reg(vcpu, exception_esr_elx(vcpu)); 284 + esr &= ~ESR_ELx_FSC; 285 + esr |= ESR_ELx_FSC_EXCL_ATOMIC; 286 + vcpu_write_sys_reg(vcpu, esr, exception_esr_elx(vcpu)); 287 + return 1; 288 + } 289 + 256 290 void kvm_inject_size_fault(struct kvm_vcpu *vcpu) 257 291 { 258 292 unsigned long addr, esr;
+26 -1
arch/arm64/kvm/mmio.c
··· 159 159 bool is_write; 160 160 int len; 161 161 u8 data_buf[8]; 162 + u64 esr; 163 + 164 + esr = kvm_vcpu_get_esr(vcpu); 162 165 163 166 /* 164 167 * No valid syndrome? Ask userspace for help if it has ··· 171 168 * though, so directly deliver an exception to the guest. 172 169 */ 173 170 if (!kvm_vcpu_dabt_isvalid(vcpu)) { 174 - trace_kvm_mmio_nisv(*vcpu_pc(vcpu), kvm_vcpu_get_esr(vcpu), 171 + trace_kvm_mmio_nisv(*vcpu_pc(vcpu), esr, 175 172 kvm_vcpu_get_hfar(vcpu), fault_ipa); 176 173 177 174 if (vcpu_is_protected(vcpu)) ··· 186 183 } 187 184 188 185 return -ENOSYS; 186 + } 187 + 188 + /* 189 + * When (DFSC == 0b00xxxx || DFSC == 0b10101x) && DFSC != 0b0000xx 190 + * ESR_EL2[12:11] describe the Load/Store Type. This allows us to 191 + * punt the LD64B/ST64B/ST64BV/ST64BV0 instructions to userspace, 192 + * which will have to provide a full emulation of these 4 193 + * instructions. No, we don't expect this do be fast. 194 + * 195 + * We rely on traps being set if the corresponding features are not 196 + * enabled, so if we get here, userspace has promised us to handle 197 + * it already. 198 + */ 199 + switch (kvm_vcpu_trap_get_fault(vcpu)) { 200 + case 0b000100 ... 0b001111: 201 + case 0b101010 ... 0b101011: 202 + if (FIELD_GET(GENMASK(12, 11), esr)) { 203 + run->exit_reason = KVM_EXIT_ARM_LDST64B; 204 + run->arm_nisv.esr_iss = esr & ~(u64)ESR_ELx_FSC; 205 + run->arm_nisv.fault_ipa = fault_ipa; 206 + return 0; 207 + } 189 208 } 190 209 191 210 /*
+13 -1
arch/arm64/kvm/mmu.c
··· 1843 1843 return ret; 1844 1844 } 1845 1845 1846 + /* 1847 + * Guest performs atomic/exclusive operations on memory with unsupported 1848 + * attributes (e.g. ld64b/st64b on normal memory when no FEAT_LS64WB) 1849 + * and trigger the exception here. Since the memslot is valid, inject 1850 + * the fault back to the guest. 1851 + */ 1852 + if (esr_fsc_is_excl_atomic_fault(kvm_vcpu_get_esr(vcpu))) { 1853 + kvm_inject_dabt_excl_atomic(vcpu, kvm_vcpu_get_hfar(vcpu)); 1854 + return 1; 1855 + } 1856 + 1846 1857 if (nested) 1847 1858 adjust_nested_fault_perms(nested, &prot, &writable); 1848 1859 ··· 2091 2080 /* Check the stage-2 fault is trans. fault or write fault */ 2092 2081 if (!esr_fsc_is_translation_fault(esr) && 2093 2082 !esr_fsc_is_permission_fault(esr) && 2094 - !esr_fsc_is_access_flag_fault(esr)) { 2083 + !esr_fsc_is_access_flag_fault(esr) && 2084 + !esr_fsc_is_excl_atomic_fault(esr)) { 2095 2085 kvm_err("Unsupported FSC: EC=%#x xFSC=%#lx ESR_EL2=%#lx\n", 2096 2086 kvm_vcpu_trap_get_class(vcpu), 2097 2087 (unsigned long)kvm_vcpu_trap_get_fault(vcpu),
-2
arch/arm64/lib/insn.c
··· 611 611 state); 612 612 } 613 613 614 - #ifdef CONFIG_ARM64_LSE_ATOMICS 615 614 static u32 aarch64_insn_encode_ldst_order(enum aarch64_insn_mem_order_type type, 616 615 u32 insn) 617 616 { ··· 754 755 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn, 755 756 value); 756 757 } 757 - #endif 758 758 759 759 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst, 760 760 enum aarch64_insn_register src,
+2 -2
arch/arm64/mm/gcs.c
··· 199 199 200 200 size = gcs_size(0); 201 201 gcs = alloc_gcs(0, size); 202 - if (!gcs) 203 - return -ENOMEM; 202 + if (IS_ERR_VALUE(gcs)) 203 + return gcs; 204 204 205 205 task->thread.gcspr_el0 = gcs + size - sizeof(u64); 206 206 task->thread.gcs_base = gcs;
+2 -1
arch/arm64/mm/ioremap.c
··· 24 24 return NULL; 25 25 26 26 /* Don't allow RAM to be mapped. */ 27 - if (WARN_ON(pfn_is_map_memory(__phys_to_pfn(phys_addr)))) 27 + if (WARN_ONCE(pfn_is_map_memory(__phys_to_pfn(phys_addr)), 28 + "ioremap attempted on RAM pfn\n")) 28 29 return NULL; 29 30 30 31 /*
+5 -5
arch/arm64/mm/proc.S
··· 48 48 #define TCR_KASAN_SW_FLAGS 0 49 49 #endif 50 50 51 - #ifdef CONFIG_KASAN_HW_TAGS 52 - #define TCR_MTE_FLAGS TCR_EL1_TCMA1 | TCR_EL1_TBI1 | TCR_EL1_TBID1 53 - #elif defined(CONFIG_ARM64_MTE) 51 + #ifdef CONFIG_ARM64_MTE 54 52 /* 55 53 * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on 56 - * TBI being enabled at EL1. 54 + * TBI being enabled at EL1. TCMA1 is needed to treat accesses with the 55 + * match-all tag (0xF) as Tag Unchecked, irrespective of the SCTLR_EL1.TCF 56 + * setting. 57 57 */ 58 - #define TCR_MTE_FLAGS TCR_EL1_TBI1 | TCR_EL1_TBID1 58 + #define TCR_MTE_FLAGS TCR_EL1_TCMA1 | TCR_EL1_TBI1 | TCR_EL1_TBID1 59 59 #else 60 60 #define TCR_MTE_FLAGS 0 61 61 #endif
-7
arch/arm64/net/bpf_jit_comp.c
··· 776 776 return 0; 777 777 } 778 778 779 - #ifdef CONFIG_ARM64_LSE_ATOMICS 780 779 static int emit_lse_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 781 780 { 782 781 const u8 code = insn->code; ··· 842 843 843 844 return 0; 844 845 } 845 - #else 846 - static inline int emit_lse_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 847 - { 848 - return -EINVAL; 849 - } 850 - #endif 851 846 852 847 static int emit_ll_sc_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 853 848 {
+3
arch/arm64/tools/cpucaps
··· 46 46 HAS_LDAPR 47 47 HAS_LPA2 48 48 HAS_LSE_ATOMICS 49 + HAS_LS64 50 + HAS_LS64_V 49 51 HAS_MOPS 50 52 HAS_NESTED_VIRT 51 53 HAS_BBML2_NOABORT ··· 105 103 WORKAROUND_2457168 106 104 WORKAROUND_2645198 107 105 WORKAROUND_2658417 106 + WORKAROUND_4311569 108 107 WORKAROUND_AMPERE_AC03_CPU_38 109 108 WORKAROUND_AMPERE_AC04_CPU_23 110 109 WORKAROUND_TRBE_OVERWRITE_FILL_MODE
-1
arch/xtensa/include/asm/syscall.h
··· 61 61 regs->areg[2] = (long) error ? error : val; 62 62 } 63 63 64 - #define SYSCALL_MAX_ARGS 6 65 64 #define XTENSA_SYSCALL_ARGUMENT_REGS {6, 3, 4, 5, 8, 9} 66 65 67 66 static inline void syscall_get_arguments(struct task_struct *task,
+92 -9
drivers/acpi/arm64/agdi.c
··· 16 16 #include "init.h" 17 17 18 18 struct agdi_data { 19 + unsigned char flags; /* AGDI Signaling Mode */ 19 20 int sdei_event; 21 + unsigned int gsiv; 22 + bool use_nmi; 23 + int irq; 20 24 }; 21 25 22 26 static int agdi_sdei_handler(u32 sdei_event, struct pt_regs *regs, void *arg) ··· 52 48 return 0; 53 49 } 54 50 51 + static irqreturn_t agdi_interrupt_handler_nmi(int irq, void *dev_id) 52 + { 53 + nmi_panic(NULL, "Arm Generic Diagnostic Dump and Reset NMI Interrupt event issued\n"); 54 + return IRQ_HANDLED; 55 + } 56 + 57 + static irqreturn_t agdi_interrupt_handler_irq(int irq, void *dev_id) 58 + { 59 + panic("Arm Generic Diagnostic Dump and Reset Interrupt event issued\n"); 60 + return IRQ_HANDLED; 61 + } 62 + 63 + static int agdi_interrupt_probe(struct platform_device *pdev, 64 + struct agdi_data *adata) 65 + { 66 + unsigned long irq_flags; 67 + int ret; 68 + int irq; 69 + 70 + irq = acpi_register_gsi(NULL, adata->gsiv, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_HIGH); 71 + if (irq < 0) { 72 + dev_err(&pdev->dev, "cannot register GSI#%d (%d)\n", adata->gsiv, irq); 73 + return irq; 74 + } 75 + 76 + irq_flags = IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_AUTOEN | 77 + IRQF_NO_THREAD; 78 + /* try NMI first */ 79 + ret = request_nmi(irq, &agdi_interrupt_handler_nmi, irq_flags, 80 + "agdi_interrupt_nmi", NULL); 81 + if (!ret) { 82 + enable_nmi(irq); 83 + adata->irq = irq; 84 + adata->use_nmi = true; 85 + return 0; 86 + } 87 + 88 + /* Then try normal interrupt */ 89 + ret = request_irq(irq, &agdi_interrupt_handler_irq, 90 + irq_flags, "agdi_interrupt_irq", NULL); 91 + if (ret) { 92 + dev_err(&pdev->dev, "cannot register IRQ %d\n", ret); 93 + acpi_unregister_gsi(adata->gsiv); 94 + return ret; 95 + } 96 + enable_irq(irq); 97 + adata->irq = irq; 98 + 99 + return 0; 100 + } 101 + 55 102 static int agdi_probe(struct platform_device *pdev) 56 103 { 57 104 struct agdi_data *adata = dev_get_platdata(&pdev->dev); ··· 110 55 if (!adata) 111 56 return -EINVAL; 112 57 113 - return agdi_sdei_probe(pdev, adata); 58 + if (adata->flags & ACPI_AGDI_SIGNALING_MODE) 59 + return agdi_interrupt_probe(pdev, adata); 60 + else 61 + return agdi_sdei_probe(pdev, adata); 114 62 } 115 63 116 - static void agdi_remove(struct platform_device *pdev) 64 + static void agdi_sdei_remove(struct platform_device *pdev, 65 + struct agdi_data *adata) 117 66 { 118 - struct agdi_data *adata = dev_get_platdata(&pdev->dev); 119 67 int err, i; 120 68 121 69 err = sdei_event_disable(adata->sdei_event); ··· 141 83 adata->sdei_event, ERR_PTR(err)); 142 84 } 143 85 86 + static void agdi_interrupt_remove(struct platform_device *pdev, 87 + struct agdi_data *adata) 88 + { 89 + if (adata->irq == -1) 90 + return; 91 + 92 + if (adata->use_nmi) 93 + free_nmi(adata->irq, NULL); 94 + else 95 + free_irq(adata->irq, NULL); 96 + 97 + acpi_unregister_gsi(adata->gsiv); 98 + } 99 + 100 + static void agdi_remove(struct platform_device *pdev) 101 + { 102 + struct agdi_data *adata = dev_get_platdata(&pdev->dev); 103 + 104 + if (adata->flags & ACPI_AGDI_SIGNALING_MODE) 105 + agdi_interrupt_remove(pdev, adata); 106 + else 107 + agdi_sdei_remove(pdev, adata); 108 + } 109 + 144 110 static struct platform_driver agdi_driver = { 145 111 .driver = { 146 112 .name = "agdi", ··· 176 94 void __init acpi_agdi_init(void) 177 95 { 178 96 struct acpi_table_agdi *agdi_table; 179 - struct agdi_data pdata; 97 + struct agdi_data pdata = { 0 }; 180 98 struct platform_device *pdev; 181 99 acpi_status status; 182 100 ··· 185 103 if (ACPI_FAILURE(status)) 186 104 return; 187 105 188 - if (agdi_table->flags & ACPI_AGDI_SIGNALING_MODE) { 189 - pr_warn("Interrupt signaling is not supported"); 190 - goto err_put_table; 191 - } 106 + if (agdi_table->flags & ACPI_AGDI_SIGNALING_MODE) 107 + pdata.gsiv = agdi_table->gsiv; 108 + else 109 + pdata.sdei_event = agdi_table->sdei_event; 192 110 193 - pdata.sdei_event = agdi_table->sdei_event; 111 + pdata.irq = -1; 112 + pdata.flags = agdi_table->flags; 194 113 195 114 pdev = platform_device_register_data(NULL, "agdi", 0, &pdata, sizeof(pdata)); 196 115 if (IS_ERR(pdev))
+8 -1
drivers/base/arch_topology.c
··· 34 34 35 35 static bool supports_scale_freq_counters(const struct cpumask *cpus) 36 36 { 37 - return cpumask_subset(cpus, &scale_freq_counters_mask); 37 + int i; 38 + 39 + for_each_cpu(i, cpus) { 40 + if (cpumask_test_cpu(i, &scale_freq_counters_mask)) 41 + return true; 42 + } 43 + 44 + return false; 38 45 } 39 46 40 47 bool topology_scale_freq_invariant(void)
+6
drivers/cpufreq/cpufreq.c
··· 198 198 } 199 199 EXPORT_SYMBOL_GPL(cpufreq_cpu_get_raw); 200 200 201 + struct cpufreq_policy *cpufreq_cpu_policy(unsigned int cpu) 202 + { 203 + return per_cpu(cpufreq_cpu_data, cpu); 204 + } 205 + EXPORT_SYMBOL_GPL(cpufreq_cpu_policy); 206 + 201 207 unsigned int cpufreq_generic_get(unsigned int cpu) 202 208 { 203 209 struct cpufreq_policy *policy = cpufreq_cpu_get_raw(cpu);
+18 -1
drivers/perf/arm-cmn.c
··· 210 210 enum cmn_part { 211 211 PART_CMN600 = 0x434, 212 212 PART_CMN650 = 0x436, 213 + PART_CMN600AE = 0x438, 213 214 PART_CMN700 = 0x43c, 214 215 PART_CI700 = 0x43a, 215 216 PART_CMN_S3 = 0x43e, ··· 2267 2266 reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01); 2268 2267 part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg); 2269 2268 part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8; 2269 + /* 600AE is close enough that it's not really worth more complexity */ 2270 + if (part == PART_CMN600AE) 2271 + part = PART_CMN600; 2270 2272 if (cmn->part && cmn->part != part) 2271 2273 dev_warn(cmn->dev, 2272 2274 "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n", ··· 2422 2418 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn); 2423 2419 dn->portid_bits = xp->portid_bits; 2424 2420 dn->deviceid_bits = xp->deviceid_bits; 2421 + /* 2422 + * Logical IDs are assigned from 0 per node type, so as 2423 + * soon as we see one bigger than expected, we can assume 2424 + * there are more than we can cope with. 2425 + */ 2426 + if (dn->logid > CMN_MAX_NODES_PER_EVENT) { 2427 + dev_err(cmn->dev, "Node ID invalid for supported CMN versions: %d\n", dn->logid); 2428 + return -ENODEV; 2429 + } 2425 2430 2426 2431 switch (dn->type) { 2427 2432 case CMN_TYPE_DTC: ··· 2480 2467 break; 2481 2468 /* Something has gone horribly wrong */ 2482 2469 default: 2483 - dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type); 2470 + dev_err(cmn->dev, "Device node type invalid for supported CMN versions: 0x%x\n", dn->type); 2484 2471 return -ENODEV; 2485 2472 } 2486 2473 } ··· 2508 2495 cmn->mesh_x = cmn->num_xps; 2509 2496 cmn->mesh_y = cmn->num_xps / cmn->mesh_x; 2510 2497 2498 + if (max(cmn->mesh_x, cmn->mesh_y) > CMN_MAX_DIMENSION) { 2499 + dev_err(cmn->dev, "Mesh size invalid for supported CMN versions: %dx%d\n", cmn->mesh_x, cmn->mesh_y); 2500 + return -ENODEV; 2501 + } 2511 2502 /* 1x1 config plays havoc with XP event encodings */ 2512 2503 if (cmn->num_xps == 1) 2513 2504 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n");
+23 -14
drivers/perf/arm_dsu_pmu.c
··· 66 66 */ 67 67 #define DSU_PMU_IDX_CYCLE_COUNTER 31 68 68 69 - /* All event counters are 32bit, with a 64bit Cycle counter */ 70 - #define DSU_PMU_COUNTER_WIDTH(idx) \ 71 - (((idx) == DSU_PMU_IDX_CYCLE_COUNTER) ? 64 : 32) 72 - 73 - #define DSU_PMU_COUNTER_MASK(idx) \ 74 - GENMASK_ULL((DSU_PMU_COUNTER_WIDTH((idx)) - 1), 0) 75 - 76 69 #define DSU_EXT_ATTR(_name, _func, _config) \ 77 70 (&((struct dev_ext_attribute[]) { \ 78 71 { \ ··· 100 107 * @num_counters : Number of event counters implemented by the PMU, 101 108 * excluding the cycle counter. 102 109 * @irq : Interrupt line for counter overflow. 110 + * @has_32b_pmevcntr : Are the non-cycle counters only 32-bit? 111 + * @has_pmccntr : Do we even have a dedicated cycle counter? 103 112 * @cpmceid_bitmap : Bitmap for the availability of architected common 104 113 * events (event_code < 0x40). 105 114 */ ··· 115 120 struct hlist_node cpuhp_node; 116 121 s8 num_counters; 117 122 int irq; 123 + bool has_32b_pmevcntr; 124 + bool has_pmccntr; 118 125 DECLARE_BITMAP(cpmceid_bitmap, DSU_PMU_MAX_COMMON_EVENTS); 119 126 }; 120 127 ··· 283 286 struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); 284 287 unsigned long *used_mask = hw_events->used_mask; 285 288 286 - if (evtype == DSU_PMU_EVT_CYCLES) { 287 - if (test_and_set_bit(DSU_PMU_IDX_CYCLE_COUNTER, used_mask)) 288 - return -EAGAIN; 289 - return DSU_PMU_IDX_CYCLE_COUNTER; 289 + if (evtype == DSU_PMU_EVT_CYCLES && dsu_pmu->has_pmccntr) { 290 + if (!test_and_set_bit(DSU_PMU_IDX_CYCLE_COUNTER, used_mask)) 291 + return DSU_PMU_IDX_CYCLE_COUNTER; 290 292 } 291 293 292 294 idx = find_first_zero_bit(used_mask, dsu_pmu->num_counters); ··· 324 328 raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags); 325 329 } 326 330 331 + static u64 dsu_pmu_counter_mask(struct hw_perf_event *hw) 332 + { 333 + return (hw->flags && hw->idx != DSU_PMU_IDX_CYCLE_COUNTER) ? U32_MAX : U64_MAX; 334 + } 335 + 327 336 static void dsu_pmu_event_update(struct perf_event *event) 328 337 { 329 338 struct hw_perf_event *hwc = &event->hw; ··· 340 339 new_count = dsu_pmu_read_counter(event); 341 340 } while (local64_cmpxchg(&hwc->prev_count, prev_count, new_count) != 342 341 prev_count); 343 - delta = (new_count - prev_count) & DSU_PMU_COUNTER_MASK(hwc->idx); 342 + delta = (new_count - prev_count) & dsu_pmu_counter_mask(hwc); 344 343 local64_add(delta, &event->count); 345 344 } 346 345 ··· 363 362 */ 364 363 static void dsu_pmu_set_event_period(struct perf_event *event) 365 364 { 366 - int idx = event->hw.idx; 367 - u64 val = DSU_PMU_COUNTER_MASK(idx) >> 1; 365 + u64 val = dsu_pmu_counter_mask(&event->hw) >> 1; 368 366 369 367 local64_set(&event->hw.prev_count, val); 370 368 dsu_pmu_write_counter(event, val); ··· 564 564 return -EINVAL; 565 565 566 566 event->hw.config_base = event->attr.config; 567 + event->hw.flags = dsu_pmu->has_32b_pmevcntr; 567 568 return 0; 568 569 } 569 570 ··· 665 664 cpmceid[1] = __dsu_pmu_read_pmceid(1); 666 665 bitmap_from_arr32(dsu_pmu->cpmceid_bitmap, cpmceid, 667 666 DSU_PMU_MAX_COMMON_EVENTS); 667 + /* Newer DSUs have 64-bit counters */ 668 + __dsu_pmu_write_counter(0, U64_MAX); 669 + if (__dsu_pmu_read_counter(0) != U64_MAX) 670 + dsu_pmu->has_32b_pmevcntr = true; 671 + /* On even newer DSUs, PMCCNTR is RAZ/WI */ 672 + __dsu_pmu_write_pmccntr(U64_MAX); 673 + if (__dsu_pmu_read_pmccntr() == U64_MAX) 674 + dsu_pmu->has_pmccntr = true; 668 675 } 669 676 670 677 static void dsu_pmu_set_active_cpu(int cpu, struct dsu_pmu *dsu_pmu)
+12 -6
drivers/perf/arm_spe_pmu.c
··· 106 106 /* Keep track of our dynamic hotplug state */ 107 107 static enum cpuhp_state arm_spe_pmu_online; 108 108 109 + static void arm_spe_pmu_stop(struct perf_event *event, int flags); 110 + 109 111 enum arm_spe_pmu_buf_fault_action { 110 112 SPE_PMU_BUF_FAULT_ACT_SPURIOUS, 111 113 SPE_PMU_BUF_FAULT_ACT_FATAL, ··· 609 607 return limit; 610 608 } 611 609 612 - static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, 613 - struct perf_event *event) 610 + static int arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, 611 + struct perf_event *event) 614 612 { 615 613 u64 base, limit; 616 614 struct arm_spe_pmu_buf *buf; ··· 624 622 /* Start a new aux session */ 625 623 buf = perf_aux_output_begin(handle, event); 626 624 if (!buf) { 627 - event->hw.state |= PERF_HES_STOPPED; 628 625 /* 629 626 * We still need to clear the limit pointer, since the 630 627 * profiler might only be disabled by virtue of a fault. ··· 643 642 644 643 out_write_limit: 645 644 write_sysreg_s(limit, SYS_PMBLIMITR_EL1); 645 + return (limit & PMBLIMITR_EL1_E) ? 0 : -EIO; 646 646 } 647 647 648 648 static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle) ··· 783 781 * when we get to it. 784 782 */ 785 783 if (!(handle->aux_flags & PERF_AUX_FLAG_TRUNCATED)) { 786 - arm_spe_perf_aux_output_begin(handle, event); 784 + if (arm_spe_perf_aux_output_begin(handle, event)) { 785 + arm_spe_pmu_stop(event, PERF_EF_UPDATE); 786 + break; 787 + } 787 788 isb(); 788 789 } 789 790 break; ··· 885 880 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle); 886 881 887 882 hwc->state = 0; 888 - arm_spe_perf_aux_output_begin(handle, event); 889 - if (hwc->state) 883 + if (arm_spe_perf_aux_output_begin(handle, event)) { 884 + arm_spe_pmu_stop(event, 0); 890 885 return; 886 + } 891 887 892 888 reg = arm_spe_event_to_pmsfcr(event); 893 889 write_sysreg_s(reg, SYS_PMSFCR_EL1);
+1 -1
drivers/perf/cxl_pmu.c
··· 877 877 if (!irq_name) 878 878 return -ENOMEM; 879 879 880 - rc = devm_request_irq(dev, irq, cxl_pmu_irq, IRQF_SHARED | IRQF_ONESHOT, 880 + rc = devm_request_irq(dev, irq, cxl_pmu_irq, IRQF_SHARED | IRQF_NO_THREAD, 881 881 irq_name, info); 882 882 if (rc) 883 883 return rc;
+1 -1
drivers/perf/riscv_pmu_sbi.c
··· 1244 1244 { 1245 1245 struct riscv_pmu *rvpmu = container_of(b, struct riscv_pmu, riscv_pm_nb); 1246 1246 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); 1247 - int enabled = bitmap_weight(cpuc->used_hw_ctrs, RISCV_MAX_COUNTERS); 1247 + bool enabled = !bitmap_empty(cpuc->used_hw_ctrs, RISCV_MAX_COUNTERS); 1248 1248 struct perf_event *event; 1249 1249 int idx; 1250 1250
+5
include/linux/cpufreq.h
··· 203 203 204 204 #ifdef CONFIG_CPU_FREQ 205 205 struct cpufreq_policy *cpufreq_cpu_get_raw(unsigned int cpu); 206 + struct cpufreq_policy *cpufreq_cpu_policy(unsigned int cpu); 206 207 struct cpufreq_policy *cpufreq_cpu_get(unsigned int cpu); 207 208 void cpufreq_cpu_put(struct cpufreq_policy *policy); 208 209 #else 209 210 static inline struct cpufreq_policy *cpufreq_cpu_get_raw(unsigned int cpu) 211 + { 212 + return NULL; 213 + } 214 + static inline struct cpufreq_policy *cpufreq_cpu_policy(unsigned int cpu) 210 215 { 211 216 return NULL; 212 217 }
+2 -1
include/uapi/linux/kvm.h
··· 180 180 #define KVM_EXIT_MEMORY_FAULT 39 181 181 #define KVM_EXIT_TDX 40 182 182 #define KVM_EXIT_ARM_SEA 41 183 + #define KVM_EXIT_ARM_LDST64B 42 183 184 184 185 /* For KVM_EXIT_INTERNAL_ERROR */ 185 186 /* Emulate instruction failed. */ ··· 403 402 } eoi; 404 403 /* KVM_EXIT_HYPERV */ 405 404 struct kvm_hyperv_exit hyperv; 406 - /* KVM_EXIT_ARM_NISV */ 405 + /* KVM_EXIT_ARM_NISV / KVM_EXIT_ARM_LDST64B */ 407 406 struct { 408 407 __u64 esr_iss; 409 408 __u64 fault_ipa;
+4 -2
tools/testing/selftests/arm64/Makefile
··· 30 30 @for DIR in $(ARM64_SUBTARGETS); do \ 31 31 BUILD_TARGET=$(OUTPUT)/$$DIR; \ 32 32 mkdir -p $$BUILD_TARGET; \ 33 - make OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ 33 + make OUTPUT=$$BUILD_TARGET -C $$DIR $@ \ 34 + $(if $(FORCE_TARGETS),|| exit); \ 34 35 done 35 36 36 37 install: all 37 38 @for DIR in $(ARM64_SUBTARGETS); do \ 38 39 BUILD_TARGET=$(OUTPUT)/$$DIR; \ 39 - make OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ 40 + make OUTPUT=$$BUILD_TARGET -C $$DIR $@ \ 41 + $(if $(FORCE_TARGETS),|| exit); \ 40 42 done 41 43 42 44 run_tests: all
+49
tools/testing/selftests/arm64/abi/hwcap.c
··· 11 11 #include <stdlib.h> 12 12 #include <string.h> 13 13 #include <unistd.h> 14 + #include <linux/auxvec.h> 15 + #include <linux/compiler.h> 14 16 #include <sys/auxv.h> 15 17 #include <sys/prctl.h> 16 18 #include <asm/hwcap.h> ··· 597 595 : "=r" (data0), "=r" (data1) : "r" (src) :); 598 596 } 599 597 598 + static void ignore_signal(int sig, siginfo_t *info, void *context) 599 + { 600 + ucontext_t *uc = context; 601 + 602 + uc->uc_mcontext.pc += 4; 603 + } 604 + 605 + static void ls64_sigill(void) 606 + { 607 + struct sigaction ign, old; 608 + char src[64] __aligned(64) = { 1 }; 609 + 610 + /* 611 + * LS64 requires target memory to be Device/Non-cacheable (if 612 + * FEAT_LS64WB not supported) and the completer supports these 613 + * instructions, otherwise we'll receive a SIGBUS. Since we are only 614 + * testing the ABI here, so just ignore the SIGBUS and see if we can 615 + * execute the instructions without receiving a SIGILL. Restore the 616 + * handler of SIGBUS after this test. 617 + */ 618 + ign.sa_sigaction = ignore_signal; 619 + ign.sa_flags = SA_SIGINFO | SA_RESTART; 620 + sigemptyset(&ign.sa_mask); 621 + sigaction(SIGBUS, &ign, &old); 622 + 623 + register void *xn asm ("x8") = src; 624 + register u64 xt_1 asm ("x0"); 625 + 626 + /* LD64B x0, [x8] */ 627 + asm volatile(".inst 0xf83fd100" : "=r" (xt_1) : "r" (xn) 628 + : "x1", "x2", "x3", "x4", "x5", "x6", "x7"); 629 + 630 + /* ST64B x0, [x8] */ 631 + asm volatile(".inst 0xf83f9100" : : "r" (xt_1), "r" (xn) 632 + : "x1", "x2", "x3", "x4", "x5", "x6", "x7"); 633 + 634 + sigaction(SIGBUS, &old, NULL); 635 + } 636 + 600 637 static const struct hwcap_data { 601 638 const char *name; 602 639 unsigned long at_hwcap; ··· 1174 1133 .at_hwcap = AT_HWCAP3, 1175 1134 .hwcap_bit = HWCAP3_MTE_STORE_ONLY, 1176 1135 .cpuinfo = "mtestoreonly", 1136 + }, 1137 + { 1138 + .name = "LS64", 1139 + .at_hwcap = AT_HWCAP3, 1140 + .hwcap_bit = HWCAP3_LS64, 1141 + .cpuinfo = "ls64", 1142 + .sigill_fn = ls64_sigill, 1143 + .sigill_reliable = true, 1177 1144 }, 1178 1145 }; 1179 1146
+1 -2
tools/testing/selftests/arm64/abi/tpidr2.c
··· 128 128 int *parent_tidptr, unsigned long tls, 129 129 int *child_tidptr) 130 130 { 131 - return my_syscall5(__NR_clone, clone_flags, newsp, parent_tidptr, tls, 132 - child_tidptr); 131 + return syscall(__NR_clone, clone_flags, newsp, parent_tidptr, tls, child_tidptr); 133 132 } 134 133 135 134 #define __STACK_SIZE (8 * 1024 * 1024)
+5 -1
tools/testing/selftests/arm64/fp/fp-pidbench.S
··· 33 33 function _start 34 34 puts "Iterations per test: " 35 35 mov x20, #10000 36 - lsl x20, x20, #8 36 + lsl x20, x20, #12 37 37 mov x0, x20 38 38 bl putdec 39 39 puts "\n" ··· 62 62 // Use SVE per syscall 63 63 puts "SVE used per syscall: " 64 64 test_loop "rdvl x0, #8" 65 + 66 + // Test non-SVE execution after SVE 67 + puts "No SVE after SVE: " 68 + test_loop 65 69 66 70 // And we're done 67 71 out:
+16 -24
tools/testing/selftests/arm64/gcs/basic-gcs.c
··· 22 22 static __attribute__((noinline)) void valid_gcs_function(void) 23 23 { 24 24 /* Do something the compiler can't optimise out */ 25 - my_syscall1(__NR_prctl, PR_SVE_GET_VL); 25 + syscall(__NR_prctl, PR_SVE_GET_VL); 26 26 } 27 27 28 28 static inline int gcs_set_status(unsigned long mode) ··· 36 36 * other 3 values passed in registers to the syscall are zero 37 37 * since the kernel validates them. 38 38 */ 39 - ret = my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, mode, 40 - 0, 0, 0); 39 + ret = syscall(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, mode, 0, 0, 0); 41 40 42 41 if (ret == 0) { 43 - ret = my_syscall5(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, 44 - &new_mode, 0, 0, 0); 42 + ret = syscall(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &new_mode, 0, 0, 0); 45 43 if (ret == 0) { 46 44 if (new_mode != mode) { 47 45 ksft_print_msg("Mode set to %lx not %lx\n", ··· 47 49 ret = -EINVAL; 48 50 } 49 51 } else { 50 - ksft_print_msg("Failed to validate mode: %d\n", ret); 52 + ksft_print_msg("Failed to validate mode: %d\n", errno); 51 53 } 52 54 53 55 if (enabling != chkfeat_gcs()) { ··· 67 69 unsigned long state; 68 70 int ret; 69 71 70 - ret = my_syscall5(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, 71 - &state, 0, 0, 0); 72 + ret = syscall(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &state, 0, 0, 0); 72 73 if (ret != 0) { 73 - ksft_print_msg("Failed to read state: %d\n", ret); 74 + ksft_print_msg("Failed to read state: %d\n", errno); 74 75 return false; 75 76 } 76 77 ··· 185 188 int elem; 186 189 bool pass = true; 187 190 188 - buf = (void *)my_syscall3(__NR_map_shadow_stack, 0, page_size, 189 - SHADOW_STACK_SET_MARKER | 190 - SHADOW_STACK_SET_TOKEN); 191 + buf = (void *)syscall(__NR_map_shadow_stack, 0, page_size, 192 + SHADOW_STACK_SET_MARKER | SHADOW_STACK_SET_TOKEN); 191 193 if (buf == MAP_FAILED) { 192 194 ksft_print_msg("Failed to map %lu byte GCS: %d\n", 193 195 page_size, errno); ··· 253 257 valid_gcs_function(); 254 258 get_gcspr(); 255 259 256 - ret = my_syscall5(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, 257 - &child_mode, 0, 0, 0); 260 + ret = syscall(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &child_mode, 0, 0, 0); 258 261 if (ret == 0 && !(child_mode & PR_SHADOW_STACK_ENABLE)) { 259 262 ksft_print_msg("GCS not enabled in child\n"); 260 263 ret = -EINVAL; ··· 316 321 valid_gcs_function(); 317 322 get_gcspr(); 318 323 319 - ret = my_syscall5(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, 320 - &child_mode, 0, 0, 0); 324 + ret = syscall(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &child_mode, 0, 0, 0); 321 325 if (ret == 0 && !(child_mode & PR_SHADOW_STACK_ENABLE)) { 322 326 ksft_print_msg("GCS not enabled in child\n"); 323 327 ret = EXIT_FAILURE; ··· 384 390 if (!(getauxval(AT_HWCAP) & HWCAP_GCS)) 385 391 ksft_exit_skip("SKIP GCS not supported\n"); 386 392 387 - ret = my_syscall5(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, 388 - &gcs_mode, 0, 0, 0); 393 + ret = syscall(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &gcs_mode, 0, 0, 0); 389 394 if (ret != 0) 390 - ksft_exit_fail_msg("Failed to read GCS state: %d\n", ret); 395 + ksft_exit_fail_msg("Failed to read GCS state: %d\n", errno); 391 396 392 397 if (!(gcs_mode & PR_SHADOW_STACK_ENABLE)) { 393 398 gcs_mode = PR_SHADOW_STACK_ENABLE; 394 - ret = my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, 395 - gcs_mode, 0, 0, 0); 399 + ret = syscall(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, gcs_mode, 0, 0, 0); 396 400 if (ret != 0) 397 - ksft_exit_fail_msg("Failed to enable GCS: %d\n", ret); 401 + ksft_exit_fail_msg("Failed to enable GCS: %d\n", errno); 398 402 } 399 403 400 404 ksft_set_plan(ARRAY_SIZE(tests)); ··· 402 410 } 403 411 404 412 /* One last test: disable GCS, we can do this one time */ 405 - ret = my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, 0, 0, 0, 0); 413 + ret = syscall(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, 0, 0, 0, 0); 406 414 if (ret != 0) 407 - ksft_print_msg("Failed to disable GCS: %d\n", ret); 415 + ksft_print_msg("Failed to disable GCS: %d\n", errno); 408 416 409 417 ksft_finished(); 410 418
+1
tools/testing/selftests/arm64/mte/.gitignore
··· 6 6 check_prctl 7 7 check_ksm_options 8 8 check_user_mem 9 + check_hugetlb_options