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dt-bindings: ufs: qcom,ufs: convert to dtschema
Convert the Qualcomm Universal Flash Storage (UFS) Controller to DT
schema format.
Except the conversion, add also properties already present in DTS:
iommus, interconnects and power-domains.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220306111125.116455-6-krzysztof.kozlowski@canonical.com
authored by
Krzysztof Kozlowski
and committed by
Rob Herring
462c5c0a
578f116b
+242
-90
+242
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+242
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
···
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Universal Flash Storage (UFS) Controller
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Andy Gross <agross@kernel.org>
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# Select only our matches, not all jedec,ufs-2.0
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select:
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properties:
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compatible:
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contains:
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const: qcom,ufshc
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required:
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- compatible
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+
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properties:
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compatible:
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items:
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- enum:
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- qcom,msm8994-ufshc
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- qcom,msm8996-ufshc
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- qcom,msm8998-ufshc
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- qcom,sdm845-ufshc
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- qcom,sm8150-ufshc
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- qcom,sm8250-ufshc
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- qcom,sm8350-ufshc
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- qcom,sm8450-ufshc
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- const: qcom,ufshc
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- const: jedec,ufs-2.0
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+
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clocks:
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minItems: 8
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maxItems: 11
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+
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clock-names:
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minItems: 8
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maxItems: 11
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+
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interconnects:
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minItems: 2
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maxItems: 2
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+
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interconnect-names:
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items:
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- const: ufs-ddr
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- const: cpu-ufs
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+
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iommus:
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minItems: 1
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maxItems: 2
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+
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phys:
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maxItems: 1
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+
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phy-names:
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items:
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- const: ufsphy
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+
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power-domains:
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maxItems: 1
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+
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reg:
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minItems: 1
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maxItems: 2
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+
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resets:
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maxItems: 1
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+
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'#reset-cells':
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const: 1
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+
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reset-names:
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items:
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- const: rst
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+
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reset-gpios:
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maxItems: 1
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description:
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GPIO connected to the RESET pin of the UFS memory device.
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required:
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- compatible
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- reg
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+
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allOf:
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- $ref: ufs-common.yaml
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8998-ufshc
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- qcom,sm8250-ufshc
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- qcom,sm8350-ufshc
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- qcom,sm8450-ufshc
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then:
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properties:
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clocks:
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minItems: 8
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maxItems: 8
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clock-names:
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items:
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- const: core_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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- const: rx_lane1_sync_clk
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reg:
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minItems: 1
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maxItems: 1
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+
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdm845-ufshc
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- qcom,sm8150-ufshc
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then:
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properties:
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clocks:
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minItems: 9
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+
maxItems: 9
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clock-names:
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items:
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- const: core_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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- const: rx_lane1_sync_clk
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- const: ice_core_clk
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reg:
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minItems: 2
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maxItems: 2
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+
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8996-ufshc
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then:
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properties:
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clocks:
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minItems: 11
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+
maxItems: 11
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clock-names:
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items:
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- const: core_clk_src
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- const: core_clk
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- const: bus_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro_src
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- const: core_clk_unipro
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- const: core_clk_ice
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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reg:
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minItems: 1
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maxItems: 1
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# TODO: define clock bindings for qcom,msm8994-ufshc
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,sm8450.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ufs@1d84000 {
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compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
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"jedec,ufs-2.0";
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reg = <0 0x01d84000 0 0x3000>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs_mem_phy_lanes>;
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phy-names = "ufsphy";
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lanes-per-direction = <2>;
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#reset-cells = <1>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
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vcc-supply = <&vreg_l7b_2p5>;
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vcc-max-microamp = <1100000>;
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vccq-supply = <&vreg_l9b_1p2>;
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vccq-max-microamp = <1200000>;
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power-domains = <&gcc UFS_PHY_GDSC>;
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iommus = <&apps_smmu 0xe0 0x0>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
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interconnect-names = "ufs-ddr", "cpu-ufs";
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clock-names = "core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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freq-table-hz = <75000000 300000000>,
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<0 0>,
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<0 0>,
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<75000000 300000000>,
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<75000000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>;
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};
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};
-90
Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
-90
Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
···
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* Universal Flash Storage (UFS) Host Controller
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UFSHC nodes are defined to describe on-chip UFS host controllers.
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Each UFS controller instance should have its own node.
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Required properties:
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- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
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For Qualcomm SoCs must contain, as below, an
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SoC-specific compatible along with "qcom,ufshc" and
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the appropriate jedec string:
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"qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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"qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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"qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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"qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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"qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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"qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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"qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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"qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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- interrupts : <interrupt mapping for UFS host controller IRQ>
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- reg : <registers mapping>
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Optional properties:
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- phys : phandle to UFS PHY node
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- phy-names : the string "ufsphy" when is found in a node, along
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with "phys" attribute, provides phandle to UFS PHY node
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- vdd-hba-supply : phandle to UFS host controller supply regulator node
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- vcc-supply : phandle to VCC supply regulator node
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- vccq-supply : phandle to VCCQ supply regulator node
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- vccq2-supply : phandle to VCCQ2 supply regulator node
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- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
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or 2.7-3.6V. This boolean property when set, specifies
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to use low voltage range of 1.7-1.95V. Note for external
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UFS cards this property is invalid and valid VCC range is
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always 2.7-3.6V.
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- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
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- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
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- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
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- clocks : List of phandle and clock specifier pairs
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- clock-names : List of clock input name strings sorted in the same
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order as the clocks property.
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"ref_clk" indicates reference clock frequency.
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UFS host supplies reference clock to UFS device and UFS device
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specification allows host to provide one of the 4 frequencies (19.2 MHz,
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26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
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parsed and used to update the reference clock setting in device.
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Defaults to 26 MHz(as per specification) if not specified by host.
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- freq-table-hz : Array of <min max> operating frequencies stored in the same
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order as the clocks property. If this property is not
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defined or a value in the array is "0" then it is assumed
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that the frequency is set by the parent clock or a
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fixed rate clock source.
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-lanes-per-direction : number of lanes available per direction - either 1 or 2.
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Note that it is assume same number of lanes is used both
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directions at once. If not specified, default is 2 lanes per direction.
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- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose
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PHY reset from the UFS controller.
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- resets : reset node register
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- reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
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- reset-gpios : A phandle and gpio specifier denoting the GPIO connected
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to the RESET pin of the UFS memory device.
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Note: If above properties are not defined it can be assumed that the supply
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regulators or clocks are always on.
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Example:
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ufshc@fc598000 {
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compatible = "jedec,ufs-1.1";
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reg = <0xfc598000 0x800>;
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interrupts = <0 28 0>;
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vdd-hba-supply = <&xxx_reg0>;
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vcc-supply = <&xxx_reg1>;
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vcc-supply-1p8;
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vccq-supply = <&xxx_reg2>;
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vccq2-supply = <&xxx_reg3>;
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vcc-max-microamp = 500000;
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vccq-max-microamp = 200000;
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vccq2-max-microamp = 200000;
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clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
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clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
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freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
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resets = <&reset 0 1>;
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reset-names = "rst";
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phys = <&ufsphy1>;
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phy-names = "ufsphy";
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#reset-cells = <1>;
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};