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dt-bindings: ufs: drop unused/old ufs-qcom PHY bindings

The Qualcomm UFS PHY bindings are documented in
bindings/phy/qcom,qmp-phy.yaml and the compatibles from separate file
bindings/ufs/ufs-qcom.txt are not used at all.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220306111125.116455-5-krzysztof.kozlowski@canonical.com

authored by

Krzysztof Kozlowski and committed by
Rob Herring 578f116b 1581355b

-63
-63
Documentation/devicetree/bindings/ufs/ufs-qcom.txt
··· 1 - * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY 2 - 3 - UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro. 4 - Each UFS PHY node should have its own node. 5 - 6 - To bind UFS PHY with UFS host controller, the controller node should 7 - contain a phandle reference to UFS PHY node. 8 - 9 - Required properties: 10 - - compatible : compatible list, contains one of the following - 11 - "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy, 12 - "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy, 13 - "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy 14 - present on MSM8996 chipset. 15 - - reg : should contain PHY register address space (mandatory), 16 - - reg-names : indicates various resources passed to driver (via reg proptery) by name. 17 - Required "reg-names" is "phy_mem". 18 - - #phy-cells : This property shall be set to 0 19 - - vdda-phy-supply : phandle to main PHY supply for analog domain 20 - - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply 21 - - clocks : List of phandle and clock specifier pairs 22 - - clock-names : List of clock input name strings sorted in the same 23 - order as the clocks property. "ref_clk_src", "ref_clk", 24 - "tx_iface_clk" & "rx_iface_clk" are mandatory but 25 - "ref_clk_parent" is optional 26 - 27 - Optional properties: 28 - - vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply 29 - - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply 30 - - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply 31 - - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply 32 - - resets : specifies the PHY reset in the UFS controller 33 - 34 - Example: 35 - 36 - ufsphy1: ufsphy@fc597000 { 37 - compatible = "qcom,ufs-phy-qmp-20nm"; 38 - reg = <0xfc597000 0x800>; 39 - reg-names = "phy_mem"; 40 - #phy-cells = <0>; 41 - vdda-phy-supply = <&pma8084_l4>; 42 - vdda-pll-supply = <&pma8084_l12>; 43 - vdda-phy-max-microamp = <50000>; 44 - vdda-pll-max-microamp = <1000>; 45 - clock-names = "ref_clk_src", 46 - "ref_clk_parent", 47 - "ref_clk", 48 - "tx_iface_clk", 49 - "rx_iface_clk"; 50 - clocks = <&clock_rpm clk_ln_bb_clk>, 51 - <&clock_gcc clk_pcie_1_phy_ldo >, 52 - <&clock_gcc clk_ufs_phy_ldo>, 53 - <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, 54 - <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; 55 - resets = <&ufshc 0>; 56 - }; 57 - 58 - ufshc: ufshc@fc598000 { 59 - #reset-cells = <1>; 60 - ... 61 - phys = <&ufsphy1>; 62 - phy-names = "ufsphy"; 63 - };