Merge tag 'mfd-next-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

+62

Documentation/devicetree/bindings/leds/backlight/richtek,rt4831-backlight.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Richtek RT4831 Backlight 8 + 9 + maintainers: 10 + - ChiYuan Huang <cy_huang@richtek.com> 11 + 12 + description: | 13 + RT4831 is a mutifunctional device that can provide power to the LCD display 14 + and LCD backlight. 15 + 16 + For the LCD backlight, it can provide four channel WLED driving capability. 17 + Each channel driving current is up to 30mA 18 + 19 + Datasheet is available at 20 + https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf 21 + 22 + allOf: 23 + - $ref: common.yaml# 24 + 25 + properties: 26 + compatible: 27 + const: richtek,rt4831-backlight 28 + 29 + default-brightness: 30 + minimum: 0 31 + maximum: 2048 32 + 33 + max-brightness: 34 + minimum: 0 35 + maximum: 2048 36 + 37 + richtek,pwm-enable: 38 + description: | 39 + Specify the backlight dimming following by PWM duty or by SW control. 40 + type: boolean 41 + 42 + richtek,bled-ovp-sel: 43 + description: | 44 + Backlight OVP level selection, currently support 17V/21V/25V/29V. 45 + $ref: /schemas/types.yaml#/definitions/uint8 46 + default: 1 47 + minimum: 0 48 + maximum: 3 49 + 50 + richtek,channel-use: 51 + description: | 52 + Backlight LED channel to be used. 53 + BIT 0/1/2/3 is used to indicate led channel 1/2/3/4 enable or disable. 54 + $ref: /schemas/types.yaml#/definitions/uint8 55 + minimum: 1 56 + maximum: 15 57 + 58 + required: 59 + - compatible 60 + - richtek,channel-use 61 + 62 + additionalProperties: false

+20

Documentation/devicetree/bindings/mfd/google,cros-ec.yaml

··· 117 117 - "#address-cells" 118 118 - "#size-cells" 119 119 120 + cbas: 121 + type: object 122 + 123 + description: 124 + This device is used to signal when a detachable base is attached 125 + to a Chrome OS tablet. This device cannot be detected at runtime. 126 + 127 + properties: 128 + compatible: 129 + const: google,cros-cbas 130 + 131 + required: 132 + - compatible 133 + 134 + additionalProperties: false 135 + 120 136 patternProperties: 121 137 "^i2c-tunnel[0-9]*$": 122 138 type: object ··· 202 186 203 187 proximity { 204 188 compatible = "google,cros-ec-mkbp-proximity"; 189 + }; 190 + 191 + cbas { 192 + compatible = "google,cros-cbas"; 205 193 }; 206 194 }; 207 195 };

+121

Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/qcom,pm8008.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Technologies, Inc. PM8008 PMIC bindings 8 + 9 + maintainers: 10 + - Guru Das Srinagesh <gurus@codeaurora.org> 11 + 12 + description: | 13 + Qualcomm Technologies, Inc. PM8008 is a dedicated camera PMIC that integrates 14 + all the necessary power management, housekeeping, and interface support 15 + functions into a single IC. 16 + 17 + properties: 18 + compatible: 19 + const: qcom,pm8008 20 + 21 + reg: 22 + description: 23 + I2C slave address. 24 + 25 + maxItems: 1 26 + 27 + interrupts: 28 + maxItems: 1 29 + 30 + description: Parent interrupt. 31 + 32 + "#interrupt-cells": 33 + const: 2 34 + 35 + description: | 36 + The first cell is the IRQ number, the second cell is the IRQ trigger 37 + flag. All interrupts are listed in include/dt-bindings/mfd/qcom-pm8008.h. 38 + 39 + interrupt-controller: true 40 + 41 + "#address-cells": 42 + const: 1 43 + 44 + "#size-cells": 45 + const: 0 46 + 47 + patternProperties: 48 + "^gpio@[0-9a-f]+$": 49 + type: object 50 + 51 + description: | 52 + The GPIO peripheral. This node may be specified twice, one for each GPIO. 53 + 54 + properties: 55 + compatible: 56 + const: qcom,pm8008-gpio 57 + 58 + reg: 59 + description: Peripheral address of one of the two GPIO peripherals. 60 + maxItems: 1 61 + 62 + gpio-controller: true 63 + 64 + interrupt-controller: true 65 + 66 + "#interrupt-cells": 67 + const: 2 68 + 69 + "#gpio-cells": 70 + const: 2 71 + 72 + required: 73 + - compatible 74 + - reg 75 + - gpio-controller 76 + - interrupt-controller 77 + - "#gpio-cells" 78 + - "#interrupt-cells" 79 + 80 + additionalProperties: false 81 + 82 + required: 83 + - compatible 84 + - reg 85 + - interrupts 86 + - "#address-cells" 87 + - "#size-cells" 88 + - "#interrupt-cells" 89 + 90 + additionalProperties: false 91 + 92 + examples: 93 + - | 94 + #include <dt-bindings/mfd/qcom-pm8008.h> 95 + #include <dt-bindings/interrupt-controller/irq.h> 96 + qupv3_se13_i2c { 97 + #address-cells = <1>; 98 + #size-cells = <0>; 99 + pm8008i@8 { 100 + compatible = "qcom,pm8008"; 101 + reg = <0x8>; 102 + #address-cells = <1>; 103 + #size-cells = <0>; 104 + interrupt-controller; 105 + #interrupt-cells = <2>; 106 + 107 + interrupt-parent = <&tlmm>; 108 + interrupts = <32 IRQ_TYPE_EDGE_RISING>; 109 + 110 + gpio@c000 { 111 + compatible = "qcom,pm8008-gpio"; 112 + reg = <0xc000>; 113 + gpio-controller; 114 + #gpio-cells = <2>; 115 + interrupt-controller; 116 + #interrupt-cells = <2>; 117 + }; 118 + }; 119 + }; 120 + 121 + ...

+4

Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt

··· 34 34 "qcom,pm8998", 35 35 "qcom,pmi8998", 36 36 "qcom,pm8005", 37 + "qcom,pm8350c", 38 + "qcom,pmk8350", 39 + "qcom,pm7325", 40 + "qcom,pmr735a", 37 41 or generalized "qcom,spmi-pmic". 38 42 - reg: Specifies the SPMI USID slave address for this device. 39 43 For more information see:

+90

Documentation/devicetree/bindings/mfd/richtek,rt4831.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/richtek,rt4831.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Richtek RT4831 DSV and Backlight Integrated IC 8 + 9 + maintainers: 10 + - ChiYuan Huang <cy_huang@richtek.com> 11 + 12 + description: | 13 + RT4831 is a multifunctional device that can provide power to the LCD display 14 + and LCD backlight. 15 + 16 + For Display Bias Voltage DSVP and DSVN, the output range is about 4V to 6.5V. 17 + It's sufficient to meet the current LCD power requirement. 18 + 19 + For the LCD backlight, it can provide four channel WLED driving capability. 20 + Each channel driving current is up to 30mA 21 + 22 + Datasheet is available at 23 + https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf 24 + 25 + properties: 26 + compatible: 27 + const: richtek,rt4831 28 + 29 + reg: 30 + description: I2C device address. 31 + maxItems: 1 32 + 33 + enable-gpios: 34 + description: | 35 + GPIO to enable/disable the chip. It is optional. 36 + Some usage directly tied this pin to follow VIO 1.8V power on sequence. 37 + maxItems: 1 38 + 39 + regulators: 40 + $ref: ../regulator/richtek,rt4831-regulator.yaml 41 + 42 + backlight: 43 + $ref: ../leds/backlight/richtek,rt4831-backlight.yaml 44 + 45 + required: 46 + - compatible 47 + - reg 48 + 49 + additionalProperties: false 50 + 51 + examples: 52 + - | 53 + #include <dt-bindings/leds/rt4831-backlight.h> 54 + i2c { 55 + #address-cells = <1>; 56 + #size-cells = <0>; 57 + 58 + rt4831@11 { 59 + compatible = "richtek,rt4831"; 60 + reg = <0x11>; 61 + 62 + regulators { 63 + DSVLCM { 64 + regulator-min-microvolt = <4000000>; 65 + regulator-max-microvolt = <7150000>; 66 + regulator-allow-bypass; 67 + }; 68 + DSVP { 69 + regulator-name = "rt4831-dsvp"; 70 + regulator-min-microvolt = <4000000>; 71 + regulator-max-microvolt = <6500000>; 72 + regulator-boot-on; 73 + }; 74 + DSVN { 75 + regulator-name = "rt4831-dsvn"; 76 + regulator-min-microvolt = <4000000>; 77 + regulator-max-microvolt = <6500000>; 78 + regulator-boot-on; 79 + }; 80 + }; 81 + 82 + backlight { 83 + compatible = "richtek,rt4831-backlight"; 84 + default-brightness = <1024>; 85 + max-brightness = <2048>; 86 + richtek,bled-ovp-sel = /bits/ 8 <RT4831_BLOVPLVL_21V>; 87 + richtek,channel-use = /bits/ 8 <RT4831_BLED_ALLCHEN>; 88 + }; 89 + }; 90 + };

-2

Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml

··· 119 119 - compatible 120 120 121 121 required: 122 - - "#address-cells" 123 - - "#size-cells" 124 122 - compatible 125 123 - reg 126 124 - clocks

+278

Documentation/devicetree/bindings/mfd/stericsson,db8500-prcmu.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/stericsson,db8500-prcmu.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ST-Ericsson DB8500 PRCMU - Power Reset and Control Management Unit 8 + 9 + maintainers: 10 + - Linus Walleij <linus.walleij@linaro.org> 11 + 12 + description: 13 + The DB8500 Power Reset and Control Management Unit is an XP70 8-bit 14 + microprocessor that is embedded in the always-on power domain of the 15 + DB8500 SoCs to manage the low power states, powering up and down parts 16 + of the silicon, and controlling reset of different IP blocks. 17 + 18 + properties: 19 + $nodename: 20 + pattern: '^prcmu@[0-9a-f]+$' 21 + 22 + compatible: 23 + description: The device is compatible both to the device-specific 24 + compatible "stericsson,db8500-prcmu" and "syscon". The latter 25 + compatible is needed for the device to be exposed as a system 26 + controller so that arbitrary registers can be access by 27 + different operating system components. 28 + items: 29 + - const: stericsson,db8500-prcmu 30 + - const: syscon 31 + 32 + reg: 33 + items: 34 + - description: Main PRCMU register area 35 + - description: PRCMU TCPM register area 36 + - description: PRCMU TCDM register area 37 + 38 + reg-names: 39 + items: 40 + - const: prcmu 41 + - const: prcmu-tcpm 42 + - const: prcmu-tcdm 43 + 44 + interrupts: 45 + maxItems: 1 46 + 47 + '#address-cells': 48 + const: 1 49 + 50 + '#size-cells': 51 + const: 1 52 + 53 + ranges: true 54 + 55 + interrupt-controller: true 56 + 57 + '#interrupt-cells': 58 + const: 2 59 + 60 + db8500-prcmu-regulators: 61 + description: Node describing the DB8500 regulators. These are mainly 62 + power rails inside the silicon but some of those are also routed 63 + out to external pins. 64 + type: object 65 + 66 + properties: 67 + compatible: 68 + const: stericsson,db8500-prcmu-regulator 69 + 70 + db8500_vape: 71 + description: The voltage for the application processor, the 72 + main voltage domain for the chip. 73 + type: object 74 + $ref: ../regulator/regulator.yaml# 75 + 76 + db8500_varm: 77 + description: The voltage for the ARM Cortex A-9 CPU. 78 + type: object 79 + $ref: ../regulator/regulator.yaml# 80 + 81 + db8500_vmodem: 82 + description: The voltage for the modem subsystem. 83 + type: object 84 + $ref: ../regulator/regulator.yaml# 85 + 86 + db8500_vpll: 87 + description: The voltage for the phase locked loop clocks. 88 + type: object 89 + $ref: ../regulator/regulator.yaml# 90 + 91 + db8500_vsmps1: 92 + description: Also known as VIO12, is a step-down voltage regulator 93 + for 1.2V I/O. SMPS means System Management Power Source. 94 + type: object 95 + $ref: ../regulator/regulator.yaml# 96 + 97 + db8500_vsmps2: 98 + description: Also known as VIO18, is a step-down voltage regulator 99 + for 1.8V I/O. SMPS means System Management Power Source. 100 + type: object 101 + $ref: ../regulator/regulator.yaml# 102 + 103 + db8500_vsmps3: 104 + description: This is a step-down voltage regulator 105 + for 0.87 thru 1.875V I/O. SMPS means System Management Power Source. 106 + type: object 107 + $ref: ../regulator/regulator.yaml# 108 + 109 + db8500_vrf1: 110 + description: RF transciever voltage regulator. 111 + type: object 112 + $ref: ../regulator/regulator.yaml# 113 + 114 + db8500_sva_mmdsp: 115 + description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP) 116 + voltage regulator. This is the voltage for the accelerator DSP 117 + for video encoding and decoding. 118 + type: object 119 + $ref: ../regulator/regulator.yaml# 120 + 121 + db8500_sva_mmdsp_ret: 122 + description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP) 123 + voltage regulator for retention mode. 124 + type: object 125 + $ref: ../regulator/regulator.yaml# 126 + 127 + db8500_sva_pipe: 128 + description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP) 129 + voltage regulator for the data pipe. 130 + type: object 131 + $ref: ../regulator/regulator.yaml# 132 + 133 + db8500_sia_mmdsp: 134 + description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP) 135 + voltage regulator. This is the voltage for the accelerator DSP 136 + for image encoding and decoding. 137 + type: object 138 + $ref: ../regulator/regulator.yaml# 139 + 140 + db8500_sia_mmdsp_ret: 141 + description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP) 142 + voltage regulator for retention mode. 143 + type: object 144 + $ref: ../regulator/regulator.yaml# 145 + 146 + db8500_sia_pipe: 147 + description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP) 148 + voltage regulator for the data pipe. 149 + type: object 150 + $ref: ../regulator/regulator.yaml# 151 + 152 + db8500_sga: 153 + description: Smart Graphics Accelerator (SGA) voltage regulator. 154 + This is in effect controlling the power to the MALI400 3D 155 + accelerator block. 156 + type: object 157 + $ref: ../regulator/regulator.yaml# 158 + 159 + db8500_b2r2_mcde: 160 + description: Blit Blend Rotate and Rescale (B2R2), and Multi-Channel 161 + Display Engine (MCDE) voltage regulator. These are two graphics 162 + blocks. 163 + type: object 164 + $ref: ../regulator/regulator.yaml# 165 + 166 + db8500_esram12: 167 + description: Embedded Static RAM (ESRAM) 1 and 2 voltage regulator. 168 + type: object 169 + $ref: ../regulator/regulator.yaml# 170 + 171 + db8500_esram12_ret: 172 + description: Embedded Static RAM (ESRAM) 1 and 2 voltage regulator for 173 + retention mode. 174 + type: object 175 + $ref: ../regulator/regulator.yaml# 176 + 177 + db8500_esram34: 178 + description: Embedded Static RAM (ESRAM) 3 and 4 voltage regulator. 179 + type: object 180 + $ref: ../regulator/regulator.yaml# 181 + 182 + db8500_esram34_ret: 183 + description: Embedded Static RAM (ESRAM) 3 and 4 voltage regulator for 184 + retention mode. 185 + type: object 186 + $ref: ../regulator/regulator.yaml# 187 + 188 + required: 189 + - compatible 190 + - db8500_vape 191 + - db8500_varm 192 + - db8500_vmodem 193 + - db8500_vpll 194 + - db8500_vsmps1 195 + - db8500_vsmps2 196 + - db8500_vsmps3 197 + - db8500_vrf1 198 + - db8500_sva_mmdsp 199 + - db8500_sva_mmdsp_ret 200 + - db8500_sva_pipe 201 + - db8500_sia_mmdsp 202 + - db8500_sia_mmdsp_ret 203 + - db8500_sia_pipe 204 + - db8500_sga 205 + - db8500_b2r2_mcde 206 + - db8500_esram12 207 + - db8500_esram12_ret 208 + - db8500_esram34 209 + - db8500_esram34_ret 210 + 211 + additionalProperties: false 212 + 213 + patternProperties: 214 + "^thermal@[0-9a-f]+$": 215 + description: Node describing the DB8500 thermal control functions. 216 + This binds to an operating system driver that monitors the 217 + temperature of the SoC. 218 + type: object 219 + 220 + properties: 221 + compatible: 222 + const: stericsson,db8500-thermal 223 + 224 + reg: 225 + maxItems: 1 226 + 227 + interrupts: 228 + items: 229 + - description: Hotmon low interrupt (falling temperature) 230 + - description: Hotmon high interrupt (rising temperature) 231 + 232 + interrupt-names: 233 + items: 234 + - const: IRQ_HOTMON_LOW 235 + - const: IRQ_HOTMON_HIGH 236 + 237 + '#thermal-sensor-cells': 238 + const: 0 239 + 240 + additionalProperties: false 241 + 242 + "^prcmu-timer-4@[0-9a-f]+$": 243 + description: Node describing the externally visible timer 4 in the 244 + PRCMU block. This timer is interesting to the operating system 245 + since even thought it has a very low resolution (32768 Hz) it is 246 + always on, and thus provides a consistent monotonic timeline for 247 + the system. 248 + type: object 249 + 250 + properties: 251 + compatible: 252 + const: stericsson,db8500-prcmu-timer-4 253 + 254 + reg: 255 + maxItems: 1 256 + 257 + additionalProperties: false 258 + 259 + "^ab850[05]$": 260 + description: Node describing the Analog Baseband 8500 mixed-signals 261 + ASIC AB8500 and subcomponents. The AB8500 is accessed through the 262 + PRCMU and hence it appears here. This component has a separate 263 + set of devicetree bindings. The AB8505 is a newer version of the 264 + same ASIC. 265 + type: object 266 + 267 + required: 268 + - compatible 269 + - reg 270 + - '#address-cells' 271 + - '#size-cells' 272 + - ranges 273 + - interrupts 274 + - interrupt-controller 275 + - '#interrupt-cells' 276 + - db8500-prcmu-regulators 277 + 278 + additionalProperties: false

-10

MAINTAINERS

··· 9418 9418 F: drivers/mfd/intel-m10-bmc.c 9419 9419 F: include/linux/mfd/intel-m10-bmc.h 9420 9420 9421 - INTEL MAX 10 BMC MFD DRIVER 9422 - M: Xu Yilun <yilun.xu@intel.com> 9423 - R: Tom Rix <trix@redhat.com> 9424 - S: Maintained 9425 - F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc 9426 - F: Documentation/hwmon/intel-m10-bmc-hwmon.rst 9427 - F: drivers/hwmon/intel-m10-bmc-hwmon.c 9428 - F: drivers/mfd/intel-m10-bmc.c 9429 - F: include/linux/mfd/intel-m10-bmc.h 9430 - 9431 9421 INTEL MENLOW THERMAL DRIVER 9432 9422 M: Sujith Thomas <sujith.thomas@intel.com> 9433 9423 L: platform-driver-x86@vger.kernel.org

+3 -3

drivers/gpio/gpio-lp87565.c

··· 123 123 return regmap_update_bits(gpio->map, 124 124 LP87565_REG_GPIO_CONFIG, 125 125 BIT(offset + 126 - __ffs(LP87565_GOIO1_OD)), 126 + __ffs(LP87565_GPIO1_OD)), 127 127 BIT(offset + 128 - __ffs(LP87565_GOIO1_OD))); 128 + __ffs(LP87565_GPIO1_OD))); 129 129 case PIN_CONFIG_DRIVE_PUSH_PULL: 130 130 return regmap_update_bits(gpio->map, 131 131 LP87565_REG_GPIO_CONFIG, 132 132 BIT(offset + 133 - __ffs(LP87565_GOIO1_OD)), 0); 133 + __ffs(LP87565_GPIO1_OD)), 0); 134 134 default: 135 135 return -ENOTSUPP; 136 136 }

+2 -12

drivers/mfd/88pm800.c

··· 122 122 MODULE_DEVICE_TABLE(i2c, pm80x_id_table); 123 123 124 124 static const struct resource rtc_resources[] = { 125 - { 126 - .name = "88pm80x-rtc", 127 - .start = PM800_IRQ_RTC, 128 - .end = PM800_IRQ_RTC, 129 - .flags = IORESOURCE_IRQ, 130 - }, 125 + DEFINE_RES_IRQ_NAMED(PM800_IRQ_RTC, "88pm80x-rtc"), 131 126 }; 132 127 133 128 static struct mfd_cell rtc_devs[] = { ··· 135 140 }; 136 141 137 142 static struct resource onkey_resources[] = { 138 - { 139 - .name = "88pm80x-onkey", 140 - .start = PM800_IRQ_ONKEY, 141 - .end = PM800_IRQ_ONKEY, 142 - .flags = IORESOURCE_IRQ, 143 - }, 143 + DEFINE_RES_IRQ_NAMED(PM800_IRQ_ONKEY, "88pm80x-onkey"), 144 144 }; 145 145 146 146 static const struct mfd_cell onkey_devs[] = {

+8 -21

drivers/mfd/88pm805.c

··· 54 54 }; 55 55 56 56 static struct resource codec_resources[] = { 57 - { 58 - /* Headset microphone insertion or removal */ 59 - .name = "micin", 60 - .start = PM805_IRQ_MIC_DET, 61 - .end = PM805_IRQ_MIC_DET, 62 - .flags = IORESOURCE_IRQ, 63 - }, 64 - { 65 - /* Audio short HP1 */ 66 - .name = "audio-short1", 67 - .start = PM805_IRQ_HP1_SHRT, 68 - .end = PM805_IRQ_HP1_SHRT, 69 - .flags = IORESOURCE_IRQ, 70 - }, 71 - { 72 - /* Audio short HP2 */ 73 - .name = "audio-short2", 74 - .start = PM805_IRQ_HP2_SHRT, 75 - .end = PM805_IRQ_HP2_SHRT, 76 - .flags = IORESOURCE_IRQ, 77 - }, 57 + /* Headset microphone insertion or removal */ 58 + DEFINE_RES_IRQ_NAMED(PM805_IRQ_MIC_DET, "micin"), 59 + 60 + /* Audio short HP1 */ 61 + DEFINE_RES_IRQ_NAMED(PM805_IRQ_HP1_SHRT, "audio-short1"), 62 + 63 + /* Audio short HP2 */ 64 + DEFINE_RES_IRQ_NAMED(PM805_IRQ_HP2_SHRT, "audio-short2"), 78 65 }; 79 66 80 67 static const struct mfd_cell codec_devs[] = {

+28 -1

drivers/mfd/Kconfig

··· 465 465 tristate "Monolithic Power Systems MP2629 ADC and Battery charger" 466 466 depends on I2C 467 467 select REGMAP_I2C 468 + select MFD_CORE 468 469 help 469 470 Select this option to enable support for Monolithic Power Systems 470 471 battery charger. This provides ADC, thermal and battery charger power ··· 903 902 select MFD_CORE 904 903 select REGMAP_I2C 905 904 select REGMAP_IRQ 905 + select CRC8 906 906 depends on I2C 907 907 help 908 908 Say Y here to enable MT6360 PMU/PMIC/LDO functional support. ··· 1078 1076 southbridge which provides access to GPIOs and Watchdog using the 1079 1077 southbridge PCI device configuration space. 1080 1078 1079 + config MFD_RT4831 1080 + tristate "Richtek RT4831 four channel WLED and Display Bias Voltage" 1081 + depends on I2C 1082 + select MFD_CORE 1083 + select REGMAP_I2C 1084 + help 1085 + This enables support for the Richtek RT4831 that includes 4 channel 1086 + WLED driving and Display Bias Voltage. It's commonly used to provide 1087 + power to the LCD display and LCD backlight. 1088 + 1081 1089 config MFD_RT5033 1082 1090 tristate "Richtek RT5033 Power Management IC" 1083 1091 depends on I2C ··· 1145 1133 config MFD_SEC_CORE 1146 1134 tristate "Samsung Electronics PMIC Series Support" 1147 1135 depends on I2C=y 1136 + depends on OF || COMPILE_TEST 1148 1137 select MFD_CORE 1149 1138 select REGMAP_I2C 1150 1139 select REGMAP_IRQ ··· 1783 1770 select REGMAP 1784 1771 select REGMAP_IRQ 1785 1772 select MFD_CORE 1786 - bool 1773 + tristate 1787 1774 1788 1775 config MFD_ARIZONA_I2C 1789 1776 tristate "Cirrus Logic/Wolfson Microelectronics Arizona platform with I2C" ··· 2099 2086 Support for Embedded Controller found on Acer Iconia Tab A500. 2100 2087 The controller itself is ENE KB930, it is running firmware 2101 2088 customized for the specific needs of the Acer A500 hardware. 2089 + 2090 + config MFD_QCOM_PM8008 2091 + tristate "QCOM PM8008 Power Management IC" 2092 + depends on I2C && OF 2093 + select REGMAP_I2C 2094 + select REGMAP_IRQ 2095 + help 2096 + Select this option to get support for the Qualcomm Technologies, Inc. 2097 + PM8008 PMIC chip. PM8008 is a dedicated camera PMIC that integrates 2098 + all the necessary power management, housekeeping, and interface 2099 + support functions into a single IC. This driver provides common 2100 + support for accessing the device by instantiating all the child nodes 2101 + under it in the device tree. Additional drivers must be enabled in 2102 + order to use the functionality of the device. 2102 2103 2103 2104 menu "Multimedia Capabilities Port drivers" 2104 2105 depends on ARCH_SA1100

+9 -7

drivers/mfd/Makefile

··· 41 41 42 42 obj-$(CONFIG_MFD_LOCHNAGAR) += lochnagar-i2c.o 43 43 44 - obj-$(CONFIG_MFD_ARIZONA) += arizona-core.o 45 - obj-$(CONFIG_MFD_ARIZONA) += arizona-irq.o 44 + arizona-objs := arizona-core.o arizona-irq.o 45 + obj-$(CONFIG_MFD_ARIZONA) += arizona.o 46 46 obj-$(CONFIG_MFD_ARIZONA_I2C) += arizona-i2c.o 47 47 obj-$(CONFIG_MFD_ARIZONA_SPI) += arizona-spi.o 48 48 ifeq ($(CONFIG_MFD_WM5102),y) 49 - obj-$(CONFIG_MFD_ARIZONA) += wm5102-tables.o 49 + arizona-objs += wm5102-tables.o 50 50 endif 51 51 ifeq ($(CONFIG_MFD_WM5110),y) 52 - obj-$(CONFIG_MFD_ARIZONA) += wm5110-tables.o 52 + arizona-objs += wm5110-tables.o 53 53 endif 54 54 ifeq ($(CONFIG_MFD_WM8997),y) 55 - obj-$(CONFIG_MFD_ARIZONA) += wm8997-tables.o 55 + arizona-objs += wm8997-tables.o 56 56 endif 57 57 ifeq ($(CONFIG_MFD_WM8998),y) 58 - obj-$(CONFIG_MFD_ARIZONA) += wm8998-tables.o 58 + arizona-objs += wm8998-tables.o 59 59 endif 60 60 ifeq ($(CONFIG_MFD_CS47L24),y) 61 - obj-$(CONFIG_MFD_ARIZONA) += cs47l24-tables.o 61 + arizona-objs += cs47l24-tables.o 62 62 endif 63 63 obj-$(CONFIG_MFD_WCD934X) += wcd934x.o 64 64 obj-$(CONFIG_MFD_WM8400) += wm8400-core.o ··· 233 233 obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o 234 234 obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o 235 235 obj-$(CONFIG_MFD_DLN2) += dln2.o 236 + obj-$(CONFIG_MFD_RT4831) += rt4831.o 236 237 obj-$(CONFIG_MFD_RT5033) += rt5033.o 237 238 obj-$(CONFIG_MFD_SKY81452) += sky81452.o 238 239 ··· 264 263 obj-$(CONFIG_MFD_STMFX) += stmfx.o 265 264 obj-$(CONFIG_MFD_KHADAS_MCU) += khadas-mcu.o 266 265 obj-$(CONFIG_MFD_ACER_A500_EC) += acer-ec-a500.o 266 + obj-$(CONFIG_MFD_QCOM_PM8008) += qcom-pm8008.o 267 267 268 268 obj-$(CONFIG_SGI_MFD_IOC3) += ioc3.o 269 269 obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o

+16 -17

drivers/mfd/ab8500-core.c

··· 827 827 }, 828 828 }; 829 829 830 - static ssize_t show_chip_id(struct device *dev, 831 - struct device_attribute *attr, char *buf) 830 + static ssize_t chip_id_show(struct device *dev, 831 + struct device_attribute *attr, char *buf) 832 832 { 833 833 struct ab8500 *ab8500; 834 834 ··· 848 848 * 0x40 Power on key 1 pressed longer than 10 seconds 849 849 * 0x80 DB8500 thermal shutdown 850 850 */ 851 - static ssize_t show_switch_off_status(struct device *dev, 852 - struct device_attribute *attr, char *buf) 851 + static ssize_t switch_off_status_show(struct device *dev, 852 + struct device_attribute *attr, char *buf) 853 853 { 854 854 int ret; 855 855 u8 value; ··· 883 883 * 0x40 UsbIDDetect 884 884 * 0x80 Reserved 885 885 */ 886 - static ssize_t show_turn_on_status(struct device *dev, 887 - struct device_attribute *attr, char *buf) 886 + static ssize_t turn_on_status_show(struct device *dev, 887 + struct device_attribute *attr, char *buf) 888 888 { 889 889 int ret; 890 890 u8 value; ··· 912 912 return sprintf(buf, "%#x\n", value); 913 913 } 914 914 915 - static ssize_t show_turn_on_status_2(struct device *dev, 916 - struct device_attribute *attr, char *buf) 915 + static ssize_t turn_on_status_2_show(struct device *dev, 916 + struct device_attribute *attr, char *buf) 917 917 { 918 918 int ret; 919 919 u8 value; ··· 927 927 return sprintf(buf, "%#x\n", (value & 0x1)); 928 928 } 929 929 930 - static ssize_t show_ab9540_dbbrstn(struct device *dev, 931 - struct device_attribute *attr, char *buf) 930 + static ssize_t dbbrstn_show(struct device *dev, 931 + struct device_attribute *attr, char *buf) 932 932 { 933 933 struct ab8500 *ab8500; 934 934 int ret; ··· 945 945 (value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0); 946 946 } 947 947 948 - static ssize_t store_ab9540_dbbrstn(struct device *dev, 948 + static ssize_t dbbrstn_store(struct device *dev, 949 949 struct device_attribute *attr, const char *buf, size_t count) 950 950 { 951 951 struct ab8500 *ab8500; ··· 980 980 return ret; 981 981 } 982 982 983 - static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL); 984 - static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL); 985 - static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL); 986 - static DEVICE_ATTR(turn_on_status_2, S_IRUGO, show_turn_on_status_2, NULL); 987 - static DEVICE_ATTR(dbbrstn, S_IRUGO | S_IWUSR, 988 - show_ab9540_dbbrstn, store_ab9540_dbbrstn); 983 + static DEVICE_ATTR_RO(chip_id); 984 + static DEVICE_ATTR_RO(switch_off_status); 985 + static DEVICE_ATTR_RO(turn_on_status); 986 + static DEVICE_ATTR_RO(turn_on_status_2); 987 + static DEVICE_ATTR_RW(dbbrstn); 989 988 990 989 static struct attribute *ab8500_sysfs_entries[] = { 991 990 &dev_attr_chip_id.attr,

+2

drivers/mfd/arizona-core.c

··· 1447 1447 return 0; 1448 1448 } 1449 1449 EXPORT_SYMBOL_GPL(arizona_dev_exit); 1450 + 1451 + MODULE_LICENSE("GPL v2");

+2 -12

drivers/mfd/as3722.c

··· 24 24 #define AS3722_DEVICE_ID 0x0C 25 25 26 26 static const struct resource as3722_rtc_resource[] = { 27 - { 28 - .name = "as3722-rtc-alarm", 29 - .start = AS3722_IRQ_RTC_ALARM, 30 - .end = AS3722_IRQ_RTC_ALARM, 31 - .flags = IORESOURCE_IRQ, 32 - }, 27 + DEFINE_RES_IRQ_NAMED(AS3722_IRQ_RTC_ALARM, "as3722-rtc-alarm"), 33 28 }; 34 29 35 30 static const struct resource as3722_adc_resource[] = { 36 - { 37 - .name = "as3722-adc", 38 - .start = AS3722_IRQ_ADC, 39 - .end = AS3722_IRQ_ADC, 40 - .flags = IORESOURCE_IRQ, 41 - }, 31 + DEFINE_RES_IRQ_NAMED(AS3722_IRQ_ADC, "as3722-adc"), 42 32 }; 43 33 44 34 static const struct mfd_cell as3722_devs[] = {

+2 -10

drivers/mfd/asic3.c

··· 723 723 }; 724 724 725 725 static struct resource asic3_mmc_resources[] = { 726 - { 727 - .start = ASIC3_SD_CTRL_BASE, 728 - .end = ASIC3_SD_CTRL_BASE + 0x3ff, 729 - .flags = IORESOURCE_MEM, 730 - }, 731 - { 732 - .start = 0, 733 - .end = 0, 734 - .flags = IORESOURCE_IRQ, 735 - }, 726 + DEFINE_RES_MEM(ASIC3_SD_CTRL_BASE, 0x400), 727 + DEFINE_RES_IRQ(0) 736 728 }; 737 729 738 730 static int asic3_mmc_enable(struct platform_device *pdev)

+17 -7

drivers/mfd/axp20x.c

··· 884 884 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip; 885 885 break; 886 886 case AXP806_ID: 887 + /* 888 + * Don't register the power key part if in slave mode or 889 + * if there is no interrupt line. 890 + */ 887 891 if (of_property_read_bool(axp20x->dev->of_node, 888 - "x-powers,self-working-mode")) { 892 + "x-powers,self-working-mode") && 893 + axp20x->irq > 0) { 889 894 axp20x->nr_cells = ARRAY_SIZE(axp806_self_working_cells); 890 895 axp20x->cells = axp806_self_working_cells; 891 896 } else { ··· 964 959 AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE); 965 960 } 966 961 967 - ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq, 968 - IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags, 969 - -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc); 970 - if (ret) { 971 - dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret); 972 - return ret; 962 + /* Only if there is an interrupt line connected towards the CPU. */ 963 + if (axp20x->irq > 0) { 964 + ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq, 965 + IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags, 966 + -1, axp20x->regmap_irq_chip, 967 + &axp20x->regmap_irqc); 968 + if (ret) { 969 + dev_err(axp20x->dev, "failed to add irq chip: %d\n", 970 + ret); 971 + return ret; 972 + } 973 973 } 974 974 975 975 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,

+20 -1

drivers/mfd/cros_ec_dev.c

··· 5 5 * Copyright (C) 2014 Google, Inc. 6 6 */ 7 7 8 + #include <linux/dmi.h> 8 9 #include <linux/kconfig.h> 9 10 #include <linux/mfd/core.h> 10 11 #include <linux/module.h> ··· 113 112 static const struct mfd_cell cros_ec_platform_cells[] = { 114 113 { .name = "cros-ec-chardev", }, 115 114 { .name = "cros-ec-debugfs", }, 116 - { .name = "cros-ec-lightbar", }, 117 115 { .name = "cros-ec-sysfs", }, 116 + { .name = "cros-ec-pchg", }, 117 + }; 118 + 119 + static const struct mfd_cell cros_ec_lightbar_cells[] = { 120 + { .name = "cros-ec-lightbar", } 118 121 }; 119 122 120 123 static const struct mfd_cell cros_ec_vbc_cells[] = { ··· 209 204 cros_subdevices[i].mfd_cells->name, 210 205 retval); 211 206 } 207 + } 208 + 209 + /* 210 + * Lightbar is a special case. Newer devices support autodetection, 211 + * but older ones do not. 212 + */ 213 + if (cros_ec_check_features(ec, EC_FEATURE_LIGHTBAR) || 214 + dmi_match(DMI_PRODUCT_NAME, "Link")) { 215 + retval = mfd_add_hotplug_devices(ec->dev, 216 + cros_ec_lightbar_cells, 217 + ARRAY_SIZE(cros_ec_lightbar_cells)); 218 + if (retval) 219 + dev_warn(ec->dev, "failed to add lightbar: %d\n", 220 + retval); 212 221 } 213 222 214 223 /*

+3 -7

drivers/mfd/da9052-i2c.c

··· 113 113 {"da9053-bc", DA9053_BC}, 114 114 {} 115 115 }; 116 + MODULE_DEVICE_TABLE(i2c, da9052_i2c_id); 116 117 117 118 #ifdef CONFIG_OF 118 119 static const struct of_device_id dialog_dt_ids[] = { ··· 155 154 return ret; 156 155 157 156 #ifdef CONFIG_OF 158 - if (!id) { 159 - struct device_node *np = client->dev.of_node; 160 - const struct of_device_id *deviceid; 161 - 162 - deviceid = of_match_node(dialog_dt_ids, np); 163 - id = deviceid->data; 164 - } 157 + if (!id) 158 + id = of_device_get_match_data(&client->dev); 165 159 #endif 166 160 167 161 if (!id) {

+8 -30

drivers/mfd/da9055-core.c

··· 254 254 }; 255 255 EXPORT_SYMBOL_GPL(da9055_regmap_config); 256 256 257 - static const struct resource da9055_onkey_resource = { 258 - .name = "ONKEY", 259 - .start = DA9055_IRQ_NONKEY, 260 - .end = DA9055_IRQ_NONKEY, 261 - .flags = IORESOURCE_IRQ, 262 - }; 257 + static const struct resource da9055_onkey_resource = 258 + DEFINE_RES_IRQ_NAMED(DA9055_IRQ_NONKEY, "ONKEY"); 263 259 264 260 static const struct resource da9055_rtc_resource[] = { 265 - { 266 - .name = "ALM", 267 - .start = DA9055_IRQ_ALARM, 268 - .end = DA9055_IRQ_ALARM, 269 - .flags = IORESOURCE_IRQ, 270 - }, 271 - { 272 - .name = "TICK", 273 - .start = DA9055_IRQ_TICK, 274 - .end = DA9055_IRQ_TICK, 275 - .flags = IORESOURCE_IRQ, 276 - }, 261 + DEFINE_RES_IRQ_NAMED(DA9055_IRQ_ALARM, "ALM"), 262 + DEFINE_RES_IRQ_NAMED(DA9055_IRQ_TICK, "TICK"), 277 263 }; 278 264 279 - static const struct resource da9055_hwmon_resource = { 280 - .name = "HWMON", 281 - .start = DA9055_IRQ_HWMON, 282 - .end = DA9055_IRQ_HWMON, 283 - .flags = IORESOURCE_IRQ, 284 - }; 265 + static const struct resource da9055_hwmon_resource = 266 + DEFINE_RES_IRQ_NAMED(DA9055_IRQ_HWMON, "HWMON"); 285 267 286 - static const struct resource da9055_ld05_6_resource = { 287 - .name = "REGULATOR", 288 - .start = DA9055_IRQ_REGULATOR, 289 - .end = DA9055_IRQ_REGULATOR, 290 - .flags = IORESOURCE_IRQ, 291 - }; 268 + static const struct resource da9055_ld05_6_resource = 269 + DEFINE_RES_IRQ_NAMED(DA9055_IRQ_REGULATOR, "REGULATOR"); 292 270 293 271 static const struct mfd_cell da9055_devs[] = { 294 272 {

+4 -9

drivers/mfd/da9062-core.c

··· 9 9 #include <linux/init.h> 10 10 #include <linux/device.h> 11 11 #include <linux/interrupt.h> 12 + #include <linux/of_device.h> 12 13 #include <linux/regmap.h> 13 14 #include <linux/irq.h> 14 15 #include <linux/mfd/core.h> ··· 623 622 const struct i2c_device_id *id) 624 623 { 625 624 struct da9062 *chip; 626 - const struct of_device_id *match; 627 625 unsigned int irq_base; 628 626 const struct mfd_cell *cell; 629 627 const struct regmap_irq_chip *irq_chip; ··· 635 635 if (!chip) 636 636 return -ENOMEM; 637 637 638 - if (i2c->dev.of_node) { 639 - match = of_match_node(da9062_dt_ids, i2c->dev.of_node); 640 - if (!match) 641 - return -EINVAL; 642 - 643 - chip->chip_type = (uintptr_t)match->data; 644 - } else { 638 + if (i2c->dev.of_node) 639 + chip->chip_type = (uintptr_t)of_device_get_match_data(&i2c->dev); 640 + else 645 641 chip->chip_type = id->driver_data; 646 - } 647 642 648 643 i2c_set_clientdata(i2c, chip); 649 644 chip->dev = &i2c->dev;

+1 -1

drivers/mfd/da9063-i2c.c

··· 448 448 DA9063_TWOWIRE_TO); 449 449 if (ret < 0) { 450 450 dev_err(da9063->dev, "Failed to set Two-Wire Bus Mode.\n"); 451 - return -EIO; 451 + return ret; 452 452 } 453 453 } 454 454

+3 -3

drivers/mfd/db8500-prcmu.c

··· 616 616 } 617 617 618 618 /** 619 - * prcmu_get_current_mode - Return the current XP70 power mode 619 + * prcmu_get_xp70_current_state - Return the current XP70 power mode 620 620 * Returns: Returns the current AP(ARM) power mode: init, 621 621 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 622 622 */ ··· 898 898 } 899 899 900 900 /** 901 - * db8500_set_ape_opp - set the appropriate APE OPP 901 + * db8500_prcmu_set_ape_opp - set the appropriate APE OPP 902 902 * @opp: The new APE operating point to which transition is to be made 903 903 * Returns: 0 on success, non-zero on failure 904 904 * ··· 2297 2297 } 2298 2298 2299 2299 /** 2300 - * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 2300 + * db8500_prcmu_modem_reset - ask the PRCMU to reset modem 2301 2301 */ 2302 2302 void db8500_prcmu_modem_reset(void) 2303 2303 {

+1 -1

drivers/mfd/hi655x-pmic.c

+13

drivers/mfd/intel-lpss-pci.c

··· 310 310 { PCI_VDEVICE(INTEL, 0x51ea), (kernel_ulong_t)&bxt_i2c_info }, 311 311 { PCI_VDEVICE(INTEL, 0x51eb), (kernel_ulong_t)&bxt_i2c_info }, 312 312 { PCI_VDEVICE(INTEL, 0x51fb), (kernel_ulong_t)&bxt_info }, 313 + /* ADL-M */ 314 + { PCI_VDEVICE(INTEL, 0x54a8), (kernel_ulong_t)&bxt_uart_info }, 315 + { PCI_VDEVICE(INTEL, 0x54a9), (kernel_ulong_t)&bxt_uart_info }, 316 + { PCI_VDEVICE(INTEL, 0x54aa), (kernel_ulong_t)&bxt_info }, 317 + { PCI_VDEVICE(INTEL, 0x54ab), (kernel_ulong_t)&bxt_info }, 318 + { PCI_VDEVICE(INTEL, 0x54c5), (kernel_ulong_t)&bxt_i2c_info }, 319 + { PCI_VDEVICE(INTEL, 0x54c6), (kernel_ulong_t)&bxt_i2c_info }, 320 + { PCI_VDEVICE(INTEL, 0x54c7), (kernel_ulong_t)&bxt_uart_info }, 321 + { PCI_VDEVICE(INTEL, 0x54e8), (kernel_ulong_t)&bxt_i2c_info }, 322 + { PCI_VDEVICE(INTEL, 0x54e9), (kernel_ulong_t)&bxt_i2c_info }, 323 + { PCI_VDEVICE(INTEL, 0x54ea), (kernel_ulong_t)&bxt_i2c_info }, 324 + { PCI_VDEVICE(INTEL, 0x54eb), (kernel_ulong_t)&bxt_i2c_info }, 325 + { PCI_VDEVICE(INTEL, 0x54fb), (kernel_ulong_t)&bxt_info }, 313 326 /* APL */ 314 327 { PCI_VDEVICE(INTEL, 0x5aac), (kernel_ulong_t)&apl_i2c_info }, 315 328 { PCI_VDEVICE(INTEL, 0x5aae), (kernel_ulong_t)&apl_i2c_info },

+10 -10

drivers/mfd/intel_soc_pmic_bxtwc.c

··· 330 330 331 331 /* sysfs interfaces to r/w PMIC registers, required by initial script */ 332 332 static unsigned long bxtwc_reg_addr; 333 - static ssize_t bxtwc_reg_show(struct device *dev, 334 - struct device_attribute *attr, char *buf) 333 + static ssize_t addr_show(struct device *dev, 334 + struct device_attribute *attr, char *buf) 335 335 { 336 336 return sprintf(buf, "0x%lx\n", bxtwc_reg_addr); 337 337 } 338 338 339 - static ssize_t bxtwc_reg_store(struct device *dev, 340 - struct device_attribute *attr, const char *buf, size_t count) 339 + static ssize_t addr_store(struct device *dev, 340 + struct device_attribute *attr, const char *buf, size_t count) 341 341 { 342 342 if (kstrtoul(buf, 0, &bxtwc_reg_addr)) { 343 343 dev_err(dev, "Invalid register address\n"); ··· 346 346 return (ssize_t)count; 347 347 } 348 348 349 - static ssize_t bxtwc_val_show(struct device *dev, 350 - struct device_attribute *attr, char *buf) 349 + static ssize_t val_show(struct device *dev, 350 + struct device_attribute *attr, char *buf) 351 351 { 352 352 int ret; 353 353 unsigned int val; ··· 362 362 return sprintf(buf, "0x%02x\n", val); 363 363 } 364 364 365 - static ssize_t bxtwc_val_store(struct device *dev, 366 - struct device_attribute *attr, const char *buf, size_t count) 365 + static ssize_t val_store(struct device *dev, 366 + struct device_attribute *attr, const char *buf, size_t count) 367 367 { 368 368 int ret; 369 369 unsigned int val; ··· 382 382 return count; 383 383 } 384 384 385 - static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store); 386 - static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store); 385 + static DEVICE_ATTR_ADMIN_RW(addr); 386 + static DEVICE_ATTR_ADMIN_RW(val); 387 387 static struct attribute *bxtwc_attrs[] = { 388 388 &dev_attr_addr.attr, 389 389 &dev_attr_val.attr,

+3 -3

drivers/mfd/janz-cmodio.c

··· 149 149 * SYSFS Attributes 150 150 */ 151 151 152 - static ssize_t mbus_show(struct device *dev, struct device_attribute *attr, 153 - char *buf) 152 + static ssize_t modulbus_number_show(struct device *dev, 153 + struct device_attribute *attr, char *buf) 154 154 { 155 155 struct cmodio_device *priv = dev_get_drvdata(dev); 156 156 157 157 return snprintf(buf, PAGE_SIZE, "%x\n", priv->hex); 158 158 } 159 159 160 - static DEVICE_ATTR(modulbus_number, S_IRUGO, mbus_show, NULL); 160 + static DEVICE_ATTR_RO(modulbus_number); 161 161 162 162 static struct attribute *cmodio_sysfs_attrs[] = { 163 163 &dev_attr_modulbus_number.attr,

+9 -10

drivers/mfd/kempld-core.c

··· 344 344 return version_type; 345 345 } 346 346 347 - static ssize_t kempld_version_show(struct device *dev, 348 - struct device_attribute *attr, char *buf) 347 + static ssize_t pld_version_show(struct device *dev, 348 + struct device_attribute *attr, char *buf) 349 349 { 350 350 struct kempld_device_data *pld = dev_get_drvdata(dev); 351 351 352 352 return scnprintf(buf, PAGE_SIZE, "%s\n", pld->info.version); 353 353 } 354 354 355 - static ssize_t kempld_specification_show(struct device *dev, 356 - struct device_attribute *attr, char *buf) 355 + static ssize_t pld_specification_show(struct device *dev, 356 + struct device_attribute *attr, char *buf) 357 357 { 358 358 struct kempld_device_data *pld = dev_get_drvdata(dev); 359 359 ··· 361 361 pld->info.spec_minor); 362 362 } 363 363 364 - static ssize_t kempld_type_show(struct device *dev, 365 - struct device_attribute *attr, char *buf) 364 + static ssize_t pld_type_show(struct device *dev, 365 + struct device_attribute *attr, char *buf) 366 366 { 367 367 struct kempld_device_data *pld = dev_get_drvdata(dev); 368 368 369 369 return scnprintf(buf, PAGE_SIZE, "%s\n", kempld_get_type_string(pld)); 370 370 } 371 371 372 - static DEVICE_ATTR(pld_version, S_IRUGO, kempld_version_show, NULL); 373 - static DEVICE_ATTR(pld_specification, S_IRUGO, kempld_specification_show, 374 - NULL); 375 - static DEVICE_ATTR(pld_type, S_IRUGO, kempld_type_show, NULL); 372 + static DEVICE_ATTR_RO(pld_version); 373 + static DEVICE_ATTR_RO(pld_specification); 374 + static DEVICE_ATTR_RO(pld_type); 376 375 377 376 static struct attribute *pld_attributes[] = { 378 377 &dev_attr_pld_version.attr,

+27

drivers/mfd/lp87565.c

··· 5 5 * Author: Keerthy <j-keerthy@ti.com> 6 6 */ 7 7 8 + #include <linux/gpio/consumer.h> 8 9 #include <linux/interrupt.h> 9 10 #include <linux/mfd/core.h> 10 11 #include <linux/module.h> ··· 65 64 return ret; 66 65 } 67 66 67 + lp87565->reset_gpio = devm_gpiod_get_optional(lp87565->dev, "reset", 68 + GPIOD_OUT_LOW); 69 + if (IS_ERR(lp87565->reset_gpio)) { 70 + ret = PTR_ERR(lp87565->reset_gpio); 71 + if (ret == -EPROBE_DEFER) 72 + return ret; 73 + } 74 + 75 + if (lp87565->reset_gpio) { 76 + gpiod_set_value_cansleep(lp87565->reset_gpio, 1); 77 + /* The minimum assertion time is undocumented, just guess */ 78 + usleep_range(2000, 4000); 79 + 80 + gpiod_set_value_cansleep(lp87565->reset_gpio, 0); 81 + /* Min 1.2 ms before first I2C transaction */ 82 + usleep_range(1500, 3000); 83 + } 84 + 68 85 ret = regmap_read(lp87565->regmap, LP87565_REG_OTP_REV, &otpid); 69 86 if (ret) { 70 87 dev_err(lp87565->dev, "Failed to read OTP ID\n"); ··· 102 83 NULL, 0, NULL); 103 84 } 104 85 86 + static void lp87565_shutdown(struct i2c_client *client) 87 + { 88 + struct lp87565 *lp87565 = i2c_get_clientdata(client); 89 + 90 + gpiod_set_value_cansleep(lp87565->reset_gpio, 1); 91 + } 92 + 105 93 static const struct i2c_device_id lp87565_id_table[] = { 106 94 { "lp87565-q1", 0 }, 107 95 { }, ··· 121 95 .of_match_table = of_lp87565_match_table, 122 96 }, 123 97 .probe = lp87565_probe, 98 + .shutdown = lp87565_shutdown, 124 99 .id_table = lp87565_id_table, 125 100 }; 126 101 module_i2c_driver(lp87565_driver);

+2 -6

drivers/mfd/max8907.c

··· 228 228 goto err_regmap_rtc; 229 229 } 230 230 231 - irq_set_status_flags(max8907->i2c_gen->irq, IRQ_NOAUTOEN); 232 - 233 231 ret = regmap_add_irq_chip(max8907->regmap_gen, max8907->i2c_gen->irq, 234 - IRQF_ONESHOT | IRQF_SHARED, -1, 235 - &max8907_chg_irq_chip, 232 + IRQF_ONESHOT | IRQF_SHARED, 233 + -1, &max8907_chg_irq_chip, 236 234 &max8907->irqc_chg); 237 235 if (ret != 0) { 238 236 dev_err(&i2c->dev, "failed to add chg irq chip: %d\n", ret); ··· 252 254 dev_err(&i2c->dev, "failed to add rtc irq chip: %d\n", ret); 253 255 goto err_irqc_rtc; 254 256 } 255 - 256 - enable_irq(max8907->i2c_gen->irq); 257 257 258 258 ret = mfd_add_devices(max8907->dev, -1, max8907_cells, 259 259 ARRAY_SIZE(max8907_cells), NULL, 0, NULL);

+4 -5

drivers/mfd/max8997.c

··· 11 11 #include <linux/slab.h> 12 12 #include <linux/i2c.h> 13 13 #include <linux/of.h> 14 + #include <linux/of_device.h> 14 15 #include <linux/of_irq.h> 15 16 #include <linux/interrupt.h> 16 17 #include <linux/pm_runtime.h> ··· 146 145 static inline unsigned long max8997_i2c_get_driver_data(struct i2c_client *i2c, 147 146 const struct i2c_device_id *id) 148 147 { 149 - if (IS_ENABLED(CONFIG_OF) && i2c->dev.of_node) { 150 - const struct of_device_id *match; 151 - match = of_match_node(max8997_pmic_dt_match, i2c->dev.of_node); 152 - return (unsigned long)match->data; 153 - } 148 + if (i2c->dev.of_node) 149 + return (unsigned long)of_device_get_match_data(&i2c->dev); 150 + 154 151 return id->driver_data; 155 152 } 156 153

+3 -5

drivers/mfd/max8998.c

··· 12 12 #include <linux/i2c.h> 13 13 #include <linux/interrupt.h> 14 14 #include <linux/of.h> 15 + #include <linux/of_device.h> 15 16 #include <linux/of_irq.h> 16 17 #include <linux/pm_runtime.h> 17 18 #include <linux/mutex.h> ··· 156 155 static inline unsigned long max8998_i2c_get_driver_data(struct i2c_client *i2c, 157 156 const struct i2c_device_id *id) 158 157 { 159 - if (IS_ENABLED(CONFIG_OF) && i2c->dev.of_node) { 160 - const struct of_device_id *match; 161 - match = of_match_node(max8998_dt_match, i2c->dev.of_node); 162 - return (unsigned long)match->data; 163 - } 158 + if (i2c->dev.of_node) 159 + return (unsigned long)of_device_get_match_data(&i2c->dev); 164 160 165 161 return id->driver_data; 166 162 }

+9 -6

drivers/mfd/mfd-core.c

··· 266 266 if (has_acpi_companion(&pdev->dev)) { 267 267 ret = acpi_check_resource_conflict(&res[r]); 268 268 if (ret) 269 - goto fail_of_entry; 269 + goto fail_res_conflict; 270 270 } 271 271 } 272 272 } 273 273 274 274 ret = platform_device_add_resources(pdev, res, cell->num_resources); 275 275 if (ret) 276 - goto fail_of_entry; 276 + goto fail_res_conflict; 277 277 278 278 ret = platform_device_add(pdev); 279 279 if (ret) 280 - goto fail_of_entry; 280 + goto fail_res_conflict; 281 281 282 282 if (cell->pm_runtime_no_callbacks) 283 283 pm_runtime_no_callbacks(&pdev->dev); ··· 286 286 287 287 return 0; 288 288 289 + fail_res_conflict: 290 + if (cell->swnode) 291 + device_remove_software_node(&pdev->dev); 289 292 fail_of_entry: 290 293 list_for_each_entry_safe(of_entry, tmp, &mfd_of_node_list, list) 291 294 if (of_entry->dev == &pdev->dev) { 292 295 list_del(&of_entry->list); 293 296 kfree(of_entry); 294 297 } 295 - device_remove_software_node(&pdev->dev); 296 298 fail_alias: 297 299 regulator_bulk_unregister_supply_alias(&pdev->dev, 298 300 cell->parent_supplies, ··· 360 358 if (level && cell->level > *level) 361 359 return 0; 362 360 361 + if (cell->swnode) 362 + device_remove_software_node(&pdev->dev); 363 + 363 364 regulator_bulk_unregister_supply_alias(dev, cell->parent_supplies, 364 365 cell->num_parent_supplies); 365 - 366 - device_remove_software_node(&pdev->dev); 367 366 368 367 platform_device_unregister(pdev); 369 368 return 0;

+4

drivers/mfd/motorola-cpcap.c

··· 327 327 if (ret) 328 328 return ret; 329 329 330 + /* Parent SPI controller uses DMA, CPCAP and child devices do not */ 331 + spi->dev.coherent_dma_mask = 0; 332 + spi->dev.dma_mask = &spi->dev.coherent_dma_mask; 333 + 330 334 return devm_mfd_add_devices(&spi->dev, 0, cpcap_mfd_devices, 331 335 ARRAY_SIZE(cpcap_mfd_devices), NULL, 0, NULL); 332 336 }

+386 -188

drivers/mfd/mt6360-core.c

··· 5 5 * Author: Gene Chen <gene_chen@richtek.com> 6 6 */ 7 7 8 + #include <linux/crc8.h> 8 9 #include <linux/i2c.h> 9 10 #include <linux/init.h> 10 11 #include <linux/interrupt.h> 11 12 #include <linux/kernel.h> 12 13 #include <linux/mfd/core.h> 13 14 #include <linux/module.h> 14 - #include <linux/of_irq.h> 15 - #include <linux/of_platform.h> 15 + #include <linux/regmap.h> 16 + #include <linux/slab.h> 16 17 17 - #include <linux/mfd/mt6360.h> 18 + enum { 19 + MT6360_SLAVE_TCPC = 0, 20 + MT6360_SLAVE_PMIC, 21 + MT6360_SLAVE_LDO, 22 + MT6360_SLAVE_PMU, 23 + MT6360_SLAVE_MAX, 24 + }; 25 + 26 + struct mt6360_ddata { 27 + struct i2c_client *i2c[MT6360_SLAVE_MAX]; 28 + struct device *dev; 29 + struct regmap *regmap; 30 + struct regmap_irq_chip_data *irq_data; 31 + unsigned int chip_rev; 32 + u8 crc8_tbl[CRC8_TABLE_SIZE]; 33 + }; 34 + 35 + #define MT6360_TCPC_SLAVEID 0x4E 36 + #define MT6360_PMIC_SLAVEID 0x1A 37 + #define MT6360_LDO_SLAVEID 0x64 38 + #define MT6360_PMU_SLAVEID 0x34 39 + 40 + #define MT6360_REG_TCPCSTART 0x00 41 + #define MT6360_REG_TCPCEND 0xFF 42 + #define MT6360_REG_PMICSTART 0x100 43 + #define MT6360_REG_PMICEND 0x13B 44 + #define MT6360_REG_LDOSTART 0x200 45 + #define MT6360_REG_LDOEND 0x21C 46 + #define MT6360_REG_PMUSTART 0x300 47 + #define MT6360_PMU_DEV_INFO 0x300 48 + #define MT6360_PMU_CHG_IRQ1 0x3D0 49 + #define MT6360_PMU_CHG_MASK1 0x3F0 50 + #define MT6360_REG_PMUEND 0x3FF 51 + 52 + #define MT6360_PMU_IRQ_REGNUM 16 53 + 54 + #define CHIP_VEN_MASK 0xF0 55 + #define CHIP_VEN_MT6360 0x50 56 + #define CHIP_REV_MASK 0x0F 57 + 58 + #define MT6360_ADDRESS_MASK 0x3F 59 + #define MT6360_DATA_SIZE_1_BYTE 0x00 60 + #define MT6360_DATA_SIZE_2_BYTES 0x40 61 + #define MT6360_DATA_SIZE_3_BYTES 0x80 62 + #define MT6360_DATA_SIZE_4_BYTES 0xC0 63 + 64 + #define MT6360_CRC8_POLYNOMIAL 0x7 65 + 66 + #define MT6360_CRC_I2C_ADDR_SIZE 1 67 + #define MT6360_CRC_REG_ADDR_SIZE 1 68 + /* prealloca read size = i2c device addr + i2c reg addr + val ... + crc8 */ 69 + #define MT6360_ALLOC_READ_SIZE(_size) (_size + 3) 70 + /* prealloca write size = i2c device addr + i2c reg addr + val ... + crc8 + dummy byte */ 71 + #define MT6360_ALLOC_WRITE_SIZE(_size) (_size + 4) 72 + #define MT6360_CRC_PREDATA_OFFSET (MT6360_CRC_I2C_ADDR_SIZE + MT6360_CRC_REG_ADDR_SIZE) 73 + #define MT6360_CRC_CRC8_SIZE 1 74 + #define MT6360_CRC_DUMMY_BYTE_SIZE 1 75 + #define MT6360_REGMAP_REG_BYTE_SIZE 2 76 + #define I2C_ADDR_XLATE_8BIT(_addr, _rw) (((_addr & 0x7F) << 1) + _rw) 18 77 19 78 /* reg 0 -> 0 ~ 7 */ 20 - #define MT6360_CHG_TREG_EVT (4) 21 - #define MT6360_CHG_AICR_EVT (5) 22 - #define MT6360_CHG_MIVR_EVT (6) 23 - #define MT6360_PWR_RDY_EVT (7) 79 + #define MT6360_CHG_TREG_EVT 4 80 + #define MT6360_CHG_AICR_EVT 5 81 + #define MT6360_CHG_MIVR_EVT 6 82 + #define MT6360_PWR_RDY_EVT 7 24 83 /* REG 1 -> 8 ~ 15 */ 25 - #define MT6360_CHG_BATSYSUV_EVT (9) 26 - #define MT6360_FLED_CHG_VINOVP_EVT (11) 27 - #define MT6360_CHG_VSYSUV_EVT (12) 28 - #define MT6360_CHG_VSYSOV_EVT (13) 29 - #define MT6360_CHG_VBATOV_EVT (14) 30 - #define MT6360_CHG_VBUSOV_EVT (15) 84 + #define MT6360_CHG_BATSYSUV_EVT 9 85 + #define MT6360_FLED_CHG_VINOVP_EVT 11 86 + #define MT6360_CHG_VSYSUV_EVT 12 87 + #define MT6360_CHG_VSYSOV_EVT 13 88 + #define MT6360_CHG_VBATOV_EVT 14 89 + #define MT6360_CHG_VBUSOV_EVT 15 31 90 /* REG 2 -> 16 ~ 23 */ 32 91 /* REG 3 -> 24 ~ 31 */ 33 - #define MT6360_WD_PMU_DET (25) 34 - #define MT6360_WD_PMU_DONE (26) 35 - #define MT6360_CHG_TMRI (27) 36 - #define MT6360_CHG_ADPBADI (29) 37 - #define MT6360_CHG_RVPI (30) 38 - #define MT6360_OTPI (31) 92 + #define MT6360_WD_PMU_DET 25 93 + #define MT6360_WD_PMU_DONE 26 94 + #define MT6360_CHG_TMRI 27 95 + #define MT6360_CHG_ADPBADI 29 96 + #define MT6360_CHG_RVPI 30 97 + #define MT6360_OTPI 31 39 98 /* REG 4 -> 32 ~ 39 */ 40 - #define MT6360_CHG_AICCMEASL (32) 41 - #define MT6360_CHGDET_DONEI (34) 42 - #define MT6360_WDTMRI (35) 43 - #define MT6360_SSFINISHI (36) 44 - #define MT6360_CHG_RECHGI (37) 45 - #define MT6360_CHG_TERMI (38) 46 - #define MT6360_CHG_IEOCI (39) 99 + #define MT6360_CHG_AICCMEASL 32 100 + #define MT6360_CHGDET_DONEI 34 101 + #define MT6360_WDTMRI 35 102 + #define MT6360_SSFINISHI 36 103 + #define MT6360_CHG_RECHGI 37 104 + #define MT6360_CHG_TERMI 38 105 + #define MT6360_CHG_IEOCI 39 47 106 /* REG 5 -> 40 ~ 47 */ 48 - #define MT6360_PUMPX_DONEI (40) 49 - #define MT6360_BAT_OVP_ADC_EVT (41) 50 - #define MT6360_TYPEC_OTP_EVT (42) 51 - #define MT6360_ADC_WAKEUP_EVT (43) 52 - #define MT6360_ADC_DONEI (44) 53 - #define MT6360_BST_BATUVI (45) 54 - #define MT6360_BST_VBUSOVI (46) 55 - #define MT6360_BST_OLPI (47) 107 + #define MT6360_PUMPX_DONEI 40 108 + #define MT6360_BAT_OVP_ADC_EVT 41 109 + #define MT6360_TYPEC_OTP_EVT 42 110 + #define MT6360_ADC_WAKEUP_EVT 43 111 + #define MT6360_ADC_DONEI 44 112 + #define MT6360_BST_BATUVI 45 113 + #define MT6360_BST_VBUSOVI 46 114 + #define MT6360_BST_OLPI 47 56 115 /* REG 6 -> 48 ~ 55 */ 57 - #define MT6360_ATTACH_I (48) 58 - #define MT6360_DETACH_I (49) 59 - #define MT6360_QC30_STPDONE (51) 60 - #define MT6360_QC_VBUSDET_DONE (52) 61 - #define MT6360_HVDCP_DET (53) 62 - #define MT6360_CHGDETI (54) 63 - #define MT6360_DCDTI (55) 116 + #define MT6360_ATTACH_I 48 117 + #define MT6360_DETACH_I 49 118 + #define MT6360_QC30_STPDONE 51 119 + #define MT6360_QC_VBUSDET_DONE 52 120 + #define MT6360_HVDCP_DET 53 121 + #define MT6360_CHGDETI 54 122 + #define MT6360_DCDTI 55 64 123 /* REG 7 -> 56 ~ 63 */ 65 - #define MT6360_FOD_DONE_EVT (56) 66 - #define MT6360_FOD_OV_EVT (57) 67 - #define MT6360_CHRDET_UVP_EVT (58) 68 - #define MT6360_CHRDET_OVP_EVT (59) 69 - #define MT6360_CHRDET_EXT_EVT (60) 70 - #define MT6360_FOD_LR_EVT (61) 71 - #define MT6360_FOD_HR_EVT (62) 72 - #define MT6360_FOD_DISCHG_FAIL_EVT (63) 124 + #define MT6360_FOD_DONE_EVT 56 125 + #define MT6360_FOD_OV_EVT 57 126 + #define MT6360_CHRDET_UVP_EVT 58 127 + #define MT6360_CHRDET_OVP_EVT 59 128 + #define MT6360_CHRDET_EXT_EVT 60 129 + #define MT6360_FOD_LR_EVT 61 130 + #define MT6360_FOD_HR_EVT 62 131 + #define MT6360_FOD_DISCHG_FAIL_EVT 63 73 132 /* REG 8 -> 64 ~ 71 */ 74 - #define MT6360_USBID_EVT (64) 75 - #define MT6360_APWDTRST_EVT (65) 76 - #define MT6360_EN_EVT (66) 77 - #define MT6360_QONB_RST_EVT (67) 78 - #define MT6360_MRSTB_EVT (68) 79 - #define MT6360_OTP_EVT (69) 80 - #define MT6360_VDDAOV_EVT (70) 81 - #define MT6360_SYSUV_EVT (71) 133 + #define MT6360_USBID_EVT 64 134 + #define MT6360_APWDTRST_EVT 65 135 + #define MT6360_EN_EVT 66 136 + #define MT6360_QONB_RST_EVT 67 137 + #define MT6360_MRSTB_EVT 68 138 + #define MT6360_OTP_EVT 69 139 + #define MT6360_VDDAOV_EVT 70 140 + #define MT6360_SYSUV_EVT 71 82 141 /* REG 9 -> 72 ~ 79 */ 83 - #define MT6360_FLED_STRBPIN_EVT (72) 84 - #define MT6360_FLED_TORPIN_EVT (73) 85 - #define MT6360_FLED_TX_EVT (74) 86 - #define MT6360_FLED_LVF_EVT (75) 87 - #define MT6360_FLED2_SHORT_EVT (78) 88 - #define MT6360_FLED1_SHORT_EVT (79) 142 + #define MT6360_FLED_STRBPIN_EVT 72 143 + #define MT6360_FLED_TORPIN_EVT 73 144 + #define MT6360_FLED_TX_EVT 74 145 + #define MT6360_FLED_LVF_EVT 75 146 + #define MT6360_FLED2_SHORT_EVT 78 147 + #define MT6360_FLED1_SHORT_EVT 79 89 148 /* REG 10 -> 80 ~ 87 */ 90 - #define MT6360_FLED2_STRB_EVT (80) 91 - #define MT6360_FLED1_STRB_EVT (81) 92 - #define MT6360_FLED2_STRB_TO_EVT (82) 93 - #define MT6360_FLED1_STRB_TO_EVT (83) 94 - #define MT6360_FLED2_TOR_EVT (84) 95 - #define MT6360_FLED1_TOR_EVT (85) 149 + #define MT6360_FLED2_STRB_EVT 80 150 + #define MT6360_FLED1_STRB_EVT 81 151 + #define MT6360_FLED2_STRB_TO_EVT 82 152 + #define MT6360_FLED1_STRB_TO_EVT 83 153 + #define MT6360_FLED2_TOR_EVT 84 154 + #define MT6360_FLED1_TOR_EVT 85 96 155 /* REG 11 -> 88 ~ 95 */ 97 156 /* REG 12 -> 96 ~ 103 */ 98 - #define MT6360_BUCK1_PGB_EVT (96) 99 - #define MT6360_BUCK1_OC_EVT (100) 100 - #define MT6360_BUCK1_OV_EVT (101) 101 - #define MT6360_BUCK1_UV_EVT (102) 157 + #define MT6360_BUCK1_PGB_EVT 96 158 + #define MT6360_BUCK1_OC_EVT 100 159 + #define MT6360_BUCK1_OV_EVT 101 160 + #define MT6360_BUCK1_UV_EVT 102 102 161 /* REG 13 -> 104 ~ 111 */ 103 - #define MT6360_BUCK2_PGB_EVT (104) 104 - #define MT6360_BUCK2_OC_EVT (108) 105 - #define MT6360_BUCK2_OV_EVT (109) 106 - #define MT6360_BUCK2_UV_EVT (110) 162 + #define MT6360_BUCK2_PGB_EVT 104 163 + #define MT6360_BUCK2_OC_EVT 108 164 + #define MT6360_BUCK2_OV_EVT 109 165 + #define MT6360_BUCK2_UV_EVT 110 107 166 /* REG 14 -> 112 ~ 119 */ 108 - #define MT6360_LDO1_OC_EVT (113) 109 - #define MT6360_LDO2_OC_EVT (114) 110 - #define MT6360_LDO3_OC_EVT (115) 111 - #define MT6360_LDO5_OC_EVT (117) 112 - #define MT6360_LDO6_OC_EVT (118) 113 - #define MT6360_LDO7_OC_EVT (119) 167 + #define MT6360_LDO1_OC_EVT 113 168 + #define MT6360_LDO2_OC_EVT 114 169 + #define MT6360_LDO3_OC_EVT 115 170 + #define MT6360_LDO5_OC_EVT 117 171 + #define MT6360_LDO6_OC_EVT 118 172 + #define MT6360_LDO7_OC_EVT 119 114 173 /* REG 15 -> 120 ~ 127 */ 115 - #define MT6360_LDO1_PGB_EVT (121) 116 - #define MT6360_LDO2_PGB_EVT (122) 117 - #define MT6360_LDO3_PGB_EVT (123) 118 - #define MT6360_LDO5_PGB_EVT (125) 119 - #define MT6360_LDO6_PGB_EVT (126) 120 - #define MT6360_LDO7_PGB_EVT (127) 174 + #define MT6360_LDO1_PGB_EVT 121 175 + #define MT6360_LDO2_PGB_EVT 122 176 + #define MT6360_LDO3_PGB_EVT 123 177 + #define MT6360_LDO5_PGB_EVT 125 178 + #define MT6360_LDO6_PGB_EVT 126 179 + #define MT6360_LDO7_PGB_EVT 127 121 180 122 - static const struct regmap_irq mt6360_pmu_irqs[] = { 181 + static const struct regmap_irq mt6360_irqs[] = { 123 182 REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8), 124 183 REGMAP_IRQ_REG_LINE(MT6360_CHG_AICR_EVT, 8), 125 184 REGMAP_IRQ_REG_LINE(MT6360_CHG_MIVR_EVT, 8), ··· 267 208 REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8), 268 209 }; 269 210 270 - static int mt6360_pmu_handle_post_irq(void *irq_drv_data) 271 - { 272 - struct mt6360_pmu_data *mpd = irq_drv_data; 273 - 274 - return regmap_update_bits(mpd->regmap, 275 - MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, MT6360_IRQ_RETRIG); 276 - } 277 - 278 - static struct regmap_irq_chip mt6360_pmu_irq_chip = { 279 - .irqs = mt6360_pmu_irqs, 280 - .num_irqs = ARRAY_SIZE(mt6360_pmu_irqs), 211 + static const struct regmap_irq_chip mt6360_irq_chip = { 212 + .name = "mt6360_irqs", 213 + .irqs = mt6360_irqs, 214 + .num_irqs = ARRAY_SIZE(mt6360_irqs), 281 215 .num_regs = MT6360_PMU_IRQ_REGNUM, 282 216 .mask_base = MT6360_PMU_CHG_MASK1, 283 217 .status_base = MT6360_PMU_CHG_IRQ1, 284 218 .ack_base = MT6360_PMU_CHG_IRQ1, 285 219 .init_ack_masked = true, 286 220 .use_ack = true, 287 - .handle_post_irq = mt6360_pmu_handle_post_irq, 288 - }; 289 - 290 - static const struct regmap_config mt6360_pmu_regmap_config = { 291 - .reg_bits = 8, 292 - .val_bits = 8, 293 - .max_register = MT6360_PMU_MAXREG, 294 221 }; 295 222 296 223 static const struct resource mt6360_adc_resources[] = { ··· 310 265 DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"), 311 266 }; 312 267 313 - static const struct resource mt6360_pmic_resources[] = { 268 + static const struct resource mt6360_regulator_resources[] = { 314 269 DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"), 315 270 DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"), 316 271 DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"), ··· 323 278 DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), 324 279 DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), 325 280 DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), 326 - }; 327 - 328 - static const struct resource mt6360_ldo_resources[] = { 329 281 DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"), 330 282 DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"), 331 283 DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"), ··· 334 292 }; 335 293 336 294 static const struct mfd_cell mt6360_devs[] = { 337 - MFD_CELL_OF("mt6360_adc", mt6360_adc_resources, 338 - NULL, 0, 0, "mediatek,mt6360_adc"), 339 - MFD_CELL_OF("mt6360_chg", mt6360_chg_resources, 340 - NULL, 0, 0, "mediatek,mt6360_chg"), 341 - MFD_CELL_OF("mt6360_led", mt6360_led_resources, 342 - NULL, 0, 0, "mediatek,mt6360_led"), 343 - MFD_CELL_OF("mt6360_pmic", mt6360_pmic_resources, 344 - NULL, 0, 0, "mediatek,mt6360_pmic"), 345 - MFD_CELL_OF("mt6360_ldo", mt6360_ldo_resources, 346 - NULL, 0, 0, "mediatek,mt6360_ldo"), 347 - MFD_CELL_OF("mt6360_tcpc", NULL, 348 - NULL, 0, 0, "mediatek,mt6360_tcpc"), 295 + MFD_CELL_OF("mt6360-adc", mt6360_adc_resources, 296 + NULL, 0, 0, "mediatek,mt6360-adc"), 297 + MFD_CELL_OF("mt6360-chg", mt6360_chg_resources, 298 + NULL, 0, 0, "mediatek,mt6360-chg"), 299 + MFD_CELL_OF("mt6360-led", mt6360_led_resources, 300 + NULL, 0, 0, "mediatek,mt6360-led"), 301 + MFD_CELL_RES("mt6360-regulator", mt6360_regulator_resources), 302 + MFD_CELL_OF("mt6360-tcpc", NULL, 303 + NULL, 0, 0, "mediatek,mt6360-tcpc"), 349 304 }; 350 305 351 - static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { 352 - MT6360_PMU_SLAVEID, 353 - MT6360_PMIC_SLAVEID, 354 - MT6360_LDO_SLAVEID, 355 - MT6360_TCPC_SLAVEID, 356 - }; 357 - 358 - static int mt6360_pmu_probe(struct i2c_client *client) 306 + static int mt6360_check_vendor_info(struct mt6360_ddata *ddata) 359 307 { 360 - struct mt6360_pmu_data *mpd; 361 - unsigned int reg_data; 362 - int i, ret; 308 + u32 info; 309 + int ret; 363 310 364 - mpd = devm_kzalloc(&client->dev, sizeof(*mpd), GFP_KERNEL); 365 - if (!mpd) 366 - return -ENOMEM; 367 - 368 - mpd->dev = &client->dev; 369 - i2c_set_clientdata(client, mpd); 370 - 371 - mpd->regmap = devm_regmap_init_i2c(client, &mt6360_pmu_regmap_config); 372 - if (IS_ERR(mpd->regmap)) { 373 - dev_err(&client->dev, "Failed to register regmap\n"); 374 - return PTR_ERR(mpd->regmap); 375 - } 376 - 377 - ret = regmap_read(mpd->regmap, MT6360_PMU_DEV_INFO, &reg_data); 378 - if (ret) { 379 - dev_err(&client->dev, "Device not found\n"); 311 + ret = regmap_read(ddata->regmap, MT6360_PMU_DEV_INFO, &info); 312 + if (ret < 0) 380 313 return ret; 381 - } 382 314 383 - mpd->chip_rev = reg_data & CHIP_REV_MASK; 384 - if (mpd->chip_rev != CHIP_VEN_MT6360) { 385 - dev_err(&client->dev, "Device not supported\n"); 315 + if ((info & CHIP_VEN_MASK) != CHIP_VEN_MT6360) { 316 + dev_err(ddata->dev, "Device not supported\n"); 386 317 return -ENODEV; 387 318 } 388 319 389 - mt6360_pmu_irq_chip.irq_drv_data = mpd; 390 - ret = devm_regmap_add_irq_chip(&client->dev, mpd->regmap, client->irq, 391 - IRQF_TRIGGER_FALLING, 0, 392 - &mt6360_pmu_irq_chip, &mpd->irq_data); 320 + ddata->chip_rev = info & CHIP_REV_MASK; 321 + 322 + return 0; 323 + } 324 + 325 + static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { 326 + MT6360_TCPC_SLAVEID, 327 + MT6360_PMIC_SLAVEID, 328 + MT6360_LDO_SLAVEID, 329 + MT6360_PMU_SLAVEID, 330 + }; 331 + 332 + static int mt6360_xlate_pmicldo_addr(u8 *addr, int rw_size) 333 + { 334 + /* Address is already in encoded [5:0] */ 335 + *addr &= MT6360_ADDRESS_MASK; 336 + 337 + switch (rw_size) { 338 + case 1: 339 + *addr |= MT6360_DATA_SIZE_1_BYTE; 340 + break; 341 + case 2: 342 + *addr |= MT6360_DATA_SIZE_2_BYTES; 343 + break; 344 + case 3: 345 + *addr |= MT6360_DATA_SIZE_3_BYTES; 346 + break; 347 + case 4: 348 + *addr |= MT6360_DATA_SIZE_4_BYTES; 349 + break; 350 + default: 351 + return -EINVAL; 352 + } 353 + 354 + return 0; 355 + } 356 + 357 + static int mt6360_regmap_read(void *context, const void *reg, size_t reg_size, 358 + void *val, size_t val_size) 359 + { 360 + struct mt6360_ddata *ddata = context; 361 + u8 bank = *(u8 *)reg; 362 + u8 reg_addr = *(u8 *)(reg + 1); 363 + struct i2c_client *i2c = ddata->i2c[bank]; 364 + bool crc_needed = false; 365 + u8 *buf; 366 + int buf_len = MT6360_ALLOC_READ_SIZE(val_size); 367 + int read_size = val_size; 368 + u8 crc; 369 + int ret; 370 + 371 + if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) { 372 + crc_needed = true; 373 + ret = mt6360_xlate_pmicldo_addr(&reg_addr, val_size); 374 + if (ret < 0) 375 + return ret; 376 + read_size += MT6360_CRC_CRC8_SIZE; 377 + } 378 + 379 + buf = kzalloc(buf_len, GFP_KERNEL); 380 + if (!buf) 381 + return -ENOMEM; 382 + 383 + buf[0] = I2C_ADDR_XLATE_8BIT(i2c->addr, I2C_SMBUS_READ); 384 + buf[1] = reg_addr; 385 + 386 + ret = i2c_smbus_read_i2c_block_data(i2c, reg_addr, read_size, 387 + buf + MT6360_CRC_PREDATA_OFFSET); 388 + if (ret < 0) 389 + goto out; 390 + else if (ret != read_size) { 391 + ret = -EIO; 392 + goto out; 393 + } 394 + 395 + if (crc_needed) { 396 + crc = crc8(ddata->crc8_tbl, buf, val_size + MT6360_CRC_PREDATA_OFFSET, 0); 397 + if (crc != buf[val_size + MT6360_CRC_PREDATA_OFFSET]) { 398 + ret = -EIO; 399 + goto out; 400 + } 401 + } 402 + 403 + memcpy(val, buf + MT6360_CRC_PREDATA_OFFSET, val_size); 404 + out: 405 + kfree(buf); 406 + return (ret < 0) ? ret : 0; 407 + } 408 + 409 + static int mt6360_regmap_write(void *context, const void *val, size_t val_size) 410 + { 411 + struct mt6360_ddata *ddata = context; 412 + u8 bank = *(u8 *)val; 413 + u8 reg_addr = *(u8 *)(val + 1); 414 + struct i2c_client *i2c = ddata->i2c[bank]; 415 + bool crc_needed = false; 416 + u8 *buf; 417 + int buf_len = MT6360_ALLOC_WRITE_SIZE(val_size); 418 + int write_size = val_size - MT6360_REGMAP_REG_BYTE_SIZE; 419 + int ret; 420 + 421 + if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) { 422 + crc_needed = true; 423 + ret = mt6360_xlate_pmicldo_addr(&reg_addr, val_size - MT6360_REGMAP_REG_BYTE_SIZE); 424 + if (ret < 0) 425 + return ret; 426 + } 427 + 428 + buf = kzalloc(buf_len, GFP_KERNEL); 429 + if (!buf) 430 + return -ENOMEM; 431 + 432 + buf[0] = I2C_ADDR_XLATE_8BIT(i2c->addr, I2C_SMBUS_WRITE); 433 + buf[1] = reg_addr; 434 + memcpy(buf + MT6360_CRC_PREDATA_OFFSET, val + MT6360_REGMAP_REG_BYTE_SIZE, write_size); 435 + 436 + if (crc_needed) { 437 + buf[val_size] = crc8(ddata->crc8_tbl, buf, val_size, 0); 438 + write_size += (MT6360_CRC_CRC8_SIZE + MT6360_CRC_DUMMY_BYTE_SIZE); 439 + } 440 + 441 + ret = i2c_smbus_write_i2c_block_data(i2c, reg_addr, write_size, 442 + buf + MT6360_CRC_PREDATA_OFFSET); 443 + 444 + kfree(buf); 445 + return ret; 446 + } 447 + 448 + static const struct regmap_bus mt6360_regmap_bus = { 449 + .read = mt6360_regmap_read, 450 + .write = mt6360_regmap_write, 451 + 452 + /* Due to PMIC and LDO CRC access size limit */ 453 + .max_raw_read = 4, 454 + .max_raw_write = 4, 455 + }; 456 + 457 + static bool mt6360_is_readwrite_reg(struct device *dev, unsigned int reg) 458 + { 459 + switch (reg) { 460 + case MT6360_REG_TCPCSTART ... MT6360_REG_TCPCEND: 461 + fallthrough; 462 + case MT6360_REG_PMICSTART ... MT6360_REG_PMICEND: 463 + fallthrough; 464 + case MT6360_REG_LDOSTART ... MT6360_REG_LDOEND: 465 + fallthrough; 466 + case MT6360_REG_PMUSTART ... MT6360_REG_PMUEND: 467 + return true; 468 + } 469 + 470 + return false; 471 + } 472 + 473 + static const struct regmap_config mt6360_regmap_config = { 474 + .reg_bits = 16, 475 + .val_bits = 8, 476 + .reg_format_endian = REGMAP_ENDIAN_BIG, 477 + .max_register = MT6360_REG_PMUEND, 478 + .writeable_reg = mt6360_is_readwrite_reg, 479 + .readable_reg = mt6360_is_readwrite_reg, 480 + }; 481 + 482 + static int mt6360_probe(struct i2c_client *client) 483 + { 484 + struct mt6360_ddata *ddata; 485 + int i, ret; 486 + 487 + ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL); 488 + if (!ddata) 489 + return -ENOMEM; 490 + 491 + ddata->dev = &client->dev; 492 + i2c_set_clientdata(client, ddata); 493 + 494 + for (i = 0; i < MT6360_SLAVE_MAX - 1; i++) { 495 + ddata->i2c[i] = devm_i2c_new_dummy_device(&client->dev, 496 + client->adapter, 497 + mt6360_slave_addr[i]); 498 + if (IS_ERR(ddata->i2c[i])) { 499 + dev_err(&client->dev, 500 + "Failed to get new dummy I2C device for address 0x%x", 501 + mt6360_slave_addr[i]); 502 + return PTR_ERR(ddata->i2c[i]); 503 + } 504 + } 505 + ddata->i2c[MT6360_SLAVE_MAX - 1] = client; 506 + 507 + crc8_populate_msb(ddata->crc8_tbl, MT6360_CRC8_POLYNOMIAL); 508 + ddata->regmap = devm_regmap_init(ddata->dev, &mt6360_regmap_bus, ddata, 509 + &mt6360_regmap_config); 510 + if (IS_ERR(ddata->regmap)) { 511 + dev_err(&client->dev, "Failed to register regmap\n"); 512 + return PTR_ERR(ddata->regmap); 513 + } 514 + 515 + ret = mt6360_check_vendor_info(ddata); 516 + if (ret) 517 + return ret; 518 + 519 + ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, 520 + 0, 0, &mt6360_irq_chip, 521 + &ddata->irq_data); 393 522 if (ret) { 394 523 dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); 395 524 return ret; 396 525 } 397 526 398 - mpd->i2c[0] = client; 399 - for (i = 1; i < MT6360_SLAVE_MAX; i++) { 400 - mpd->i2c[i] = devm_i2c_new_dummy_device(&client->dev, 401 - client->adapter, 402 - mt6360_slave_addr[i]); 403 - if (IS_ERR(mpd->i2c[i])) { 404 - dev_err(&client->dev, 405 - "Failed to get new dummy I2C device for address 0x%x", 406 - mt6360_slave_addr[i]); 407 - return PTR_ERR(mpd->i2c[i]); 408 - } 409 - i2c_set_clientdata(mpd->i2c[i], mpd); 410 - } 411 - 412 527 ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 413 528 mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL, 414 - 0, regmap_irq_get_domain(mpd->irq_data)); 529 + 0, regmap_irq_get_domain(ddata->irq_data)); 415 530 if (ret) { 416 531 dev_err(&client->dev, 417 532 "Failed to register subordinate devices\n"); ··· 578 379 return 0; 579 380 } 580 381 581 - static int __maybe_unused mt6360_pmu_suspend(struct device *dev) 382 + static int __maybe_unused mt6360_suspend(struct device *dev) 582 383 { 583 384 struct i2c_client *i2c = to_i2c_client(dev); 584 385 ··· 588 389 return 0; 589 390 } 590 391 591 - static int __maybe_unused mt6360_pmu_resume(struct device *dev) 392 + static int __maybe_unused mt6360_resume(struct device *dev) 592 393 { 593 394 594 395 struct i2c_client *i2c = to_i2c_client(dev); ··· 599 400 return 0; 600 401 } 601 402 602 - static SIMPLE_DEV_PM_OPS(mt6360_pmu_pm_ops, 603 - mt6360_pmu_suspend, mt6360_pmu_resume); 403 + static SIMPLE_DEV_PM_OPS(mt6360_pm_ops, mt6360_suspend, mt6360_resume); 604 404 605 - static const struct of_device_id __maybe_unused mt6360_pmu_of_id[] = { 606 - { .compatible = "mediatek,mt6360_pmu", }, 405 + static const struct of_device_id __maybe_unused mt6360_of_id[] = { 406 + { .compatible = "mediatek,mt6360", }, 607 407 {}, 608 408 }; 609 - MODULE_DEVICE_TABLE(of, mt6360_pmu_of_id); 409 + MODULE_DEVICE_TABLE(of, mt6360_of_id); 610 410 611 - static struct i2c_driver mt6360_pmu_driver = { 411 + static struct i2c_driver mt6360_driver = { 612 412 .driver = { 613 - .name = "mt6360_pmu", 614 - .pm = &mt6360_pmu_pm_ops, 615 - .of_match_table = of_match_ptr(mt6360_pmu_of_id), 413 + .name = "mt6360", 414 + .pm = &mt6360_pm_ops, 415 + .of_match_table = of_match_ptr(mt6360_of_id), 616 416 }, 617 - .probe_new = mt6360_pmu_probe, 417 + .probe_new = mt6360_probe, 618 418 }; 619 - module_i2c_driver(mt6360_pmu_driver); 419 + module_i2c_driver(mt6360_driver); 620 420 621 421 MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>"); 622 - MODULE_DESCRIPTION("MT6360 PMU I2C Driver"); 422 + MODULE_DESCRIPTION("MT6360 I2C Driver"); 623 423 MODULE_LICENSE("GPL v2");

+16 -4

drivers/mfd/mt6397-core.c

··· 47 47 DEFINE_RES_IRQ(MT6397_IRQ_RTC), 48 48 }; 49 49 50 + static const struct resource mt6358_keys_resources[] = { 51 + DEFINE_RES_IRQ_NAMED(MT6358_IRQ_PWRKEY, "powerkey"), 52 + DEFINE_RES_IRQ_NAMED(MT6358_IRQ_HOMEKEY, "homekey"), 53 + DEFINE_RES_IRQ_NAMED(MT6358_IRQ_PWRKEY_R, "powerkey_r"), 54 + DEFINE_RES_IRQ_NAMED(MT6358_IRQ_HOMEKEY_R, "homekey_r"), 55 + }; 56 + 50 57 static const struct resource mt6323_keys_resources[] = { 51 - DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY), 52 - DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY), 58 + DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_PWRKEY, "powerkey"), 59 + DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_FCHRKEY, "homekey"), 53 60 }; 54 61 55 62 static const struct resource mt6397_keys_resources[] = { 56 - DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY), 57 - DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY), 63 + DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"), 64 + DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"), 58 65 }; 59 66 60 67 static const struct resource mt6323_pwrc_resources[] = { ··· 105 98 }, { 106 99 .name = "mt6358-sound", 107 100 .of_compatible = "mediatek,mt6358-sound" 101 + }, { 102 + .name = "mt6358-keys", 103 + .num_resources = ARRAY_SIZE(mt6358_keys_resources), 104 + .resources = mt6358_keys_resources, 105 + .of_compatible = "mediatek,mt6358-keys" 108 106 }, 109 107 }; 110 108

+1 -1

drivers/mfd/omap-usb-host.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 - /** 2 + /* 3 3 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI 4 4 * 5 5 * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com

+1 -1

drivers/mfd/omap-usb-tll.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 - /** 2 + /* 3 3 * omap-usb-tll.c - The USB TLL driver for OMAP EHCI & OHCI 4 4 * 5 5 * Copyright (C) 2012-2013 Texas Instruments Incorporated - https://www.ti.com

+6 -6

drivers/mfd/pcf50633-core.c

··· 77 77 EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits); 78 78 79 79 /* sysfs attributes */ 80 - static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr, 81 - char *buf) 80 + static ssize_t dump_regs_show(struct device *dev, 81 + struct device_attribute *attr, char *buf) 82 82 { 83 83 struct pcf50633 *pcf = dev_get_drvdata(dev); 84 84 u8 dump[16]; ··· 106 106 107 107 return buf1 - buf; 108 108 } 109 - static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL); 109 + static DEVICE_ATTR_ADMIN_RO(dump_regs); 110 110 111 - static ssize_t show_resume_reason(struct device *dev, 112 - struct device_attribute *attr, char *buf) 111 + static ssize_t resume_reason_show(struct device *dev, 112 + struct device_attribute *attr, char *buf) 113 113 { 114 114 struct pcf50633 *pcf = dev_get_drvdata(dev); 115 115 int n; ··· 123 123 124 124 return n; 125 125 } 126 - static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL); 126 + static DEVICE_ATTR_ADMIN_RO(resume_reason); 127 127 128 128 static struct attribute *pcf_sysfs_entries[] = { 129 129 &dev_attr_dump_regs.attr,

+260

drivers/mfd/qcom-pm8008.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #include <linux/bitops.h> 7 + #include <linux/i2c.h> 8 + #include <linux/interrupt.h> 9 + #include <linux/irq.h> 10 + #include <linux/irqdomain.h> 11 + #include <linux/module.h> 12 + #include <linux/of_device.h> 13 + #include <linux/of_platform.h> 14 + #include <linux/pinctrl/consumer.h> 15 + #include <linux/regmap.h> 16 + #include <linux/slab.h> 17 + 18 + #include <dt-bindings/mfd/qcom-pm8008.h> 19 + 20 + #define I2C_INTR_STATUS_BASE 0x0550 21 + #define INT_RT_STS_OFFSET 0x10 22 + #define INT_SET_TYPE_OFFSET 0x11 23 + #define INT_POL_HIGH_OFFSET 0x12 24 + #define INT_POL_LOW_OFFSET 0x13 25 + #define INT_LATCHED_CLR_OFFSET 0x14 26 + #define INT_EN_SET_OFFSET 0x15 27 + #define INT_EN_CLR_OFFSET 0x16 28 + #define INT_LATCHED_STS_OFFSET 0x18 29 + 30 + enum { 31 + PM8008_MISC, 32 + PM8008_TEMP_ALARM, 33 + PM8008_GPIO1, 34 + PM8008_GPIO2, 35 + PM8008_NUM_PERIPHS, 36 + }; 37 + 38 + #define PM8008_PERIPH_0_BASE 0x900 39 + #define PM8008_PERIPH_1_BASE 0x2400 40 + #define PM8008_PERIPH_2_BASE 0xC000 41 + #define PM8008_PERIPH_3_BASE 0xC100 42 + 43 + #define PM8008_TEMP_ALARM_ADDR PM8008_PERIPH_1_BASE 44 + #define PM8008_GPIO1_ADDR PM8008_PERIPH_2_BASE 45 + #define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE 46 + 47 + #define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET) 48 + #define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET) 49 + #define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET) 50 + #define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET) 51 + #define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET) 52 + #define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSET) 53 + #define PM8008_POLARITY_LO_BASE (PM8008_PERIPH_0_BASE | INT_POL_LOW_OFFSET) 54 + 55 + #define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE) 56 + 57 + struct pm8008_data { 58 + struct device *dev; 59 + struct regmap *regmap; 60 + int irq; 61 + struct regmap_irq_chip_data *irq_data; 62 + }; 63 + 64 + static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)}; 65 + static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)}; 66 + static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)}; 67 + static unsigned int p3_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_3_BASE)}; 68 + 69 + static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] = { 70 + REGMAP_IRQ_MAIN_REG_OFFSET(p0_offs), 71 + REGMAP_IRQ_MAIN_REG_OFFSET(p1_offs), 72 + REGMAP_IRQ_MAIN_REG_OFFSET(p2_offs), 73 + REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs), 74 + }; 75 + 76 + static unsigned int pm8008_virt_regs[] = { 77 + PM8008_POLARITY_HI_BASE, 78 + PM8008_POLARITY_LO_BASE, 79 + }; 80 + 81 + enum { 82 + POLARITY_HI_INDEX, 83 + POLARITY_LO_INDEX, 84 + PM8008_NUM_VIRT_REGS, 85 + }; 86 + 87 + static struct regmap_irq pm8008_irqs[] = { 88 + REGMAP_IRQ_REG(PM8008_IRQ_MISC_UVLO, PM8008_MISC, BIT(0)), 89 + REGMAP_IRQ_REG(PM8008_IRQ_MISC_OVLO, PM8008_MISC, BIT(1)), 90 + REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST2, PM8008_MISC, BIT(2)), 91 + REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST3, PM8008_MISC, BIT(3)), 92 + REGMAP_IRQ_REG(PM8008_IRQ_MISC_LDO_OCP, PM8008_MISC, BIT(4)), 93 + REGMAP_IRQ_REG(PM8008_IRQ_TEMP_ALARM, PM8008_TEMP_ALARM, BIT(0)), 94 + REGMAP_IRQ_REG(PM8008_IRQ_GPIO1, PM8008_GPIO1, BIT(0)), 95 + REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)), 96 + }; 97 + 98 + static int pm8008_set_type_virt(unsigned int **virt_buf, 99 + unsigned int type, unsigned long hwirq, 100 + int reg) 101 + { 102 + switch (type) { 103 + case IRQ_TYPE_EDGE_FALLING: 104 + case IRQ_TYPE_LEVEL_LOW: 105 + virt_buf[POLARITY_HI_INDEX][reg] &= ~pm8008_irqs[hwirq].mask; 106 + virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask; 107 + break; 108 + 109 + case IRQ_TYPE_EDGE_RISING: 110 + case IRQ_TYPE_LEVEL_HIGH: 111 + virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask; 112 + virt_buf[POLARITY_LO_INDEX][reg] &= ~pm8008_irqs[hwirq].mask; 113 + break; 114 + 115 + case IRQ_TYPE_EDGE_BOTH: 116 + virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask; 117 + virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask; 118 + break; 119 + 120 + default: 121 + return -EINVAL; 122 + } 123 + 124 + return 0; 125 + } 126 + 127 + static struct regmap_irq_chip pm8008_irq_chip = { 128 + .name = "pm8008_irq", 129 + .main_status = I2C_INTR_STATUS_BASE, 130 + .num_main_regs = 1, 131 + .num_virt_regs = PM8008_NUM_VIRT_REGS, 132 + .irqs = pm8008_irqs, 133 + .num_irqs = ARRAY_SIZE(pm8008_irqs), 134 + .num_regs = PM8008_NUM_PERIPHS, 135 + .not_fixed_stride = true, 136 + .sub_reg_offsets = pm8008_sub_reg_offsets, 137 + .set_type_virt = pm8008_set_type_virt, 138 + .status_base = PM8008_STATUS_BASE, 139 + .mask_base = PM8008_MASK_BASE, 140 + .unmask_base = PM8008_UNMASK_BASE, 141 + .type_base = PM8008_TYPE_BASE, 142 + .ack_base = PM8008_ACK_BASE, 143 + .virt_reg_base = pm8008_virt_regs, 144 + .num_type_reg = PM8008_NUM_PERIPHS, 145 + }; 146 + 147 + static struct regmap_config qcom_mfd_regmap_cfg = { 148 + .reg_bits = 16, 149 + .val_bits = 8, 150 + .max_register = 0xFFFF, 151 + }; 152 + 153 + static int pm8008_init(struct pm8008_data *chip) 154 + { 155 + int rc; 156 + 157 + /* 158 + * Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework 159 + * reads this as the default value instead of zero, the HW default. 160 + * This is required to enable the writing of TYPE registers in 161 + * regmap_irq_sync_unlock(). 162 + */ 163 + rc = regmap_write(chip->regmap, 164 + (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), 165 + BIT(0)); 166 + if (rc) 167 + return rc; 168 + 169 + /* Do the same for GPIO1 and GPIO2 peripherals */ 170 + rc = regmap_write(chip->regmap, 171 + (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); 172 + if (rc) 173 + return rc; 174 + 175 + rc = regmap_write(chip->regmap, 176 + (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); 177 + 178 + return rc; 179 + } 180 + 181 + static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, 182 + int client_irq) 183 + { 184 + int rc, i; 185 + struct regmap_irq_type *type; 186 + struct regmap_irq_chip_data *irq_data; 187 + 188 + rc = pm8008_init(chip); 189 + if (rc) { 190 + dev_err(chip->dev, "Init failed: %d\n", rc); 191 + return rc; 192 + } 193 + 194 + for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) { 195 + type = &pm8008_irqs[i].type; 196 + 197 + type->type_reg_offset = pm8008_irqs[i].reg_offset; 198 + type->type_rising_val = pm8008_irqs[i].mask; 199 + type->type_falling_val = pm8008_irqs[i].mask; 200 + type->type_level_high_val = 0; 201 + type->type_level_low_val = 0; 202 + 203 + if (type->type_reg_offset == PM8008_MISC) 204 + type->types_supported = IRQ_TYPE_EDGE_RISING; 205 + else 206 + type->types_supported = (IRQ_TYPE_EDGE_BOTH | 207 + IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW); 208 + } 209 + 210 + rc = devm_regmap_add_irq_chip(chip->dev, chip->regmap, client_irq, 211 + IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data); 212 + if (rc) { 213 + dev_err(chip->dev, "Failed to add IRQ chip: %d\n", rc); 214 + return rc; 215 + } 216 + 217 + return 0; 218 + } 219 + 220 + static int pm8008_probe(struct i2c_client *client) 221 + { 222 + int rc; 223 + struct pm8008_data *chip; 224 + 225 + chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 226 + if (!chip) 227 + return -ENOMEM; 228 + 229 + chip->dev = &client->dev; 230 + chip->regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg); 231 + if (!chip->regmap) 232 + return -ENODEV; 233 + 234 + i2c_set_clientdata(client, chip); 235 + 236 + if (of_property_read_bool(chip->dev->of_node, "interrupt-controller")) { 237 + rc = pm8008_probe_irq_peripherals(chip, client->irq); 238 + if (rc) 239 + dev_err(chip->dev, "Failed to probe irq periphs: %d\n", rc); 240 + } 241 + 242 + return devm_of_platform_populate(chip->dev); 243 + } 244 + 245 + static const struct of_device_id pm8008_match[] = { 246 + { .compatible = "qcom,pm8008", }, 247 + { }, 248 + }; 249 + 250 + static struct i2c_driver pm8008_mfd_driver = { 251 + .driver = { 252 + .name = "pm8008", 253 + .of_match_table = pm8008_match, 254 + }, 255 + .probe_new = pm8008_probe, 256 + }; 257 + module_i2c_driver(pm8008_mfd_driver); 258 + 259 + MODULE_LICENSE("GPL v2"); 260 + MODULE_ALIAS("i2c:qcom-pm8008");

+1 -1

drivers/mfd/rn5t618.c

··· 107 107 108 108 ret = devm_regmap_add_irq_chip(rn5t618->dev, rn5t618->regmap, 109 109 rn5t618->irq, 110 - IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 110 + IRQF_TRIGGER_LOW | IRQF_ONESHOT, 111 111 0, irq_chip, &rn5t618->irq_data); 112 112 if (ret) 113 113 dev_err(rn5t618->dev, "Failed to register IRQ chip\n");

+115

drivers/mfd/rt4831.c

··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright (c) 2021 Richtek Technology Corp. 4 + * 5 + * Author: ChiYuan Huang <cy_huang@richtek.com> 6 + */ 7 + 8 + #include <linux/gpio/consumer.h> 9 + #include <linux/i2c.h> 10 + #include <linux/kernel.h> 11 + #include <linux/mfd/core.h> 12 + #include <linux/module.h> 13 + #include <linux/regmap.h> 14 + 15 + #define RT4831_REG_REVISION 0x01 16 + #define RT4831_REG_ENABLE 0x08 17 + #define RT4831_REG_I2CPROT 0x15 18 + 19 + #define RICHTEK_VENDOR_ID 0x03 20 + #define RT4831_VID_MASK GENMASK(1, 0) 21 + #define RT4831_RESET_MASK BIT(7) 22 + #define RT4831_I2CSAFETMR_MASK BIT(0) 23 + 24 + static const struct mfd_cell rt4831_subdevs[] = { 25 + MFD_CELL_OF("rt4831-backlight", NULL, NULL, 0, 0, "richtek,rt4831-backlight"), 26 + MFD_CELL_NAME("rt4831-regulator") 27 + }; 28 + 29 + static bool rt4831_is_accessible_reg(struct device *dev, unsigned int reg) 30 + { 31 + if (reg >= RT4831_REG_REVISION && reg <= RT4831_REG_I2CPROT) 32 + return true; 33 + return false; 34 + } 35 + 36 + static const struct regmap_config rt4831_regmap_config = { 37 + .reg_bits = 8, 38 + .val_bits = 8, 39 + .max_register = RT4831_REG_I2CPROT, 40 + 41 + .readable_reg = rt4831_is_accessible_reg, 42 + .writeable_reg = rt4831_is_accessible_reg, 43 + }; 44 + 45 + static int rt4831_probe(struct i2c_client *client) 46 + { 47 + struct gpio_desc *enable_gpio; 48 + struct regmap *regmap; 49 + unsigned int chip_id; 50 + int ret; 51 + 52 + enable_gpio = devm_gpiod_get_optional(&client->dev, "enable", GPIOD_OUT_HIGH); 53 + if (IS_ERR(enable_gpio)) { 54 + dev_err(&client->dev, "Failed to get 'enable' GPIO\n"); 55 + return PTR_ERR(enable_gpio); 56 + } 57 + 58 + regmap = devm_regmap_init_i2c(client, &rt4831_regmap_config); 59 + if (IS_ERR(regmap)) { 60 + dev_err(&client->dev, "Failed to initialize regmap\n"); 61 + return PTR_ERR(regmap); 62 + } 63 + 64 + ret = regmap_read(regmap, RT4831_REG_REVISION, &chip_id); 65 + if (ret) { 66 + dev_err(&client->dev, "Failed to get H/W revision\n"); 67 + return ret; 68 + } 69 + 70 + if ((chip_id & RT4831_VID_MASK) != RICHTEK_VENDOR_ID) { 71 + dev_err(&client->dev, "Chip vendor ID 0x%02x not matched\n", chip_id); 72 + return -ENODEV; 73 + } 74 + 75 + /* 76 + * Used to prevent the abnormal shutdown. 77 + * If SCL/SDA both keep low for one second to reset HW. 78 + */ 79 + ret = regmap_update_bits(regmap, RT4831_REG_I2CPROT, RT4831_I2CSAFETMR_MASK, 80 + RT4831_I2CSAFETMR_MASK); 81 + if (ret) { 82 + dev_err(&client->dev, "Failed to enable I2C safety timer\n"); 83 + return ret; 84 + } 85 + 86 + return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, rt4831_subdevs, 87 + ARRAY_SIZE(rt4831_subdevs), NULL, 0, NULL); 88 + } 89 + 90 + static int rt4831_remove(struct i2c_client *client) 91 + { 92 + struct regmap *regmap = dev_get_regmap(&client->dev, NULL); 93 + 94 + /* Disable WLED and DSV outputs */ 95 + return regmap_update_bits(regmap, RT4831_REG_ENABLE, RT4831_RESET_MASK, RT4831_RESET_MASK); 96 + } 97 + 98 + static const struct of_device_id __maybe_unused rt4831_of_match[] = { 99 + { .compatible = "richtek,rt4831", }, 100 + {} 101 + }; 102 + MODULE_DEVICE_TABLE(of, rt4831_of_match); 103 + 104 + static struct i2c_driver rt4831_driver = { 105 + .driver = { 106 + .name = "rt4831", 107 + .of_match_table = rt4831_of_match, 108 + }, 109 + .probe_new = rt4831_probe, 110 + .remove = rt4831_remove, 111 + }; 112 + module_i2c_driver(rt4831_driver); 113 + 114 + MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>"); 115 + MODULE_LICENSE("GPL v2");

+10 -58

drivers/mfd/sec-core.c

··· 10 10 #include <linux/slab.h> 11 11 #include <linux/i2c.h> 12 12 #include <linux/of.h> 13 + #include <linux/of_device.h> 13 14 #include <linux/of_irq.h> 14 15 #include <linux/interrupt.h> 15 16 #include <linux/pm_runtime.h> ··· 94 93 { .name = "s2mpu02-regulator", }, 95 94 }; 96 95 97 - #ifdef CONFIG_OF 98 96 static const struct of_device_id sec_dt_match[] = { 99 97 { 100 98 .compatible = "samsung,s5m8767-pmic", ··· 121 121 }, 122 122 }; 123 123 MODULE_DEVICE_TABLE(of, sec_dt_match); 124 - #endif 125 124 126 125 static bool s2mpa01_volatile(struct device *dev, unsigned int reg) 127 126 { ··· 280 281 } 281 282 } 282 283 283 - #ifdef CONFIG_OF 284 284 /* 285 285 * Only the common platform data elements for s5m8767 are parsed here from the 286 286 * device tree. Other sub-modules of s5m8767 such as pmic, rtc , charger and ··· 298 300 if (!pd) 299 301 return ERR_PTR(-ENOMEM); 300 302 301 - /* 302 - * ToDo: the 'wakeup' member in the platform data is more of a linux 303 - * specfic information. Hence, there is no binding for that yet and 304 - * not parsed here. 305 - */ 306 - 307 303 pd->manual_poweroff = of_property_read_bool(dev->of_node, 308 304 "samsung,s2mps11-acokb-ground"); 309 305 pd->disable_wrstbi = of_property_read_bool(dev->of_node, 310 306 "samsung,s2mps11-wrstbi-ground"); 311 307 return pd; 312 308 } 313 - #else 314 - static struct sec_platform_data * 315 - sec_pmic_i2c_parse_dt_pdata(struct device *dev) 316 - { 317 - return NULL; 318 - } 319 - #endif 320 - 321 - static inline unsigned long sec_i2c_get_driver_data(struct i2c_client *i2c, 322 - const struct i2c_device_id *id) 323 - { 324 - #ifdef CONFIG_OF 325 - if (i2c->dev.of_node) { 326 - const struct of_device_id *match; 327 - 328 - match = of_match_node(sec_dt_match, i2c->dev.of_node); 329 - return (unsigned long)match->data; 330 - } 331 - #endif 332 - return id->driver_data; 333 - } 334 309 335 310 static int sec_pmic_probe(struct i2c_client *i2c, 336 311 const struct i2c_device_id *id) 337 312 { 338 - struct sec_platform_data *pdata = dev_get_platdata(&i2c->dev); 339 313 const struct regmap_config *regmap; 314 + struct sec_platform_data *pdata; 340 315 const struct mfd_cell *sec_devs; 341 316 struct sec_pmic_dev *sec_pmic; 342 - unsigned long device_type; 343 317 int ret, num_sec_devs; 344 318 345 319 sec_pmic = devm_kzalloc(&i2c->dev, sizeof(struct sec_pmic_dev), ··· 323 353 sec_pmic->dev = &i2c->dev; 324 354 sec_pmic->i2c = i2c; 325 355 sec_pmic->irq = i2c->irq; 326 - device_type = sec_i2c_get_driver_data(i2c, id); 327 356 328 - if (sec_pmic->dev->of_node) { 329 - pdata = sec_pmic_i2c_parse_dt_pdata(sec_pmic->dev); 330 - if (IS_ERR(pdata)) { 331 - ret = PTR_ERR(pdata); 332 - return ret; 333 - } 334 - pdata->device_type = device_type; 357 + pdata = sec_pmic_i2c_parse_dt_pdata(sec_pmic->dev); 358 + if (IS_ERR(pdata)) { 359 + ret = PTR_ERR(pdata); 360 + return ret; 335 361 } 336 - if (pdata) { 337 - sec_pmic->device_type = pdata->device_type; 338 - sec_pmic->irq_base = pdata->irq_base; 339 - sec_pmic->wakeup = pdata->wakeup; 340 - sec_pmic->pdata = pdata; 341 - } 362 + 363 + sec_pmic->device_type = (unsigned long)of_device_get_match_data(sec_pmic->dev); 364 + sec_pmic->pdata = pdata; 342 365 343 366 switch (sec_pmic->device_type) { 344 367 case S2MPA01: ··· 370 407 ret); 371 408 return ret; 372 409 } 373 - 374 - if (pdata && pdata->cfg_pmic_irq) 375 - pdata->cfg_pmic_irq(); 376 410 377 411 sec_irq_init(sec_pmic); 378 412 ··· 422 462 if (ret) 423 463 return ret; 424 464 425 - device_init_wakeup(sec_pmic->dev, sec_pmic->wakeup); 426 465 sec_pmic_configure(sec_pmic); 427 466 sec_pmic_dump_rev(sec_pmic); 428 467 ··· 492 533 493 534 static SIMPLE_DEV_PM_OPS(sec_pmic_pm_ops, sec_pmic_suspend, sec_pmic_resume); 494 535 495 - static const struct i2c_device_id sec_pmic_id[] = { 496 - { "sec_pmic", 0 }, 497 - { } 498 - }; 499 - MODULE_DEVICE_TABLE(i2c, sec_pmic_id); 500 - 501 536 static struct i2c_driver sec_pmic_driver = { 502 537 .driver = { 503 538 .name = "sec_pmic", 504 539 .pm = &sec_pmic_pm_ops, 505 - .of_match_table = of_match_ptr(sec_dt_match), 540 + .of_match_table = sec_dt_match, 506 541 }, 507 542 .probe = sec_pmic_probe, 508 543 .shutdown = sec_pmic_shutdown, 509 - .id_table = sec_pmic_id, 510 544 }; 511 545 module_i2c_driver(sec_pmic_driver); 512 546

+1 -3

drivers/mfd/sec-irq.c

··· 444 444 if (!sec_pmic->irq) { 445 445 dev_warn(sec_pmic->dev, 446 446 "No interrupt specified, no interrupts\n"); 447 - sec_pmic->irq_base = 0; 448 447 return 0; 449 448 } 450 449 ··· 481 482 ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic, 482 483 sec_pmic->irq, 483 484 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 484 - sec_pmic->irq_base, sec_irq_chip, 485 - &sec_pmic->irq_data); 485 + 0, sec_irq_chip, &sec_pmic->irq_data); 486 486 if (ret != 0) { 487 487 dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret); 488 488 return ret;

+14 -14

drivers/mfd/si476x-cmd.c

··· 390 390 } 391 391 392 392 /** 393 - * si476x_cmd_func_info() - send 'FUNC_INFO' command to the device 393 + * si476x_core_cmd_func_info() - send 'FUNC_INFO' command to the device 394 394 * @core: device to send the command to 395 395 * @info: struct si476x_func_info to fill all the information 396 396 * returned by the command ··· 424 424 EXPORT_SYMBOL_GPL(si476x_core_cmd_func_info); 425 425 426 426 /** 427 - * si476x_cmd_set_property() - send 'SET_PROPERTY' command to the device 427 + * si476x_core_cmd_set_property() - send 'SET_PROPERTY' command to the device 428 428 * @core: device to send the command to 429 429 * @property: property address 430 430 * @value: property value ··· 452 452 EXPORT_SYMBOL_GPL(si476x_core_cmd_set_property); 453 453 454 454 /** 455 - * si476x_cmd_get_property() - send 'GET_PROPERTY' command to the device 455 + * si476x_core_cmd_get_property() - send 'GET_PROPERTY' command to the device 456 456 * @core: device to send the command to 457 457 * @property: property address 458 458 * ··· 481 481 EXPORT_SYMBOL_GPL(si476x_core_cmd_get_property); 482 482 483 483 /** 484 - * si476x_cmd_dig_audio_pin_cfg() - send 'DIG_AUDIO_PIN_CFG' command to 484 + * si476x_core_cmd_dig_audio_pin_cfg() - send 'DIG_AUDIO_PIN_CFG' command to 485 485 * the device 486 486 * @core: device to send the command to 487 487 * @dclk: DCLK pin function configuration: ··· 539 539 EXPORT_SYMBOL_GPL(si476x_core_cmd_dig_audio_pin_cfg); 540 540 541 541 /** 542 - * si476x_cmd_zif_pin_cfg - send 'ZIF_PIN_CFG_COMMAND' 542 + * si476x_core_cmd_zif_pin_cfg - send 'ZIF_PIN_CFG_COMMAND' 543 543 * @core: - device to send the command to 544 544 * @iqclk: - IQCL pin function configuration: 545 545 * SI476X_IQCLK_NOOP - do not modify the behaviour ··· 588 588 EXPORT_SYMBOL_GPL(si476x_core_cmd_zif_pin_cfg); 589 589 590 590 /** 591 - * si476x_cmd_ic_link_gpo_ctl_pin_cfg - send 591 + * si476x_core_cmd_ic_link_gpo_ctl_pin_cfg - send 592 592 * 'IC_LINK_GPIO_CTL_PIN_CFG' comand to the device 593 593 * @core: - device to send the command to 594 594 * @icin: - ICIN pin function configuration: ··· 645 645 EXPORT_SYMBOL_GPL(si476x_core_cmd_ic_link_gpo_ctl_pin_cfg); 646 646 647 647 /** 648 - * si476x_cmd_ana_audio_pin_cfg - send 'ANA_AUDIO_PIN_CFG' to the 648 + * si476x_core_cmd_ana_audio_pin_cfg - send 'ANA_AUDIO_PIN_CFG' to the 649 649 * device 650 650 * @core: - device to send the command to 651 651 * @lrout: - LROUT pin function configuration: ··· 674 674 675 675 676 676 /** 677 - * si476x_cmd_intb_pin_cfg - send 'INTB_PIN_CFG' command to the device 677 + * si476x_core_cmd_intb_pin_cfg_a10 - send 'INTB_PIN_CFG' command to the device 678 678 * @core: - device to send the command to 679 679 * @intb: - INTB pin function configuration: 680 680 * SI476X_INTB_NOOP - do not modify the behaviour ··· 726 726 727 727 728 728 /** 729 - * si476x_cmd_am_rsq_status - send 'AM_RSQ_STATUS' command to the 729 + * si476x_core_cmd_am_rsq_status - send 'AM_RSQ_STATUS' command to the 730 730 * device 731 731 * @core: - device to send the command to 732 732 * @rsqargs: - pointer to a structure containing a group of sub-args 733 733 * relevant to sending the RSQ status command 734 - * @report: - all signal quality information retured by the command 734 + * @report: - all signal quality information returned by the command 735 735 * (if NULL then the output of the command is ignored) 736 736 * 737 737 * Function returns 0 on success and negative error code on failure ··· 856 856 857 857 858 858 /** 859 - * si476x_cmd_fm_seek_start - send 'FM_SEEK_START' command to the 859 + * si476x_core_cmd_fm_seek_start - send 'FM_SEEK_START' command to the 860 860 * device 861 861 * @core: - device to send the command to 862 862 * @seekup: - if set the direction of the search is 'up' ··· 884 884 EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_seek_start); 885 885 886 886 /** 887 - * si476x_cmd_fm_rds_status - send 'FM_RDS_STATUS' command to the 887 + * si476x_core_cmd_fm_rds_status - send 'FM_RDS_STATUS' command to the 888 888 * device 889 889 * @core: - device to send the command to 890 890 * @status_only: - if set the data is not removed from RDSFIFO, ··· 892 892 * rest RDS data contains the last valid info received 893 893 * @mtfifo: if set the command clears RDS receive FIFO 894 894 * @intack: if set the command clards the RDSINT bit. 895 - * @report: - all signal quality information retured by the command 895 + * @report: - all signal quality information returned by the command 896 896 * (if NULL then the output of the command is ignored) 897 897 * 898 898 * Function returns 0 on success and negative error code on failure ··· 1032 1032 1033 1033 1034 1034 /** 1035 - * si476x_cmd_am_seek_start - send 'FM_SEEK_START' command to the 1035 + * si476x_core_cmd_am_seek_start - send 'FM_SEEK_START' command to the 1036 1036 * device 1037 1037 * @core: - device to send the command to 1038 1038 * @seekup: - if set the direction of the search is 'up'

+5 -5

drivers/mfd/si476x-i2c.c

··· 350 350 mutex_unlock(&core->rds_drainer_status_lock); 351 351 } 352 352 /** 353 - * si476x_drain_rds_fifo() - RDS buffer drainer. 353 + * si476x_core_drain_rds_fifo() - RDS buffer drainer. 354 354 * @work: struct work_struct being ppassed to the function by the 355 355 * kernel. 356 356 * ··· 454 454 EXPORT_SYMBOL_GPL(si476x_core_i2c_xfer); 455 455 456 456 /** 457 - * si476x_get_status() 457 + * si476x_core_get_status() 458 458 * @core: Core device structure 459 459 * 460 460 * Get the status byte of the core device by berforming one byte I2C ··· 473 473 } 474 474 475 475 /** 476 - * si476x_get_and_signal_status() - IRQ dispatcher 476 + * si476x_core_get_and_signal_status() - IRQ dispatcher 477 477 * @core: Core device structure 478 478 * 479 479 * Dispatch the arrived interrupt request based on the value of the ··· 532 532 } 533 533 534 534 /** 535 - * si476x_firmware_version_to_revision() 535 + * si476x_core_fwver_to_revision() 536 536 * @core: Core device structure 537 537 * @func: Selects the boot function of the device: 538 538 * *_BOOTLOADER - Boot loader ··· 603 603 } 604 604 605 605 /** 606 - * si476x_get_revision_info() 606 + * si476x_core_get_revision_info() 607 607 * @core: Core device structure 608 608 * 609 609 * Get the firmware version number of the device. It is done in

+4 -4

drivers/mfd/sm501.c

··· 1190 1190 return 0; 1191 1191 } 1192 1192 1193 - /* sm501_dbg_regs 1193 + /* dbg_regs_show 1194 1194 * 1195 1195 * Debug attribute to attach to parent device to show core registers 1196 1196 */ 1197 1197 1198 - static ssize_t sm501_dbg_regs(struct device *dev, 1199 - struct device_attribute *attr, char *buff) 1198 + static ssize_t dbg_regs_show(struct device *dev, 1199 + struct device_attribute *attr, char *buff) 1200 1200 { 1201 1201 struct sm501_devdata *sm = dev_get_drvdata(dev) ; 1202 1202 unsigned int reg; ··· 1213 1213 } 1214 1214 1215 1215 1216 - static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL); 1216 + static DEVICE_ATTR_RO(dbg_regs); 1217 1217 1218 1218 /* sm501_init_reg 1219 1219 *

+1 -1

drivers/mfd/stmpe-i2c.c

··· 109 109 { "stmpe2403", STMPE2403 }, 110 110 { } 111 111 }; 112 - MODULE_DEVICE_TABLE(i2c, stmpe_id); 112 + MODULE_DEVICE_TABLE(i2c, stmpe_i2c_id); 113 113 114 114 static struct i2c_driver stmpe_i2c_driver = { 115 115 .driver = {

+5 -25

drivers/mfd/sun6i-prcm.c

··· 20 20 }; 21 21 22 22 static const struct resource sun6i_a31_ar100_clk_res[] = { 23 - { 24 - .start = 0x0, 25 - .end = 0x3, 26 - .flags = IORESOURCE_MEM, 27 - }, 23 + DEFINE_RES_MEM(0x0, 4) 28 24 }; 29 25 30 26 static const struct resource sun6i_a31_apb0_clk_res[] = { 31 - { 32 - .start = 0xc, 33 - .end = 0xf, 34 - .flags = IORESOURCE_MEM, 35 - }, 27 + DEFINE_RES_MEM(0xc, 4) 36 28 }; 37 29 38 30 static const struct resource sun6i_a31_apb0_gates_clk_res[] = { 39 - { 40 - .start = 0x28, 41 - .end = 0x2b, 42 - .flags = IORESOURCE_MEM, 43 - }, 31 + DEFINE_RES_MEM(0x28, 4) 44 32 }; 45 33 46 34 static const struct resource sun6i_a31_ir_clk_res[] = { 47 - { 48 - .start = 0x54, 49 - .end = 0x57, 50 - .flags = IORESOURCE_MEM, 51 - }, 35 + DEFINE_RES_MEM(0x54, 4) 52 36 }; 53 37 54 38 static const struct resource sun6i_a31_apb0_rstc_res[] = { 55 - { 56 - .start = 0xb0, 57 - .end = 0xb3, 58 - .flags = IORESOURCE_MEM, 59 - }, 39 + DEFINE_RES_MEM(0xb0, 4) 60 40 }; 61 41 62 42 static const struct resource sun8i_codec_analog_res[] = {

+1 -1

drivers/mfd/syscon.c

··· 108 108 syscon_config.max_register = resource_size(&res) - reg_io_width; 109 109 110 110 regmap = regmap_init_mmio(NULL, base, &syscon_config); 111 + kfree(syscon_config.name); 111 112 if (IS_ERR(regmap)) { 112 113 pr_err("regmap init failed\n"); 113 114 ret = PTR_ERR(regmap); ··· 145 144 regmap_exit(regmap); 146 145 err_regmap: 147 146 iounmap(base); 148 - kfree(syscon_config.name); 149 147 err_map: 150 148 kfree(syscon); 151 149 return ERR_PTR(ret);

+2 -10

drivers/mfd/t7l66xb.c

··· 37 37 }; 38 38 39 39 static const struct resource t7l66xb_mmc_resources[] = { 40 - { 41 - .start = 0x800, 42 - .end = 0x9ff, 43 - .flags = IORESOURCE_MEM, 44 - }, 45 - { 46 - .start = IRQ_T7L66XB_MMC, 47 - .end = IRQ_T7L66XB_MMC, 48 - .flags = IORESOURCE_IRQ, 49 - }, 40 + DEFINE_RES_MEM(0x800, 0x200), 41 + DEFINE_RES_IRQ(IRQ_T7L66XB_MMC) 50 42 }; 51 43 52 44 #define SCR_REVID 0x08 /* b Revision ID */

+3 -3

drivers/mfd/timberdale.c

··· 623 623 }, 624 624 }; 625 625 626 - static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, 627 - char *buf) 626 + static ssize_t fw_ver_show(struct device *dev, 627 + struct device_attribute *attr, char *buf) 628 628 { 629 629 struct timberdale_device *priv = dev_get_drvdata(dev); 630 630 ··· 632 632 priv->fw.config); 633 633 } 634 634 635 - static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); 635 + static DEVICE_ATTR_RO(fw_ver); 636 636 637 637 /*--------------------------------------------------------------------------*/ 638 638

+1 -5

drivers/mfd/tps80031.c

··· 35 35 #include <linux/slab.h> 36 36 37 37 static const struct resource tps80031_rtc_resources[] = { 38 - { 39 - .start = TPS80031_INT_RTC_ALARM, 40 - .end = TPS80031_INT_RTC_ALARM, 41 - .flags = IORESOURCE_IRQ, 42 - }, 38 + DEFINE_RES_IRQ(TPS80031_INT_RTC_ALARM), 43 39 }; 44 40 45 41 /* TPS80031 sub mfd devices */

+1 -1

drivers/mfd/twl-core.c

··· 485 485 EXPORT_SYMBOL(twl_i2c_read); 486 486 487 487 /** 488 - * twl_regcache_bypass - Configure the regcache bypass for the regmap associated 488 + * twl_set_regcache_bypass - Configure the regcache bypass for the regmap associated 489 489 * with the module 490 490 * @mod_no: module number 491 491 * @enable: Regcache bypass state

+1 -1

drivers/mfd/ucb1x00-assabet.c

··· 28 28 ucb1x00_adc_disable(ucb); \ 29 29 return sprintf(buf, "%d\n", val); \ 30 30 } \ 31 - static DEVICE_ATTR(name,0444,name##_show,NULL) 31 + static DEVICE_ATTR_RO(name) 32 32 33 33 UCB1X00_ATTR(vbatt, UCB_ADC_INP_AD1); 34 34 UCB1X00_ATTR(vcharger, UCB_ADC_INP_AD0);

+24 -26

drivers/mfd/wcd934x.c

··· 17 17 #include <linux/regulator/consumer.h> 18 18 #include <linux/slimbus.h> 19 19 20 + #define WCD934X_REGMAP_IRQ_REG(_irq, _off, _mask) \ 21 + [_irq] = { \ 22 + .reg_offset = (_off), \ 23 + .mask = (_mask), \ 24 + .type = { \ 25 + .type_reg_offset = (_off), \ 26 + .types_supported = IRQ_TYPE_EDGE_BOTH, \ 27 + .type_reg_mask = (_mask), \ 28 + .type_level_low_val = (_mask), \ 29 + .type_level_high_val = (_mask), \ 30 + .type_falling_val = 0, \ 31 + .type_rising_val = 0, \ 32 + }, \ 33 + } 34 + 20 35 static const struct mfd_cell wcd934x_devices[] = { 21 36 { 22 37 .name = "wcd934x-codec", ··· 45 30 }; 46 31 47 32 static const struct regmap_irq wcd934x_irqs[] = { 48 - [WCD934X_IRQ_SLIMBUS] = { 49 - .reg_offset = 0, 50 - .mask = BIT(0), 51 - .type = { 52 - .type_reg_offset = 0, 53 - .types_supported = IRQ_TYPE_EDGE_BOTH, 54 - .type_reg_mask = BIT(0), 55 - .type_level_low_val = BIT(0), 56 - .type_level_high_val = BIT(0), 57 - .type_falling_val = 0, 58 - .type_rising_val = 0, 59 - }, 60 - }, 61 - [WCD934X_IRQ_SOUNDWIRE] = { 62 - .reg_offset = 2, 63 - .mask = BIT(4), 64 - .type = { 65 - .type_reg_offset = 2, 66 - .types_supported = IRQ_TYPE_EDGE_BOTH, 67 - .type_reg_mask = BIT(4), 68 - .type_level_low_val = BIT(4), 69 - .type_level_high_val = BIT(4), 70 - .type_falling_val = 0, 71 - .type_rising_val = 0, 72 - }, 73 - }, 33 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_SLIMBUS, 0, BIT(0)), 34 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_HPH_PA_OCPL_FAULT, 0, BIT(2)), 35 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_HPH_PA_OCPR_FAULT, 0, BIT(3)), 36 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_SW_DET, 1, BIT(0)), 37 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_ELECT_INS_REM_DET, 1, BIT(1)), 38 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_BUTTON_PRESS_DET, 1, BIT(2)), 39 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET, 1, BIT(3)), 40 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 1, BIT(4)), 41 + WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_SOUNDWIRE, 2, BIT(4)), 74 42 }; 75 43 76 44 static const struct regmap_irq_chip wcd934x_regmap_irq_chip = {

+37 -213

drivers/mfd/wm831x-core.c

··· 109 109 } 110 110 111 111 /** 112 - * wm831x_reg_unlock: Unlock user keyed registers 112 + * wm831x_reg_lock: Unlock user keyed registers 113 113 * 114 114 * The WM831x has a user key preventing writes to particularly 115 115 * critical registers. This function locks those registers, ··· 622 622 .end = WM831X_DC1_DVS_CONTROL, 623 623 .flags = IORESOURCE_REG, 624 624 }, 625 - { 626 - .name = "UV", 627 - .start = WM831X_IRQ_UV_DC1, 628 - .end = WM831X_IRQ_UV_DC1, 629 - .flags = IORESOURCE_IRQ, 630 - }, 631 - { 632 - .name = "HC", 633 - .start = WM831X_IRQ_HC_DC1, 634 - .end = WM831X_IRQ_HC_DC1, 635 - .flags = IORESOURCE_IRQ, 636 - }, 625 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC1, "UV"), 626 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_HC_DC1, "HC"), 637 627 }; 638 628 639 629 ··· 633 643 .end = WM831X_DC2_DVS_CONTROL, 634 644 .flags = IORESOURCE_REG, 635 645 }, 636 - { 637 - .name = "UV", 638 - .start = WM831X_IRQ_UV_DC2, 639 - .end = WM831X_IRQ_UV_DC2, 640 - .flags = IORESOURCE_IRQ, 641 - }, 642 - { 643 - .name = "HC", 644 - .start = WM831X_IRQ_HC_DC2, 645 - .end = WM831X_IRQ_HC_DC2, 646 - .flags = IORESOURCE_IRQ, 647 - }, 646 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC2, "UV"), 647 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_HC_DC2, "HC"), 648 648 }; 649 649 650 650 static const struct resource wm831x_dcdc3_resources[] = { ··· 643 663 .end = WM831X_DC3_SLEEP_CONTROL, 644 664 .flags = IORESOURCE_REG, 645 665 }, 646 - { 647 - .name = "UV", 648 - .start = WM831X_IRQ_UV_DC3, 649 - .end = WM831X_IRQ_UV_DC3, 650 - .flags = IORESOURCE_IRQ, 651 - }, 666 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC3, "UV"), 652 667 }; 653 668 654 669 static const struct resource wm831x_dcdc4_resources[] = { ··· 652 677 .end = WM831X_DC4_SLEEP_CONTROL, 653 678 .flags = IORESOURCE_REG, 654 679 }, 655 - { 656 - .name = "UV", 657 - .start = WM831X_IRQ_UV_DC4, 658 - .end = WM831X_IRQ_UV_DC4, 659 - .flags = IORESOURCE_IRQ, 660 - }, 680 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC4, "UV"), 661 681 }; 662 682 663 683 static const struct resource wm8320_dcdc4_buck_resources[] = { ··· 661 691 .end = WM832X_DC4_SLEEP_CONTROL, 662 692 .flags = IORESOURCE_REG, 663 693 }, 664 - { 665 - .name = "UV", 666 - .start = WM831X_IRQ_UV_DC4, 667 - .end = WM831X_IRQ_UV_DC4, 668 - .flags = IORESOURCE_IRQ, 669 - }, 694 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC4, "UV"), 670 695 }; 671 696 672 697 static const struct resource wm831x_gpio_resources[] = { ··· 678 713 .end = WM831X_CURRENT_SINK_1, 679 714 .flags = IORESOURCE_REG, 680 715 }, 681 - { 682 - .start = WM831X_IRQ_CS1, 683 - .end = WM831X_IRQ_CS1, 684 - .flags = IORESOURCE_IRQ, 685 - }, 716 + DEFINE_RES_IRQ(WM831X_IRQ_CS1), 686 717 }; 687 718 688 719 static const struct resource wm831x_isink2_resources[] = { ··· 687 726 .end = WM831X_CURRENT_SINK_2, 688 727 .flags = IORESOURCE_REG, 689 728 }, 690 - { 691 - .start = WM831X_IRQ_CS2, 692 - .end = WM831X_IRQ_CS2, 693 - .flags = IORESOURCE_IRQ, 694 - }, 729 + DEFINE_RES_IRQ(WM831X_IRQ_CS2), 695 730 }; 696 731 697 732 static const struct resource wm831x_ldo1_resources[] = { ··· 696 739 .end = WM831X_LDO1_SLEEP_CONTROL, 697 740 .flags = IORESOURCE_REG, 698 741 }, 699 - { 700 - .name = "UV", 701 - .start = WM831X_IRQ_UV_LDO1, 702 - .end = WM831X_IRQ_UV_LDO1, 703 - .flags = IORESOURCE_IRQ, 704 - }, 742 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO1, "UV"), 705 743 }; 706 744 707 745 static const struct resource wm831x_ldo2_resources[] = { ··· 705 753 .end = WM831X_LDO2_SLEEP_CONTROL, 706 754 .flags = IORESOURCE_REG, 707 755 }, 708 - { 709 - .name = "UV", 710 - .start = WM831X_IRQ_UV_LDO2, 711 - .end = WM831X_IRQ_UV_LDO2, 712 - .flags = IORESOURCE_IRQ, 713 - }, 756 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO2, "UV"), 714 757 }; 715 758 716 759 static const struct resource wm831x_ldo3_resources[] = { ··· 714 767 .end = WM831X_LDO3_SLEEP_CONTROL, 715 768 .flags = IORESOURCE_REG, 716 769 }, 717 - { 718 - .name = "UV", 719 - .start = WM831X_IRQ_UV_LDO3, 720 - .end = WM831X_IRQ_UV_LDO3, 721 - .flags = IORESOURCE_IRQ, 722 - }, 770 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO3, "UV"), 723 771 }; 724 772 725 773 static const struct resource wm831x_ldo4_resources[] = { ··· 723 781 .end = WM831X_LDO4_SLEEP_CONTROL, 724 782 .flags = IORESOURCE_REG, 725 783 }, 726 - { 727 - .name = "UV", 728 - .start = WM831X_IRQ_UV_LDO4, 729 - .end = WM831X_IRQ_UV_LDO4, 730 - .flags = IORESOURCE_IRQ, 731 - }, 784 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO4, "UV"), 732 785 }; 733 786 734 787 static const struct resource wm831x_ldo5_resources[] = { ··· 732 795 .end = WM831X_LDO5_SLEEP_CONTROL, 733 796 .flags = IORESOURCE_REG, 734 797 }, 735 - { 736 - .name = "UV", 737 - .start = WM831X_IRQ_UV_LDO5, 738 - .end = WM831X_IRQ_UV_LDO5, 739 - .flags = IORESOURCE_IRQ, 740 - }, 798 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO5, "UV"), 741 799 }; 742 800 743 801 static const struct resource wm831x_ldo6_resources[] = { ··· 741 809 .end = WM831X_LDO6_SLEEP_CONTROL, 742 810 .flags = IORESOURCE_REG, 743 811 }, 744 - { 745 - .name = "UV", 746 - .start = WM831X_IRQ_UV_LDO6, 747 - .end = WM831X_IRQ_UV_LDO6, 748 - .flags = IORESOURCE_IRQ, 749 - }, 812 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO6, "UV"), 750 813 }; 751 814 752 815 static const struct resource wm831x_ldo7_resources[] = { ··· 750 823 .end = WM831X_LDO7_SLEEP_CONTROL, 751 824 .flags = IORESOURCE_REG, 752 825 }, 753 - { 754 - .name = "UV", 755 - .start = WM831X_IRQ_UV_LDO7, 756 - .end = WM831X_IRQ_UV_LDO7, 757 - .flags = IORESOURCE_IRQ, 758 - }, 826 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO7, "UV"), 759 827 }; 760 828 761 829 static const struct resource wm831x_ldo8_resources[] = { ··· 759 837 .end = WM831X_LDO8_SLEEP_CONTROL, 760 838 .flags = IORESOURCE_REG, 761 839 }, 762 - { 763 - .name = "UV", 764 - .start = WM831X_IRQ_UV_LDO8, 765 - .end = WM831X_IRQ_UV_LDO8, 766 - .flags = IORESOURCE_IRQ, 767 - }, 840 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO8, "UV"), 768 841 }; 769 842 770 843 static const struct resource wm831x_ldo9_resources[] = { ··· 768 851 .end = WM831X_LDO9_SLEEP_CONTROL, 769 852 .flags = IORESOURCE_REG, 770 853 }, 771 - { 772 - .name = "UV", 773 - .start = WM831X_IRQ_UV_LDO9, 774 - .end = WM831X_IRQ_UV_LDO9, 775 - .flags = IORESOURCE_IRQ, 776 - }, 854 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO9, "UV"), 777 855 }; 778 856 779 857 static const struct resource wm831x_ldo10_resources[] = { ··· 777 865 .end = WM831X_LDO10_SLEEP_CONTROL, 778 866 .flags = IORESOURCE_REG, 779 867 }, 780 - { 781 - .name = "UV", 782 - .start = WM831X_IRQ_UV_LDO10, 783 - .end = WM831X_IRQ_UV_LDO10, 784 - .flags = IORESOURCE_IRQ, 785 - }, 868 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO10, "UV"), 786 869 }; 787 870 788 871 static const struct resource wm831x_ldo11_resources[] = { ··· 789 882 }; 790 883 791 884 static const struct resource wm831x_on_resources[] = { 792 - { 793 - .start = WM831X_IRQ_ON, 794 - .end = WM831X_IRQ_ON, 795 - .flags = IORESOURCE_IRQ, 796 - }, 885 + DEFINE_RES_IRQ(WM831X_IRQ_ON), 797 886 }; 798 887 799 888 800 889 static const struct resource wm831x_power_resources[] = { 801 - { 802 - .name = "SYSLO", 803 - .start = WM831X_IRQ_PPM_SYSLO, 804 - .end = WM831X_IRQ_PPM_SYSLO, 805 - .flags = IORESOURCE_IRQ, 806 - }, 807 - { 808 - .name = "PWR SRC", 809 - .start = WM831X_IRQ_PPM_PWR_SRC, 810 - .end = WM831X_IRQ_PPM_PWR_SRC, 811 - .flags = IORESOURCE_IRQ, 812 - }, 813 - { 814 - .name = "USB CURR", 815 - .start = WM831X_IRQ_PPM_USB_CURR, 816 - .end = WM831X_IRQ_PPM_USB_CURR, 817 - .flags = IORESOURCE_IRQ, 818 - }, 819 - { 820 - .name = "BATT HOT", 821 - .start = WM831X_IRQ_CHG_BATT_HOT, 822 - .end = WM831X_IRQ_CHG_BATT_HOT, 823 - .flags = IORESOURCE_IRQ, 824 - }, 825 - { 826 - .name = "BATT COLD", 827 - .start = WM831X_IRQ_CHG_BATT_COLD, 828 - .end = WM831X_IRQ_CHG_BATT_COLD, 829 - .flags = IORESOURCE_IRQ, 830 - }, 831 - { 832 - .name = "BATT FAIL", 833 - .start = WM831X_IRQ_CHG_BATT_FAIL, 834 - .end = WM831X_IRQ_CHG_BATT_FAIL, 835 - .flags = IORESOURCE_IRQ, 836 - }, 837 - { 838 - .name = "OV", 839 - .start = WM831X_IRQ_CHG_OV, 840 - .end = WM831X_IRQ_CHG_OV, 841 - .flags = IORESOURCE_IRQ, 842 - }, 843 - { 844 - .name = "END", 845 - .start = WM831X_IRQ_CHG_END, 846 - .end = WM831X_IRQ_CHG_END, 847 - .flags = IORESOURCE_IRQ, 848 - }, 849 - { 850 - .name = "TO", 851 - .start = WM831X_IRQ_CHG_TO, 852 - .end = WM831X_IRQ_CHG_TO, 853 - .flags = IORESOURCE_IRQ, 854 - }, 855 - { 856 - .name = "MODE", 857 - .start = WM831X_IRQ_CHG_MODE, 858 - .end = WM831X_IRQ_CHG_MODE, 859 - .flags = IORESOURCE_IRQ, 860 - }, 861 - { 862 - .name = "START", 863 - .start = WM831X_IRQ_CHG_START, 864 - .end = WM831X_IRQ_CHG_START, 865 - .flags = IORESOURCE_IRQ, 866 - }, 890 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_PPM_SYSLO, "SYSLO"), 891 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_PPM_PWR_SRC, "PWR SRC"), 892 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_PPM_USB_CURR, "USB CURR"), 893 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_BATT_HOT, "BATT HOT"), 894 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_BATT_COLD, "BATT COLD"), 895 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_BATT_FAIL, "BATT FAIL"), 896 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_OV, "OV"), 897 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_END, "END"), 898 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_TO, "TO"), 899 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_MODE, "MODE"), 900 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_START, "START"), 867 901 }; 868 902 869 903 static const struct resource wm831x_rtc_resources[] = { 870 - { 871 - .name = "PER", 872 - .start = WM831X_IRQ_RTC_PER, 873 - .end = WM831X_IRQ_RTC_PER, 874 - .flags = IORESOURCE_IRQ, 875 - }, 876 - { 877 - .name = "ALM", 878 - .start = WM831X_IRQ_RTC_ALM, 879 - .end = WM831X_IRQ_RTC_ALM, 880 - .flags = IORESOURCE_IRQ, 881 - }, 904 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_RTC_PER, "PER"), 905 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_RTC_ALM, "ALM"), 882 906 }; 883 907 884 908 static const struct resource wm831x_status1_resources[] = { ··· 829 991 }; 830 992 831 993 static const struct resource wm831x_touch_resources[] = { 832 - { 833 - .name = "TCHPD", 834 - .start = WM831X_IRQ_TCHPD, 835 - .end = WM831X_IRQ_TCHPD, 836 - .flags = IORESOURCE_IRQ, 837 - }, 838 - { 839 - .name = "TCHDATA", 840 - .start = WM831X_IRQ_TCHDATA, 841 - .end = WM831X_IRQ_TCHDATA, 842 - .flags = IORESOURCE_IRQ, 843 - }, 994 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_TCHPD, "TCHPD"), 995 + DEFINE_RES_IRQ_NAMED(WM831X_IRQ_TCHDATA, "TCHDATA"), 844 996 }; 845 997 846 998 static const struct resource wm831x_wdt_resources[] = { 847 - { 848 - .start = WM831X_IRQ_WDOG_TO, 849 - .end = WM831X_IRQ_WDOG_TO, 850 - .flags = IORESOURCE_IRQ, 851 - }, 999 + DEFINE_RES_IRQ(WM831X_IRQ_WDOG_TO), 852 1000 }; 853 1001 854 1002 static const struct mfd_cell wm8310_devs[] = {

+3 -3

drivers/mfd/wm831x-otp.c

··· 38 38 return 0; 39 39 } 40 40 41 - static ssize_t wm831x_unique_id_show(struct device *dev, 42 - struct device_attribute *attr, char *buf) 41 + static ssize_t unique_id_show(struct device *dev, 42 + struct device_attribute *attr, char *buf) 43 43 { 44 44 struct wm831x *wm831x = dev_get_drvdata(dev); 45 45 int rval; ··· 52 52 return sprintf(buf, "%*phN\n", WM831X_UNIQUE_ID_LEN, id); 53 53 } 54 54 55 - static DEVICE_ATTR(unique_id, 0444, wm831x_unique_id_show, NULL); 55 + static DEVICE_ATTR_RO(unique_id); 56 56 57 57 int wm831x_otp_init(struct wm831x *wm831x) 58 58 {

+11

drivers/regulator/lp87565-regulator.c

··· 11 11 12 12 #include <linux/mfd/lp87565.h> 13 13 14 + enum LP87565_regulator_id { 15 + /* BUCK's */ 16 + LP87565_BUCK_0, 17 + LP87565_BUCK_1, 18 + LP87565_BUCK_2, 19 + LP87565_BUCK_3, 20 + LP87565_BUCK_10, 21 + LP87565_BUCK_23, 22 + LP87565_BUCK_3210, 23 + }; 24 + 14 25 #define LP87565_REGULATOR(_name, _id, _of, _ops, _n, _vr, _vm, \ 15 26 _er, _em, _ev, _delay, _lr, _cr) \ 16 27 [_id] = { \

+23

include/dt-bindings/leds/rt4831-backlight.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * This header provides constants for rt4831 backlight bindings. 4 + * 5 + * Copyright (C) 2020, Richtek Technology Corp. 6 + * Author: ChiYuan Huang <cy_huang@richtek.com> 7 + */ 8 + 9 + #ifndef _DT_BINDINGS_RT4831_BACKLIGHT_H 10 + #define _DT_BINDINGS_RT4831_BACKLIGHT_H 11 + 12 + #define RT4831_BLOVPLVL_17V 0 13 + #define RT4831_BLOVPLVL_21V 1 14 + #define RT4831_BLOVPLVL_25V 2 15 + #define RT4831_BLOVPLVL_29V 3 16 + 17 + #define RT4831_BLED_CH1EN (1 << 0) 18 + #define RT4831_BLED_CH2EN (1 << 1) 19 + #define RT4831_BLED_CH3EN (1 << 2) 20 + #define RT4831_BLED_CH4EN (1 << 3) 21 + #define RT4831_BLED_ALLCHEN ((1 << 4) - 1) 22 + 23 + #endif /* _DT_BINDINGS_RT4831_BACKLIGHT_H */

+19

include/dt-bindings/mfd/qcom-pm8008.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (c) 2021 The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef __DT_BINDINGS_MFD_QCOM_PM8008_H 7 + #define __DT_BINDINGS_MFD_QCOM_PM8008_H 8 + 9 + /* PM8008 IRQ numbers */ 10 + #define PM8008_IRQ_MISC_UVLO 0 11 + #define PM8008_IRQ_MISC_OVLO 1 12 + #define PM8008_IRQ_MISC_OTST2 2 13 + #define PM8008_IRQ_MISC_OTST3 3 14 + #define PM8008_IRQ_MISC_LDO_OCP 4 15 + #define PM8008_IRQ_TEMP_ALARM 5 16 + #define PM8008_IRQ_GPIO1 6 17 + #define PM8008_IRQ_GPIO2 7 18 + 19 + #endif

+1 -1

include/linux/mfd/hi655x-pmic.h

··· 2 2 /* 3 3 * Device driver for regulators in hi655x IC 4 4 * 5 - * Copyright (c) 2016 Hisilicon. 5 + * Copyright (c) 2016 HiSilicon Ltd. 6 6 * 7 7 * Authors: 8 8 * Chen Feng <puck.chen@hisilicon.com>

+13 -23

include/linux/mfd/lp87565.h

··· 222 222 #define LP87565_GPIO2_SEL BIT(1) 223 223 #define LP87565_GPIO1_SEL BIT(0) 224 224 225 - #define LP87565_GOIO3_OD BIT(6) 226 - #define LP87565_GOIO2_OD BIT(5) 227 - #define LP87565_GOIO1_OD BIT(4) 228 - #define LP87565_GOIO3_DIR BIT(2) 229 - #define LP87565_GOIO2_DIR BIT(1) 230 - #define LP87565_GOIO1_DIR BIT(0) 225 + #define LP87565_GPIO3_OD BIT(6) 226 + #define LP87565_GPIO2_OD BIT(5) 227 + #define LP87565_GPIO1_OD BIT(4) 228 + #define LP87565_GPIO3_DIR BIT(2) 229 + #define LP87565_GPIO2_DIR BIT(1) 230 + #define LP87565_GPIO1_DIR BIT(0) 231 231 232 - #define LP87565_GOIO3_IN BIT(2) 233 - #define LP87565_GOIO2_IN BIT(1) 234 - #define LP87565_GOIO1_IN BIT(0) 232 + #define LP87565_GPIO3_IN BIT(2) 233 + #define LP87565_GPIO2_IN BIT(1) 234 + #define LP87565_GPIO1_IN BIT(0) 235 235 236 - #define LP87565_GOIO3_OUT BIT(2) 237 - #define LP87565_GOIO2_OUT BIT(1) 238 - #define LP87565_GOIO1_OUT BIT(0) 239 - 240 - enum LP87565_regulator_id { 241 - /* BUCK's */ 242 - LP87565_BUCK_0, 243 - LP87565_BUCK_1, 244 - LP87565_BUCK_2, 245 - LP87565_BUCK_3, 246 - LP87565_BUCK_10, 247 - LP87565_BUCK_23, 248 - LP87565_BUCK_3210, 249 - }; 236 + #define LP87565_GPIO3_OUT BIT(2) 237 + #define LP87565_GPIO2_OUT BIT(1) 238 + #define LP87565_GPIO1_OUT BIT(0) 250 239 251 240 /** 252 241 * struct LP87565 - state holder for the LP87565 driver ··· 252 263 u8 rev; 253 264 u8 dev_type; 254 265 struct regmap *regmap; 266 + struct gpio_desc *reset_gpio; 255 267 }; 256 268 #endif /* __LINUX_MFD_LP87565_H */

+2

include/linux/mfd/mt6358/registers.h

··· 8 8 9 9 /* PMIC Registers */ 10 10 #define MT6358_SWCID 0xa 11 + #define MT6358_TOPSTATUS 0x28 12 + #define MT6358_TOP_RST_MISC 0x14c 11 13 #define MT6358_MISC_TOP_INT_CON0 0x188 12 14 #define MT6358_MISC_TOP_INT_STATUS0 0x194 13 15 #define MT6358_TOP_INT_STATUS0 0x19e

-240

include/linux/mfd/mt6360.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * Copyright (c) 2020 MediaTek Inc. 4 - */ 5 - 6 - #ifndef __MT6360_H__ 7 - #define __MT6360_H__ 8 - 9 - #include <linux/regmap.h> 10 - 11 - enum { 12 - MT6360_SLAVE_PMU = 0, 13 - MT6360_SLAVE_PMIC, 14 - MT6360_SLAVE_LDO, 15 - MT6360_SLAVE_TCPC, 16 - MT6360_SLAVE_MAX, 17 - }; 18 - 19 - #define MT6360_PMU_SLAVEID (0x34) 20 - #define MT6360_PMIC_SLAVEID (0x1A) 21 - #define MT6360_LDO_SLAVEID (0x64) 22 - #define MT6360_TCPC_SLAVEID (0x4E) 23 - 24 - struct mt6360_pmu_data { 25 - struct i2c_client *i2c[MT6360_SLAVE_MAX]; 26 - struct device *dev; 27 - struct regmap *regmap; 28 - struct regmap_irq_chip_data *irq_data; 29 - unsigned int chip_rev; 30 - }; 31 - 32 - /* PMU register defininition */ 33 - #define MT6360_PMU_DEV_INFO (0x00) 34 - #define MT6360_PMU_CORE_CTRL1 (0x01) 35 - #define MT6360_PMU_RST1 (0x02) 36 - #define MT6360_PMU_CRCEN (0x03) 37 - #define MT6360_PMU_RST_PAS_CODE1 (0x04) 38 - #define MT6360_PMU_RST_PAS_CODE2 (0x05) 39 - #define MT6360_PMU_CORE_CTRL2 (0x06) 40 - #define MT6360_PMU_TM_PAS_CODE1 (0x07) 41 - #define MT6360_PMU_TM_PAS_CODE2 (0x08) 42 - #define MT6360_PMU_TM_PAS_CODE3 (0x09) 43 - #define MT6360_PMU_TM_PAS_CODE4 (0x0A) 44 - #define MT6360_PMU_IRQ_IND (0x0B) 45 - #define MT6360_PMU_IRQ_MASK (0x0C) 46 - #define MT6360_PMU_IRQ_SET (0x0D) 47 - #define MT6360_PMU_SHDN_CTRL (0x0E) 48 - #define MT6360_PMU_TM_INF (0x0F) 49 - #define MT6360_PMU_I2C_CTRL (0x10) 50 - #define MT6360_PMU_CHG_CTRL1 (0x11) 51 - #define MT6360_PMU_CHG_CTRL2 (0x12) 52 - #define MT6360_PMU_CHG_CTRL3 (0x13) 53 - #define MT6360_PMU_CHG_CTRL4 (0x14) 54 - #define MT6360_PMU_CHG_CTRL5 (0x15) 55 - #define MT6360_PMU_CHG_CTRL6 (0x16) 56 - #define MT6360_PMU_CHG_CTRL7 (0x17) 57 - #define MT6360_PMU_CHG_CTRL8 (0x18) 58 - #define MT6360_PMU_CHG_CTRL9 (0x19) 59 - #define MT6360_PMU_CHG_CTRL10 (0x1A) 60 - #define MT6360_PMU_CHG_CTRL11 (0x1B) 61 - #define MT6360_PMU_CHG_CTRL12 (0x1C) 62 - #define MT6360_PMU_CHG_CTRL13 (0x1D) 63 - #define MT6360_PMU_CHG_CTRL14 (0x1E) 64 - #define MT6360_PMU_CHG_CTRL15 (0x1F) 65 - #define MT6360_PMU_CHG_CTRL16 (0x20) 66 - #define MT6360_PMU_CHG_AICC_RESULT (0x21) 67 - #define MT6360_PMU_DEVICE_TYPE (0x22) 68 - #define MT6360_PMU_QC_CONTROL1 (0x23) 69 - #define MT6360_PMU_QC_CONTROL2 (0x24) 70 - #define MT6360_PMU_QC30_CONTROL1 (0x25) 71 - #define MT6360_PMU_QC30_CONTROL2 (0x26) 72 - #define MT6360_PMU_USB_STATUS1 (0x27) 73 - #define MT6360_PMU_QC_STATUS1 (0x28) 74 - #define MT6360_PMU_QC_STATUS2 (0x29) 75 - #define MT6360_PMU_CHG_PUMP (0x2A) 76 - #define MT6360_PMU_CHG_CTRL17 (0x2B) 77 - #define MT6360_PMU_CHG_CTRL18 (0x2C) 78 - #define MT6360_PMU_CHRDET_CTRL1 (0x2D) 79 - #define MT6360_PMU_CHRDET_CTRL2 (0x2E) 80 - #define MT6360_PMU_DPDN_CTRL (0x2F) 81 - #define MT6360_PMU_CHG_HIDDEN_CTRL1 (0x30) 82 - #define MT6360_PMU_CHG_HIDDEN_CTRL2 (0x31) 83 - #define MT6360_PMU_CHG_HIDDEN_CTRL3 (0x32) 84 - #define MT6360_PMU_CHG_HIDDEN_CTRL4 (0x33) 85 - #define MT6360_PMU_CHG_HIDDEN_CTRL5 (0x34) 86 - #define MT6360_PMU_CHG_HIDDEN_CTRL6 (0x35) 87 - #define MT6360_PMU_CHG_HIDDEN_CTRL7 (0x36) 88 - #define MT6360_PMU_CHG_HIDDEN_CTRL8 (0x37) 89 - #define MT6360_PMU_CHG_HIDDEN_CTRL9 (0x38) 90 - #define MT6360_PMU_CHG_HIDDEN_CTRL10 (0x39) 91 - #define MT6360_PMU_CHG_HIDDEN_CTRL11 (0x3A) 92 - #define MT6360_PMU_CHG_HIDDEN_CTRL12 (0x3B) 93 - #define MT6360_PMU_CHG_HIDDEN_CTRL13 (0x3C) 94 - #define MT6360_PMU_CHG_HIDDEN_CTRL14 (0x3D) 95 - #define MT6360_PMU_CHG_HIDDEN_CTRL15 (0x3E) 96 - #define MT6360_PMU_CHG_HIDDEN_CTRL16 (0x3F) 97 - #define MT6360_PMU_CHG_HIDDEN_CTRL17 (0x40) 98 - #define MT6360_PMU_CHG_HIDDEN_CTRL18 (0x41) 99 - #define MT6360_PMU_CHG_HIDDEN_CTRL19 (0x42) 100 - #define MT6360_PMU_CHG_HIDDEN_CTRL20 (0x43) 101 - #define MT6360_PMU_CHG_HIDDEN_CTRL21 (0x44) 102 - #define MT6360_PMU_CHG_HIDDEN_CTRL22 (0x45) 103 - #define MT6360_PMU_CHG_HIDDEN_CTRL23 (0x46) 104 - #define MT6360_PMU_CHG_HIDDEN_CTRL24 (0x47) 105 - #define MT6360_PMU_CHG_HIDDEN_CTRL25 (0x48) 106 - #define MT6360_PMU_BC12_CTRL (0x49) 107 - #define MT6360_PMU_CHG_STAT (0x4A) 108 - #define MT6360_PMU_RESV1 (0x4B) 109 - #define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH (0x4E) 110 - #define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL (0x4F) 111 - #define MT6360_PMU_TYPEC_OTP_HYST_TH (0x50) 112 - #define MT6360_PMU_TYPEC_OTP_CTRL (0x51) 113 - #define MT6360_PMU_ADC_BAT_DATA_H (0x52) 114 - #define MT6360_PMU_ADC_BAT_DATA_L (0x53) 115 - #define MT6360_PMU_IMID_BACKBST_ON (0x54) 116 - #define MT6360_PMU_IMID_BACKBST_OFF (0x55) 117 - #define MT6360_PMU_ADC_CONFIG (0x56) 118 - #define MT6360_PMU_ADC_EN2 (0x57) 119 - #define MT6360_PMU_ADC_IDLE_T (0x58) 120 - #define MT6360_PMU_ADC_RPT_1 (0x5A) 121 - #define MT6360_PMU_ADC_RPT_2 (0x5B) 122 - #define MT6360_PMU_ADC_RPT_3 (0x5C) 123 - #define MT6360_PMU_ADC_RPT_ORG1 (0x5D) 124 - #define MT6360_PMU_ADC_RPT_ORG2 (0x5E) 125 - #define MT6360_PMU_BAT_OVP_TH_SEL_CODEH (0x5F) 126 - #define MT6360_PMU_BAT_OVP_TH_SEL_CODEL (0x60) 127 - #define MT6360_PMU_CHG_CTRL19 (0x61) 128 - #define MT6360_PMU_VDDASUPPLY (0x62) 129 - #define MT6360_PMU_BC12_MANUAL (0x63) 130 - #define MT6360_PMU_CHGDET_FUNC (0x64) 131 - #define MT6360_PMU_FOD_CTRL (0x65) 132 - #define MT6360_PMU_CHG_CTRL20 (0x66) 133 - #define MT6360_PMU_CHG_HIDDEN_CTRL26 (0x67) 134 - #define MT6360_PMU_CHG_HIDDEN_CTRL27 (0x68) 135 - #define MT6360_PMU_RESV2 (0x69) 136 - #define MT6360_PMU_USBID_CTRL1 (0x6D) 137 - #define MT6360_PMU_USBID_CTRL2 (0x6E) 138 - #define MT6360_PMU_USBID_CTRL3 (0x6F) 139 - #define MT6360_PMU_FLED_CFG (0x70) 140 - #define MT6360_PMU_RESV3 (0x71) 141 - #define MT6360_PMU_FLED1_CTRL (0x72) 142 - #define MT6360_PMU_FLED_STRB_CTRL (0x73) 143 - #define MT6360_PMU_FLED1_STRB_CTRL2 (0x74) 144 - #define MT6360_PMU_FLED1_TOR_CTRL (0x75) 145 - #define MT6360_PMU_FLED2_CTRL (0x76) 146 - #define MT6360_PMU_RESV4 (0x77) 147 - #define MT6360_PMU_FLED2_STRB_CTRL2 (0x78) 148 - #define MT6360_PMU_FLED2_TOR_CTRL (0x79) 149 - #define MT6360_PMU_FLED_VMIDTRK_CTRL1 (0x7A) 150 - #define MT6360_PMU_FLED_VMID_RTM (0x7B) 151 - #define MT6360_PMU_FLED_VMIDTRK_CTRL2 (0x7C) 152 - #define MT6360_PMU_FLED_PWSEL (0x7D) 153 - #define MT6360_PMU_FLED_EN (0x7E) 154 - #define MT6360_PMU_FLED_Hidden1 (0x7F) 155 - #define MT6360_PMU_RGB_EN (0x80) 156 - #define MT6360_PMU_RGB1_ISNK (0x81) 157 - #define MT6360_PMU_RGB2_ISNK (0x82) 158 - #define MT6360_PMU_RGB3_ISNK (0x83) 159 - #define MT6360_PMU_RGB_ML_ISNK (0x84) 160 - #define MT6360_PMU_RGB1_DIM (0x85) 161 - #define MT6360_PMU_RGB2_DIM (0x86) 162 - #define MT6360_PMU_RGB3_DIM (0x87) 163 - #define MT6360_PMU_RESV5 (0x88) 164 - #define MT6360_PMU_RGB12_Freq (0x89) 165 - #define MT6360_PMU_RGB34_Freq (0x8A) 166 - #define MT6360_PMU_RGB1_Tr (0x8B) 167 - #define MT6360_PMU_RGB1_Tf (0x8C) 168 - #define MT6360_PMU_RGB1_TON_TOFF (0x8D) 169 - #define MT6360_PMU_RGB2_Tr (0x8E) 170 - #define MT6360_PMU_RGB2_Tf (0x8F) 171 - #define MT6360_PMU_RGB2_TON_TOFF (0x90) 172 - #define MT6360_PMU_RGB3_Tr (0x91) 173 - #define MT6360_PMU_RGB3_Tf (0x92) 174 - #define MT6360_PMU_RGB3_TON_TOFF (0x93) 175 - #define MT6360_PMU_RGB_Hidden_CTRL1 (0x94) 176 - #define MT6360_PMU_RGB_Hidden_CTRL2 (0x95) 177 - #define MT6360_PMU_RESV6 (0x97) 178 - #define MT6360_PMU_SPARE1 (0x9A) 179 - #define MT6360_PMU_SPARE2 (0xA0) 180 - #define MT6360_PMU_SPARE3 (0xB0) 181 - #define MT6360_PMU_SPARE4 (0xC0) 182 - #define MT6360_PMU_CHG_IRQ1 (0xD0) 183 - #define MT6360_PMU_CHG_IRQ2 (0xD1) 184 - #define MT6360_PMU_CHG_IRQ3 (0xD2) 185 - #define MT6360_PMU_CHG_IRQ4 (0xD3) 186 - #define MT6360_PMU_CHG_IRQ5 (0xD4) 187 - #define MT6360_PMU_CHG_IRQ6 (0xD5) 188 - #define MT6360_PMU_QC_IRQ (0xD6) 189 - #define MT6360_PMU_FOD_IRQ (0xD7) 190 - #define MT6360_PMU_BASE_IRQ (0xD8) 191 - #define MT6360_PMU_FLED_IRQ1 (0xD9) 192 - #define MT6360_PMU_FLED_IRQ2 (0xDA) 193 - #define MT6360_PMU_RGB_IRQ (0xDB) 194 - #define MT6360_PMU_BUCK1_IRQ (0xDC) 195 - #define MT6360_PMU_BUCK2_IRQ (0xDD) 196 - #define MT6360_PMU_LDO_IRQ1 (0xDE) 197 - #define MT6360_PMU_LDO_IRQ2 (0xDF) 198 - #define MT6360_PMU_CHG_STAT1 (0xE0) 199 - #define MT6360_PMU_CHG_STAT2 (0xE1) 200 - #define MT6360_PMU_CHG_STAT3 (0xE2) 201 - #define MT6360_PMU_CHG_STAT4 (0xE3) 202 - #define MT6360_PMU_CHG_STAT5 (0xE4) 203 - #define MT6360_PMU_CHG_STAT6 (0xE5) 204 - #define MT6360_PMU_QC_STAT (0xE6) 205 - #define MT6360_PMU_FOD_STAT (0xE7) 206 - #define MT6360_PMU_BASE_STAT (0xE8) 207 - #define MT6360_PMU_FLED_STAT1 (0xE9) 208 - #define MT6360_PMU_FLED_STAT2 (0xEA) 209 - #define MT6360_PMU_RGB_STAT (0xEB) 210 - #define MT6360_PMU_BUCK1_STAT (0xEC) 211 - #define MT6360_PMU_BUCK2_STAT (0xED) 212 - #define MT6360_PMU_LDO_STAT1 (0xEE) 213 - #define MT6360_PMU_LDO_STAT2 (0xEF) 214 - #define MT6360_PMU_CHG_MASK1 (0xF0) 215 - #define MT6360_PMU_CHG_MASK2 (0xF1) 216 - #define MT6360_PMU_CHG_MASK3 (0xF2) 217 - #define MT6360_PMU_CHG_MASK4 (0xF3) 218 - #define MT6360_PMU_CHG_MASK5 (0xF4) 219 - #define MT6360_PMU_CHG_MASK6 (0xF5) 220 - #define MT6360_PMU_QC_MASK (0xF6) 221 - #define MT6360_PMU_FOD_MASK (0xF7) 222 - #define MT6360_PMU_BASE_MASK (0xF8) 223 - #define MT6360_PMU_FLED_MASK1 (0xF9) 224 - #define MT6360_PMU_FLED_MASK2 (0xFA) 225 - #define MT6360_PMU_FAULTB_MASK (0xFB) 226 - #define MT6360_PMU_BUCK1_MASK (0xFC) 227 - #define MT6360_PMU_BUCK2_MASK (0xFD) 228 - #define MT6360_PMU_LDO_MASK1 (0xFE) 229 - #define MT6360_PMU_LDO_MASK2 (0xFF) 230 - #define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2) 231 - 232 - /* MT6360_PMU_IRQ_SET */ 233 - #define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - MT6360_PMU_CHG_IRQ1 + 1) 234 - #define MT6360_IRQ_RETRIG BIT(2) 235 - 236 - #define CHIP_VEN_MASK (0xF0) 237 - #define CHIP_VEN_MT6360 (0x50) 238 - #define CHIP_REV_MASK (0x0F) 239 - 240 - #endif /* __MT6360_H__ */

-33

include/linux/mfd/samsung/core.h

··· 67 67 struct i2c_client *i2c; 68 68 69 69 unsigned long device_type; 70 - int irq_base; 71 70 int irq; 72 71 struct regmap_irq_chip_data *irq_data; 73 - 74 - bool wakeup; 75 72 }; 76 73 77 74 int sec_irq_init(struct sec_pmic_dev *sec_pmic); ··· 78 81 struct sec_platform_data { 79 82 struct sec_regulator_data *regulators; 80 83 struct sec_opmode_data *opmode; 81 - int device_type; 82 84 int num_regulators; 83 - 84 - int irq_base; 85 - int (*cfg_pmic_irq)(void); 86 - 87 - bool wakeup; 88 - bool buck_voltage_lock; 89 85 90 86 int buck_gpios[3]; 91 87 int buck_ds[3]; ··· 89 99 unsigned int buck4_voltage[8]; 90 100 bool buck4_gpiodvs; 91 101 92 - int buck_set1; 93 - int buck_set2; 94 - int buck_set3; 95 - int buck2_enable; 96 - int buck3_enable; 97 - int buck4_enable; 98 102 int buck_default_idx; 99 - int buck2_default_idx; 100 - int buck3_default_idx; 101 - int buck4_default_idx; 102 - 103 103 int buck_ramp_delay; 104 104 105 - int buck2_ramp_delay; 106 - int buck34_ramp_delay; 107 - int buck5_ramp_delay; 108 - int buck16_ramp_delay; 109 - int buck7810_ramp_delay; 110 - int buck9_ramp_delay; 111 - int buck24_ramp_delay; 112 - int buck3_ramp_delay; 113 - int buck7_ramp_delay; 114 - int buck8910_ramp_delay; 115 - 116 - bool buck1_ramp_enable; 117 105 bool buck2_ramp_enable; 118 106 bool buck3_ramp_enable; 119 107 bool buck4_ramp_enable; 120 - bool buck6_ramp_enable; 121 108 122 109 int buck2_init; 123 110 int buck3_init;

+5 -5

sound/soc/codecs/Kconfig

··· 693 693 694 694 config SND_SOC_CS47L24 695 695 tristate 696 - depends on MFD_CS47L24 696 + depends on MFD_CS47L24 && MFD_ARIZONA 697 697 698 698 config SND_SOC_CS47L35 699 699 tristate ··· 1593 1593 1594 1594 config SND_SOC_WM5102 1595 1595 tristate 1596 - depends on MFD_WM5102 1596 + depends on MFD_WM5102 && MFD_ARIZONA 1597 1597 1598 1598 config SND_SOC_WM5110 1599 1599 tristate 1600 - depends on MFD_WM5110 1600 + depends on MFD_WM5110 && MFD_ARIZONA 1601 1601 1602 1602 config SND_SOC_WM8350 1603 1603 tristate ··· 1762 1762 1763 1763 config SND_SOC_WM8997 1764 1764 tristate 1765 - depends on MFD_WM8997 1765 + depends on MFD_WM8997 && MFD_ARIZONA 1766 1766 1767 1767 config SND_SOC_WM8998 1768 1768 tristate 1769 - depends on MFD_WM8998 1769 + depends on MFD_WM8998 && MFD_ARIZONA 1770 1770 1771 1771 config SND_SOC_WM9081 1772 1772 tristate

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