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arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1

On RZ/G2LC SMARC EVK, CAN0 is not populated.

CAN1 is multiplexed with SCIF1 using SW1[3] or RSPI using SW1[4].

This patch adds support for the CAN1 interface on RZ/G2LC SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by
Geert Uytterhoeven 46da6327 fa00d6dc

+36 -6
-6
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
··· 14 14 compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; 15 15 }; 16 16 17 - &canfd { 18 - /delete-property/ pinctrl-0; 19 - /delete-property/ pinctrl-names; 20 - status = "disabled"; 21 - }; 22 - 23 17 &ehci0 { 24 18 /delete-property/ pinctrl-0; 25 19 /delete-property/ pinctrl-names;
+23
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
··· 17 17 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ 18 18 }; 19 19 20 + #if SW_SCIF_CAN 21 + /* SW8 should be at position 2->1 */ 22 + can1_pins: can1 { 23 + pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */ 24 + <RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */ 25 + }; 26 + #endif 27 + 20 28 scif1_pins: scif1 { 21 29 pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ 22 30 <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ 23 31 <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ 24 32 <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ 25 33 }; 34 + 35 + #if SW_RSPI_CAN 36 + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ 37 + can1-stb { 38 + gpio-hog; 39 + gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>; 40 + output-low; 41 + line-name = "can1_stb"; 42 + }; 43 + 44 + can1_pins: can1 { 45 + pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */ 46 + <RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */ 47 + }; 48 + #endif 26 49 27 50 sd1-pwr-en-hog { 28 51 gpio-hog;
+13
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
··· 44 44 }; 45 45 }; 46 46 47 + #if (SW_SCIF_CAN || SW_RSPI_CAN) 48 + &canfd { 49 + pinctrl-0 = <&can1_pins>; 50 + /delete-node/ channel@0; 51 + }; 52 + #else 53 + &canfd { 54 + /delete-property/ pinctrl-0; 55 + /delete-property/ pinctrl-names; 56 + status = "disabled"; 57 + }; 58 + #endif 59 + 47 60 /* 48 61 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board 49 62 * SW1 should be at position 2->3 so that SER0_CTS# line is activated