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arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board

SCIF1 interface is available on PMOD1 connector (CN7) on carrier board.

This patch adds pinmux and scif1 node to carrier board dtsi file for
RZ/G2LC SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by
Geert Uytterhoeven fa00d6dc 2ed3b5d9

+33
+7
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
··· 17 17 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ 18 18 }; 19 19 20 + scif1_pins: scif1 { 21 + pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ 22 + <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ 23 + <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ 24 + <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ 25 + }; 26 + 20 27 sd1-pwr-en-hog { 21 28 gpio-hog; 22 29 gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
+26
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
··· 34 34 #include "rzg2lc-smarc-som.dtsi" 35 35 #include "rzg2lc-smarc-pinfunction.dtsi" 36 36 #include "rz-smarc-common.dtsi" 37 + 38 + /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ 39 + #define PMOD1_SER0 1 40 + 41 + / { 42 + aliases { 43 + serial1 = &scif1; 44 + }; 45 + }; 46 + 47 + /* 48 + * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board 49 + * SW1 should be at position 2->3 so that SER0_CTS# line is activated 50 + * SW2 should be at position 2->3 so that SER0_TX line is activated 51 + * SW3 should be at position 2->3 so that SER0_RX line is activated 52 + * SW4 should be at position 2->3 so that SER0_RTS# line is activated 53 + */ 54 + #if (!SW_SCIF_CAN && PMOD1_SER0) 55 + &scif1 { 56 + pinctrl-0 = <&scif1_pins>; 57 + pinctrl-names = "default"; 58 + 59 + uart-has-rtscts; 60 + status = "okay"; 61 + }; 62 + #endif