drm/amdgpu: Add didt method to register block

+2 -6

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 914 914 amdgpu_wreg64_t pcie_wreg64; 915 915 amdgpu_rreg64_ext_t pcie_rreg64_ext; 916 916 amdgpu_wreg64_ext_t pcie_wreg64_ext; 917 - /* protects concurrent DIDT register access */ 918 - spinlock_t didt_idx_lock; 919 - amdgpu_rreg_t didt_rreg; 920 - amdgpu_wreg_t didt_wreg; 921 917 /* protects concurrent gc_cac register access */ 922 918 spinlock_t gc_cac_idx_lock; 923 919 amdgpu_rreg_t gc_cac_rreg; ··· 1334 1338 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1335 1339 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1336 1340 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1337 - #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1338 - #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1341 + #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1342 + #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1339 1343 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1340 1344 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1341 1345 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

··· 638 638 if (size & 0x3 || *pos & 0x3) 639 639 return -EINVAL; 640 640 641 - if (!adev->didt_rreg) 641 + if (!adev->reg.didt.rreg) 642 642 return -EOPNOTSUPP; 643 643 644 644 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); ··· 696 696 if (size & 0x3 || *pos & 0x3) 697 697 return -EINVAL; 698 698 699 - if (!adev->didt_wreg) 699 + if (!adev->reg.didt.wreg) 700 700 return -EOPNOTSUPP; 701 701 702 702 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);

-3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 3842 3842 adev->pcie_wreg64 = &amdgpu_invalid_wreg64; 3843 3843 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; 3844 3844 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; 3845 - adev->didt_rreg = &amdgpu_invalid_rreg; 3846 - adev->didt_wreg = &amdgpu_invalid_wreg; 3847 3845 adev->gc_cac_rreg = &amdgpu_invalid_rreg; 3848 3846 adev->gc_cac_wreg = &amdgpu_invalid_wreg; 3849 3847 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; ··· 3891 3893 3892 3894 spin_lock_init(&adev->mmio_idx_lock); 3893 3895 spin_lock_init(&adev->pcie_idx_lock); 3894 - spin_lock_init(&adev->didt_idx_lock); 3895 3896 spin_lock_init(&adev->gc_cac_idx_lock); 3896 3897 spin_lock_init(&adev->se_cac_idx_lock); 3897 3898 spin_lock_init(&adev->audio_endpt_idx_lock);

+22

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

··· 42 42 spin_lock_init(&adev->reg.uvd_ctx.lock); 43 43 adev->reg.uvd_ctx.rreg = NULL; 44 44 adev->reg.uvd_ctx.wreg = NULL; 45 + 46 + spin_lock_init(&adev->reg.didt.lock); 47 + adev->reg.didt.rreg = NULL; 48 + adev->reg.didt.wreg = NULL; 45 49 } 46 50 47 51 uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) ··· 85 81 return; 86 82 } 87 83 adev->reg.uvd_ctx.wreg(adev, reg, v); 84 + } 85 + 86 + uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg) 87 + { 88 + if (!adev->reg.didt.rreg) { 89 + dev_err_once(adev->dev, "DIDT register read not supported\n"); 90 + return 0; 91 + } 92 + return adev->reg.didt.rreg(adev, reg); 93 + } 94 + 95 + void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) 96 + { 97 + if (!adev->reg.didt.wreg) { 98 + dev_err_once(adev->dev, "DIDT register write not supported\n"); 99 + return; 100 + } 101 + adev->reg.didt.wreg(adev, reg, v); 88 102 } 89 103 90 104 /*

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h

··· 41 41 struct amdgpu_reg_access { 42 42 struct amdgpu_reg_ind smc; 43 43 struct amdgpu_reg_ind uvd_ctx; 44 + struct amdgpu_reg_ind didt; 44 45 }; 45 46 46 47 void amdgpu_reg_access_init(struct amdgpu_device *adev); ··· 49 48 void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 50 49 uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg); 51 50 void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 51 + uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg); 52 + void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 52 53 53 54 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); 54 55 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);

+6 -6

drivers/gpu/drm/amd/amdgpu/cik.c

··· 223 223 unsigned long flags; 224 224 u32 r; 225 225 226 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 226 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 227 227 WREG32(mmDIDT_IND_INDEX, (reg)); 228 228 r = RREG32(mmDIDT_IND_DATA); 229 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 229 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 230 230 return r; 231 231 } 232 232 ··· 234 234 { 235 235 unsigned long flags; 236 236 237 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 237 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 238 238 WREG32(mmDIDT_IND_INDEX, (reg)); 239 239 WREG32(mmDIDT_IND_DATA, (v)); 240 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 240 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 241 241 } 242 242 243 243 static const u32 bonaire_golden_spm_registers[] = ··· 1990 1990 adev->pcie_wreg = &cik_pcie_wreg; 1991 1991 adev->reg.uvd_ctx.rreg = &cik_uvd_ctx_rreg; 1992 1992 adev->reg.uvd_ctx.wreg = &cik_uvd_ctx_wreg; 1993 - adev->didt_rreg = &cik_didt_rreg; 1994 - adev->didt_wreg = &cik_didt_wreg; 1993 + adev->reg.didt.rreg = &cik_didt_rreg; 1994 + adev->reg.didt.wreg = &cik_didt_wreg; 1995 1995 1996 1996 adev->asic_funcs = &cik_asic_funcs; 1997 1997

+6 -6

drivers/gpu/drm/amd/amdgpu/nv.c

··· 283 283 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 284 284 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 285 285 286 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 286 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 287 287 WREG32(address, (reg)); 288 288 r = RREG32(data); 289 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 289 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 290 290 return r; 291 291 } 292 292 ··· 297 297 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 298 298 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 299 299 300 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 300 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 301 301 WREG32(address, (reg)); 302 302 WREG32(data, (v)); 303 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 303 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 304 304 } 305 305 306 306 static u32 nv_get_config_memsize(struct amdgpu_device *adev) ··· 642 642 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 643 643 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 644 644 645 - adev->didt_rreg = &nv_didt_rreg; 646 - adev->didt_wreg = &nv_didt_wreg; 645 + adev->reg.didt.rreg = &nv_didt_rreg; 646 + adev->reg.didt.wreg = &nv_didt_wreg; 647 647 648 648 adev->asic_funcs = &nv_asic_funcs; 649 649

-2

drivers/gpu/drm/amd/amdgpu/si.c

··· 2045 2045 adev->pciep_wreg = &si_pciep_wreg; 2046 2046 adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg; 2047 2047 adev->reg.uvd_ctx.wreg = &si_uvd_ctx_wreg; 2048 - adev->didt_rreg = NULL; 2049 - adev->didt_wreg = NULL; 2050 2048 2051 2049 adev->asic_funcs = &si_asic_funcs; 2052 2050

+6 -6

drivers/gpu/drm/amd/amdgpu/soc15.c

··· 273 273 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 274 274 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 275 275 276 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 276 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 277 277 WREG32(address, (reg)); 278 278 r = RREG32(data); 279 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 279 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 280 280 return r; 281 281 } 282 282 ··· 287 287 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 288 288 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 289 289 290 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 290 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 291 291 WREG32(address, (reg)); 292 292 WREG32(data, (v)); 293 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 293 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 294 294 } 295 295 296 296 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) ··· 971 971 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 972 972 adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; 973 973 adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; 974 - adev->didt_rreg = &soc15_didt_rreg; 975 - adev->didt_wreg = &soc15_didt_wreg; 974 + adev->reg.didt.rreg = &soc15_didt_rreg; 975 + adev->reg.didt.wreg = &soc15_didt_wreg; 976 976 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 977 977 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 978 978 adev->se_cac_rreg = &soc15_se_cac_rreg;

+6 -6

drivers/gpu/drm/amd/amdgpu/soc21.c

··· 229 229 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 230 230 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 231 231 232 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 232 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 233 233 WREG32(address, (reg)); 234 234 r = RREG32(data); 235 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 235 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 236 236 return r; 237 237 } 238 238 ··· 243 243 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 244 244 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 245 245 246 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 246 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 247 247 WREG32(address, (reg)); 248 248 WREG32(data, (v)); 249 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 249 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 250 250 } 251 251 252 252 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) ··· 596 596 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 597 597 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 598 598 599 - adev->didt_rreg = &soc21_didt_rreg; 600 - adev->didt_wreg = &soc21_didt_wreg; 599 + adev->reg.didt.rreg = &soc21_didt_rreg; 600 + adev->reg.didt.wreg = &soc21_didt_wreg; 601 601 602 602 adev->asic_funcs = &soc21_asic_funcs; 603 603

-2

drivers/gpu/drm/amd/amdgpu/soc24.c

··· 368 368 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 369 369 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 370 370 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 371 - adev->didt_rreg = NULL; 372 - adev->didt_wreg = NULL; 373 371 374 372 adev->asic_funcs = &soc24_asic_funcs; 375 373

-2

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

··· 260 260 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 261 261 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 262 262 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 263 - adev->didt_rreg = NULL; 264 - adev->didt_wreg = NULL; 265 263 266 264 adev->asic_funcs = &soc_v1_0_asic_funcs; 267 265

+6 -6

drivers/gpu/drm/amd/amdgpu/vi.c

··· 394 394 unsigned long flags; 395 395 u32 r; 396 396 397 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 397 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 398 398 WREG32(mmDIDT_IND_INDEX, (reg)); 399 399 r = RREG32(mmDIDT_IND_DATA); 400 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 400 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 401 401 return r; 402 402 } 403 403 ··· 405 405 { 406 406 unsigned long flags; 407 407 408 - spin_lock_irqsave(&adev->didt_idx_lock, flags); 408 + spin_lock_irqsave(&adev->reg.didt.lock, flags); 409 409 WREG32(mmDIDT_IND_INDEX, (reg)); 410 410 WREG32(mmDIDT_IND_DATA, (v)); 411 - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 411 + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 412 412 } 413 413 414 414 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) ··· 1464 1464 adev->pcie_wreg = &vi_pcie_wreg; 1465 1465 adev->reg.uvd_ctx.rreg = &vi_uvd_ctx_rreg; 1466 1466 adev->reg.uvd_ctx.wreg = &vi_uvd_ctx_wreg; 1467 - adev->didt_rreg = &vi_didt_rreg; 1468 - adev->didt_wreg = &vi_didt_wreg; 1467 + adev->reg.didt.rreg = &vi_didt_rreg; 1468 + adev->reg.didt.wreg = &vi_didt_wreg; 1469 1469 adev->gc_cac_rreg = &vi_gc_cac_rreg; 1470 1470 adev->gc_cac_wreg = &vi_gc_cac_wreg; 1471 1471

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