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drm/amdgpu: add support for GC IP version 11.5.4

This initializes GC IP version 11.5.4.

v2: squash in RLC offset fix

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Tim Huang and committed by
Alex Deucher 47ae1f93 bc35ae1a

+34 -1
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
··· 1988 1988 case IP_VERSION(11, 5, 1): 1989 1989 case IP_VERSION(11, 5, 2): 1990 1990 case IP_VERSION(11, 5, 3): 1991 + case IP_VERSION(11, 5, 4): 1991 1992 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1992 1993 break; 1993 1994 case IP_VERSION(12, 0, 0): ··· 2048 2047 case IP_VERSION(11, 5, 1): 2049 2048 case IP_VERSION(11, 5, 2): 2050 2049 case IP_VERSION(11, 5, 3): 2050 + case IP_VERSION(11, 5, 4): 2051 2051 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2052 2052 break; 2053 2053 case IP_VERSION(12, 0, 0): ··· 2360 2358 case IP_VERSION(11, 5, 1): 2361 2359 case IP_VERSION(11, 5, 2): 2362 2360 case IP_VERSION(11, 5, 3): 2361 + case IP_VERSION(11, 5, 4): 2363 2362 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2364 2363 break; 2365 2364 case IP_VERSION(12, 0, 0): ··· 2562 2559 case IP_VERSION(11, 5, 1): 2563 2560 case IP_VERSION(11, 5, 2): 2564 2561 case IP_VERSION(11, 5, 3): 2562 + case IP_VERSION(11, 5, 4): 2565 2563 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2566 2564 adev->enable_mes = true; 2567 2565 adev->enable_mes_kiq = true; ··· 2965 2961 case IP_VERSION(11, 5, 1): 2966 2962 case IP_VERSION(11, 5, 2): 2967 2963 case IP_VERSION(11, 5, 3): 2964 + case IP_VERSION(11, 5, 4): 2968 2965 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2969 2966 break; 2970 2967 case IP_VERSION(12, 0, 0): ··· 2993 2988 case IP_VERSION(11, 5, 1): 2994 2989 case IP_VERSION(11, 5, 2): 2995 2990 case IP_VERSION(11, 5, 3): 2991 + case IP_VERSION(11, 5, 4): 2996 2992 adev->flags |= AMD_IS_APU; 2997 2993 break; 2998 2994 default:
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
··· 949 949 case IP_VERSION(11, 5, 1): 950 950 case IP_VERSION(11, 5, 2): 951 951 case IP_VERSION(11, 5, 3): 952 + case IP_VERSION(11, 5, 4): 952 953 /* Don't enable it by default yet. 953 954 */ 954 955 if (amdgpu_tmz < 1) {
+11 -1
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 120 120 MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin"); 121 121 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin"); 122 122 MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin"); 123 + MODULE_FIRMWARE("amdgpu/gc_11_5_4_pfp.bin"); 124 + MODULE_FIRMWARE("amdgpu/gc_11_5_4_me.bin"); 125 + MODULE_FIRMWARE("amdgpu/gc_11_5_4_mec.bin"); 126 + MODULE_FIRMWARE("amdgpu/gc_11_5_4_rlc.bin"); 123 127 124 128 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 125 129 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), ··· 1117 1113 case IP_VERSION(11, 5, 1): 1118 1114 case IP_VERSION(11, 5, 2): 1119 1115 case IP_VERSION(11, 5, 3): 1116 + case IP_VERSION(11, 5, 4): 1120 1117 adev->gfx.config.max_hw_contexts = 8; 1121 1118 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1122 1119 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; ··· 1600 1595 case IP_VERSION(11, 5, 1): 1601 1596 case IP_VERSION(11, 5, 2): 1602 1597 case IP_VERSION(11, 5, 3): 1598 + case IP_VERSION(11, 5, 4): 1603 1599 adev->gfx.me.num_me = 1; 1604 1600 adev->gfx.me.num_pipe_per_me = 1; 1605 1601 adev->gfx.me.num_queue_per_pipe = 2; ··· 3058 3052 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 3059 3053 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || 3060 3054 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) || 3061 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3)) 3055 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3) || 3056 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 3062 3057 bootload_status = RREG32_SOC15(GC, 0, 3063 3058 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 3064 3059 else ··· 5647 5640 case IP_VERSION(11, 5, 1): 5648 5641 case IP_VERSION(11, 5, 2): 5649 5642 case IP_VERSION(11, 5, 3): 5643 + case IP_VERSION(11, 5, 4): 5650 5644 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5651 5645 break; 5652 5646 default: ··· 5686 5678 case IP_VERSION(11, 5, 1): 5687 5679 case IP_VERSION(11, 5, 2): 5688 5680 case IP_VERSION(11, 5, 3): 5681 + case IP_VERSION(11, 5, 4): 5689 5682 if (!enable) 5690 5683 amdgpu_gfx_off_ctrl(adev, false); 5691 5684 ··· 5721 5712 case IP_VERSION(11, 5, 1): 5722 5713 case IP_VERSION(11, 5, 2): 5723 5714 case IP_VERSION(11, 5, 3): 5715 + case IP_VERSION(11, 5, 4): 5724 5716 gfx_v11_0_update_gfx_clock_gating(adev, 5725 5717 state == AMD_CG_STATE_GATE); 5726 5718 break;
+2
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
··· 602 602 case IP_VERSION(11, 5, 1): 603 603 case IP_VERSION(11, 5, 2): 604 604 case IP_VERSION(11, 5, 3): 605 + case IP_VERSION(11, 5, 4): 605 606 adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs; 606 607 break; 607 608 default: ··· 779 778 case IP_VERSION(11, 5, 1): 780 779 case IP_VERSION(11, 5, 2): 781 780 case IP_VERSION(11, 5, 3): 781 + case IP_VERSION(11, 5, 4): 782 782 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 783 783 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 784 784 /*
+1
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
··· 41 41 MODULE_FIRMWARE("amdgpu/gc_11_5_1_imu.bin"); 42 42 MODULE_FIRMWARE("amdgpu/gc_11_5_2_imu.bin"); 43 43 MODULE_FIRMWARE("amdgpu/gc_11_5_3_imu.bin"); 44 + MODULE_FIRMWARE("amdgpu/gc_11_5_4_imu.bin"); 44 45 45 46 static int imu_v11_0_init_microcode(struct amdgpu_device *adev) 46 47 {
+2
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
··· 56 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 + MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 + MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 59 61 60 62 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 61 63 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block);
+5
drivers/gpu/drm/amd/amdgpu/soc21.c
··· 799 799 AMD_PG_SUPPORT_GFX_PG; 800 800 adev->external_rev_id = adev->rev_id + 0x50; 801 801 break; 802 + case IP_VERSION(11, 5, 4): 803 + adev->cg_flags = 0; 804 + adev->pg_flags = 0; 805 + adev->external_rev_id = adev->rev_id + 0x1; 806 + break; 802 807 default: 803 808 /* FIXME: not supported yet */ 804 809 return -EINVAL;
+1
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
··· 1705 1705 case IP_VERSION(11, 5, 1): 1706 1706 case IP_VERSION(11, 5, 2): 1707 1707 case IP_VERSION(11, 5, 3): 1708 + case IP_VERSION(11, 5, 4): 1708 1709 /* Cacheline size not available in IP discovery for gc11. 1709 1710 * kfd_fill_gpu_cache_info_from_gfx_config to hard code it 1710 1711 */
+5
drivers/gpu/drm/amd/amdkfd/kfd_device.c
··· 164 164 case IP_VERSION(11, 5, 1): 165 165 case IP_VERSION(11, 5, 2): 166 166 case IP_VERSION(11, 5, 3): 167 + case IP_VERSION(11, 5, 4): 167 168 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 168 169 break; 169 170 case IP_VERSION(12, 0, 0): ··· 442 441 gfx_target_version = 110503; 443 442 f2g = &gfx_v11_kfd2kgd; 444 443 break; 444 + case IP_VERSION(11, 5, 4): 445 + gfx_target_version = 110504; 446 + f2g = &gfx_v11_kfd2kgd; 447 + break; 445 448 case IP_VERSION(12, 0, 0): 446 449 gfx_target_version = 120000; 447 450 f2g = &gfx_v12_kfd2kgd;