phy: qcom-qmp-pcie: cleanup the driver · tjh.dev/kernel@fd92699

+11 -202

1 changed file

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drivers

phy

qualcomm

phy-qcom-qmp-pcie.c

+11 -202

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

··· 1257 1257 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 1258 1258 int pcs_misc_tbl_num_sec; 1259 1259 1260 - /* Init sequence for DP PHY block link rates */ 1261 - const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1262 - int serdes_tbl_rbr_num; 1263 - const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1264 - int serdes_tbl_hbr_num; 1265 - const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1266 - int serdes_tbl_hbr2_num; 1267 - const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1268 - int serdes_tbl_hbr3_num; 1269 - 1270 - /* DP PHY callbacks */ 1271 - int (*configure_dp_phy)(struct qmp_phy *qphy); 1272 - void (*configure_dp_tx)(struct qmp_phy *qphy); 1273 - int (*calibrate_dp_phy)(struct qmp_phy *qphy); 1274 - void (*dp_aux_init)(struct qmp_phy *qphy); 1275 - 1276 1260 /* clock ids to be requested */ 1277 1261 const char * const *clk_list; 1278 1262 int num_clks; ··· 1276 1292 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1277 1293 unsigned int phy_status; 1278 1294 1279 - /* true, if PHY has a separate PHY_COM control block */ 1280 - bool has_phy_com_ctrl; 1281 - /* true, if PHY has a reset for individual lanes */ 1282 - bool has_lane_rst; 1283 1295 /* true, if PHY needs delay after POWER_DOWN */ 1284 1296 bool has_pwrdn_delay; 1285 1297 /* power_down delay in usec */ 1286 1298 int pwrdn_delay_min; 1287 1299 int pwrdn_delay_max; 1288 1300 1289 - /* true, if PHY has a separate DP_COM control block */ 1290 - bool has_phy_dp_com_ctrl; 1291 1301 /* true, if PHY has secondary tx/rx lanes to be configured */ 1292 1302 bool is_dual_lane_phy; 1293 - 1294 - /* true, if PCS block has no separate SW_RESET register */ 1295 - bool no_pcs_sw_reset; 1296 - }; 1297 - 1298 - struct qmp_phy_combo_cfg { 1299 - const struct qmp_phy_cfg *usb_cfg; 1300 - const struct qmp_phy_cfg *dp_cfg; 1301 1303 }; 1302 1304 1303 1305 /** ··· 1301 1331 * @pipe_clk: pipe clock 1302 1332 * @index: lane index 1303 1333 * @qmp: QMP phy to which this lane belongs 1304 - * @lane_rst: lane's reset controller 1305 1334 * @mode: current PHY mode 1306 - * @dp_aux_cfg: Display port aux config 1307 - * @dp_opts: Display port optional config 1308 - * @dp_clks: Display port clocks 1309 1335 */ 1310 1336 struct qmp_phy { 1311 1337 struct phy *phy; ··· 1316 1350 struct clk *pipe_clk; 1317 1351 unsigned int index; 1318 1352 struct qcom_qmp *qmp; 1319 - struct reset_control *lane_rst; 1320 1353 enum phy_mode mode; 1321 - unsigned int dp_aux_cfg; 1322 - struct phy_configure_opts_dp dp_opts; 1323 - struct qmp_phy_dp_clks *dp_clks; 1324 - }; 1325 - 1326 - struct qmp_phy_dp_clks { 1327 - struct qmp_phy *qphy; 1328 - struct clk_hw dp_link_hw; 1329 - struct clk_hw dp_pixel_hw; 1330 1354 }; 1331 1355 1332 1356 /** 1333 1357 * struct qcom_qmp - structure holding QMP phy block attributes 1334 1358 * 1335 1359 * @dev: device 1336 - * @dp_com: iomapped memory space for phy's dp_com control block 1337 1360 * 1338 1361 * @clks: array of clocks required by phy 1339 1362 * @resets: array of resets required by phy ··· 1331 1376 * @phys: array of per-lane phy descriptors 1332 1377 * @phy_mutex: mutex lock for PHY common block initialization 1333 1378 * @init_count: phy common block initialization count 1334 - * @ufs_reset: optional UFS PHY reset handle 1335 1379 */ 1336 1380 struct qcom_qmp { 1337 1381 struct device *dev; 1338 - void __iomem *dp_com; 1339 1382 1340 1383 struct clk_bulk_data *clks; 1341 1384 struct reset_control **resets; ··· 1343 1390 1344 1391 struct mutex phy_mutex; 1345 1392 int init_count; 1346 - 1347 - struct reset_control *ufs_reset; 1348 1393 }; 1349 1394 1350 1395 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ··· 1421 1470 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1422 1471 .phy_status = PHYSTATUS, 1423 1472 1424 - .has_phy_com_ctrl = false, 1425 - .has_lane_rst = false, 1426 1473 .has_pwrdn_delay = true, 1427 1474 .pwrdn_delay_min = 995, /* us */ 1428 1475 .pwrdn_delay_max = 1005, /* us */ ··· 1449 1500 .start_ctrl = SERDES_START | PCS_START, 1450 1501 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1451 1502 1452 - .has_phy_com_ctrl = false, 1453 - .has_lane_rst = false, 1454 1503 .has_pwrdn_delay = true, 1455 1504 .pwrdn_delay_min = 995, /* us */ 1456 1505 .pwrdn_delay_max = 1005, /* us */ ··· 1776 1829 1777 1830 static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) 1778 1831 { 1779 - struct qcom_qmp *qmp = qphy->qmp; 1780 1832 const struct qmp_phy_cfg *cfg = qphy->cfg; 1781 1833 void __iomem *serdes = qphy->serdes; 1782 1834 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1783 1835 int serdes_tbl_num = cfg->serdes_tbl_num; 1784 - int ret; 1785 1836 1786 1837 qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 1787 1838 if (cfg->serdes_tbl_sec) 1788 1839 qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 1789 1840 cfg->serdes_tbl_num_sec); 1790 - 1791 - if (cfg->has_phy_com_ctrl) { 1792 - void __iomem *status; 1793 - unsigned int mask, val; 1794 - 1795 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 1796 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 1797 - SERDES_START | PCS_START); 1798 - 1799 - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 1800 - mask = cfg->mask_com_pcs_ready; 1801 - 1802 - ret = readl_poll_timeout(status, val, (val & mask), 10, 1803 - PHY_INIT_COMPLETE_TIMEOUT); 1804 - if (ret) { 1805 - dev_err(qmp->dev, 1806 - "phy common block init timed-out\n"); 1807 - return ret; 1808 - } 1809 - } 1810 1841 1811 1842 return 0; 1812 1843 } ··· 1793 1868 { 1794 1869 struct qcom_qmp *qmp = qphy->qmp; 1795 1870 const struct qmp_phy_cfg *cfg = qphy->cfg; 1796 - void __iomem *serdes = qphy->serdes; 1797 1871 void __iomem *pcs = qphy->pcs; 1798 - void __iomem *dp_com = qmp->dp_com; 1799 1872 int ret, i; 1800 1873 1801 1874 mutex_lock(&qmp->phy_mutex); ··· 1831 1908 if (ret) 1832 1909 goto err_assert_reset; 1833 1910 1834 - if (cfg->has_phy_dp_com_ctrl) { 1835 - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 1836 - SW_PWRDN); 1837 - /* override hardware control for reset of qmp phy */ 1838 - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1839 - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1840 - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1841 - 1842 - /* Default type-c orientation, i.e CC1 */ 1843 - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 1844 - 1845 - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 1846 - USB3_MODE | DP_MODE); 1847 - 1848 - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 1849 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1850 - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1851 - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1852 - 1853 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 1854 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1855 - } 1856 - 1857 - if (cfg->has_phy_com_ctrl) { 1858 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 1859 - SW_PWRDN); 1860 - } else { 1861 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1862 - qphy_setbits(pcs, 1863 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1864 - cfg->pwrdn_ctrl); 1865 - else 1866 - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 1867 - cfg->pwrdn_ctrl); 1868 - } 1911 + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1912 + qphy_setbits(pcs, 1913 + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1914 + cfg->pwrdn_ctrl); 1915 + else 1916 + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 1917 + cfg->pwrdn_ctrl); 1869 1918 1870 1919 mutex_unlock(&qmp->phy_mutex); 1871 1920 ··· 1858 1963 { 1859 1964 struct qcom_qmp *qmp = qphy->qmp; 1860 1965 const struct qmp_phy_cfg *cfg = qphy->cfg; 1861 - void __iomem *serdes = qphy->serdes; 1862 1966 int i = cfg->num_resets; 1863 1967 1864 1968 mutex_lock(&qmp->phy_mutex); 1865 1969 if (--qmp->init_count) { 1866 1970 mutex_unlock(&qmp->phy_mutex); 1867 1971 return 0; 1868 - } 1869 - 1870 - reset_control_assert(qmp->ufs_reset); 1871 - if (cfg->has_phy_com_ctrl) { 1872 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 1873 - SERDES_START | PCS_START); 1874 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 1875 - SW_RESET); 1876 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 1877 - SW_PWRDN); 1878 1972 } 1879 1973 1880 1974 while (--i >= 0) ··· 1882 1998 { 1883 1999 struct qmp_phy *qphy = phy_get_drvdata(phy); 1884 2000 struct qcom_qmp *qmp = qphy->qmp; 1885 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1886 2001 int ret; 1887 2002 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1888 - 1889 - if (cfg->no_pcs_sw_reset) { 1890 - /* 1891 - * Get UFS reset, which is delayed until now to avoid a 1892 - * circular dependency where UFS needs its PHY, but the PHY 1893 - * needs this UFS reset. 1894 - */ 1895 - if (!qmp->ufs_reset) { 1896 - qmp->ufs_reset = 1897 - devm_reset_control_get_exclusive(qmp->dev, 1898 - "ufsphy"); 1899 - 1900 - if (IS_ERR(qmp->ufs_reset)) { 1901 - ret = PTR_ERR(qmp->ufs_reset); 1902 - dev_err(qmp->dev, 1903 - "failed to get UFS reset: %d\n", 1904 - ret); 1905 - 1906 - qmp->ufs_reset = NULL; 1907 - return ret; 1908 - } 1909 - } 1910 - 1911 - ret = reset_control_assert(qmp->ufs_reset); 1912 - if (ret) 1913 - return ret; 1914 - } 1915 2003 1916 2004 ret = qcom_qmp_phy_pcie_com_init(qphy); 1917 2005 if (ret) ··· 1907 2051 1908 2052 qcom_qmp_phy_pcie_serdes_init(qphy); 1909 2053 1910 - if (cfg->has_lane_rst) { 1911 - ret = reset_control_deassert(qphy->lane_rst); 1912 - if (ret) { 1913 - dev_err(qmp->dev, "lane%d reset deassert failed\n", 1914 - qphy->index); 1915 - return ret; 1916 - } 1917 - } 1918 - 1919 2054 ret = clk_prepare_enable(qphy->pipe_clk); 1920 2055 if (ret) { 1921 2056 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1922 - goto err_reset_lane; 2057 + return ret; 1923 2058 } 1924 2059 1925 2060 /* Tx, Rx, and PCS configurations */ ··· 1950 2103 qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 1951 2104 cfg->pcs_tbl_num_sec); 1952 2105 1953 - ret = reset_control_deassert(qmp->ufs_reset); 1954 - if (ret) 1955 - goto err_disable_pipe_clk; 1956 - 1957 2106 qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 1958 2107 cfg->pcs_misc_tbl_num); 1959 2108 if (cfg->pcs_misc_tbl_sec) ··· 1966 2123 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 1967 2124 1968 2125 /* Pull PHY out of reset state */ 1969 - if (!cfg->no_pcs_sw_reset) 1970 - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2126 + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2127 + 1971 2128 /* start SerDes and Phy-Coding-Sublayer */ 1972 2129 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1973 2130 ··· 1986 2143 1987 2144 err_disable_pipe_clk: 1988 2145 clk_disable_unprepare(qphy->pipe_clk); 1989 - err_reset_lane: 1990 - if (cfg->has_lane_rst) 1991 - reset_control_assert(qphy->lane_rst); 1992 2146 1993 2147 return ret; 1994 2148 } ··· 1998 2158 clk_disable_unprepare(qphy->pipe_clk); 1999 2159 2000 2160 /* PHY reset */ 2001 - if (!cfg->no_pcs_sw_reset) 2002 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2161 + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2003 2162 2004 2163 /* stop SerDes and Phy-Coding-Sublayer */ 2005 2164 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ··· 2018 2179 static int qcom_qmp_phy_pcie_exit(struct phy *phy) 2019 2180 { 2020 2181 struct qmp_phy *qphy = phy_get_drvdata(phy); 2021 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2022 - 2023 - if (cfg->has_lane_rst) 2024 - reset_control_assert(qphy->lane_rst); 2025 2182 2026 2183 qcom_qmp_phy_pcie_com_exit(qphy); 2027 2184 ··· 2183 2348 .owner = THIS_MODULE, 2184 2349 }; 2185 2350 2186 - static void qcom_qmp_reset_control_put(void *data) 2187 - { 2188 - reset_control_put(data); 2189 - } 2190 - 2191 2351 static 2192 2352 int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, 2193 2353 void __iomem *serdes, const struct qmp_phy_cfg *cfg) ··· 2266 2436 return ret; 2267 2437 } 2268 2438 qphy->pipe_clk = NULL; 2269 - } 2270 - 2271 - /* Get lane reset, if any */ 2272 - if (cfg->has_lane_rst) { 2273 - snprintf(prop_name, sizeof(prop_name), "lane%d", id); 2274 - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); 2275 - if (IS_ERR(qphy->lane_rst)) { 2276 - dev_err(dev, "failed to get lane%d reset\n", id); 2277 - return PTR_ERR(qphy->lane_rst); 2278 - } 2279 - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 2280 - qphy->lane_rst); 2281 - if (ret) 2282 - return ret; 2283 2439 } 2284 2440 2285 2441 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops); ··· 2353 2537 serdes = devm_platform_ioremap_resource(pdev, 0); 2354 2538 if (IS_ERR(serdes)) 2355 2539 return PTR_ERR(serdes); 2356 - 2357 - /* per PHY dp_com; if PHY has dp_com control block */ 2358 - if (cfg->has_phy_dp_com_ctrl) { 2359 - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2360 - if (IS_ERR(qmp->dp_com)) 2361 - return PTR_ERR(qmp->dp_com); 2362 - } 2363 2540 2364 2541 expected_phys = cfg->nlanes; 2365 2542

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