phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap

The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.

The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230113150615.19375-3-sinthu.raja@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Sinthu Raja and committed by

Vinod Koul 3 years ago 494de1dd 9a8a54b9

+33 -5

1 changed file

expand all

drivers

phy

phy-j721e-wiz.c

+33 -5

drivers/phy/ti/phy-j721e-wiz.c

··· 58 58 LANE_MODE_GEN4, 59 59 }; 60 60 61 + /* 62 + * List of master lanes used for lane swapping 63 + */ 64 + enum wiz_typec_master_lane { 65 + LANE0 = 0, 66 + LANE2 = 2, 67 + }; 68 + 61 69 enum wiz_refclk_mux_sel { 62 70 PLL0_REFCLK, 63 71 PLL1_REFCLK, ··· 201 193 202 194 static const struct reg_field typec_ln10_swap = 203 195 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 196 + 197 + static const struct reg_field typec_ln23_swap = 198 + REG_FIELD(WIZ_SERDES_TYPEC, 31, 31); 204 199 205 200 struct wiz_clk_mux { 206 201 struct clk_hw hw; ··· 378 367 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; 379 368 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; 380 369 struct regmap_field *typec_ln10_swap; 370 + struct regmap_field *typec_ln23_swap; 381 371 struct regmap_field *sup_legacy_clk_override; 382 372 383 373 struct device *dev; ··· 686 674 if (IS_ERR(wiz->typec_ln10_swap)) { 687 675 dev_err(dev, "LN10_SWAP reg field init failed\n"); 688 676 return PTR_ERR(wiz->typec_ln10_swap); 677 + } 678 + 679 + wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap, 680 + typec_ln23_swap); 681 + if (IS_ERR(wiz->typec_ln23_swap)) { 682 + dev_err(dev, "LN23_SWAP reg field init failed\n"); 683 + return PTR_ERR(wiz->typec_ln23_swap); 689 684 } 690 685 691 686 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); ··· 1265 1246 else 1266 1247 regmap_field_write(wiz->typec_ln10_swap, 0); 1267 1248 } else { 1268 - /* if no typec-dir gpio was specified and PHY type is 1269 - * USB3 with master lane number is '0', set LN10 SWAP 1270 - * bit to '1' 1249 + /* if no typec-dir gpio is specified and PHY type is USB3 1250 + * with master lane number is '0' or '2', then set LN10 or 1251 + * LN23 SWAP bit to '1' respectively. 1271 1252 */ 1272 1253 u32 num_lanes = wiz->num_lanes; 1273 1254 int i; 1274 1255 1275 1256 for (i = 0; i < num_lanes; i++) { 1276 - if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) 1277 - if (wiz->master_lane_num[i] == 0) 1257 + if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) { 1258 + switch (wiz->master_lane_num[i]) { 1259 + case LANE0: 1278 1260 regmap_field_write(wiz->typec_ln10_swap, 1); 1261 + break; 1262 + case LANE2: 1263 + regmap_field_write(wiz->typec_ln23_swap, 1); 1264 + break; 1265 + default: 1266 + break; 1267 + } 1268 + } 1279 1269 } 1280 1270 } 1281 1271 }

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