Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: renesas: rzt2h: Add pin configuration support
Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H SoC
allows configuring several electrical characteristics through the DRCTLm
(I/O Buffer Function Switching) registers. These registers control bias
configuration, Schmitt trigger input, output slew rate, and drive
strength.
Implement pinconf_ops to allow reading and updating these properties
through the generic pin configuration framework. The implementation
supports bias-disable, bias-pull-up, bias-pull-down,
input-schmitt-enable, slew-rate, and drive-strength-microamp.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260319141515.2053556-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Lad Prabhakar
and committed by
Geert Uytterhoeven
494feecd
9efe63b7
+258
+258
drivers/pinctrl/renesas/pinctrl-rzt2h.c
+258
drivers/pinctrl/renesas/pinctrl-rzt2h.c
···
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* Copyright (C) 2025 Renesas Electronics Corporation.
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*/
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/bits.h>
···
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#define PMC(m) (0x400 + (m))
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#define PFC(m) (0x600 + 8 * (m))
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#define PIN(m) (0x800 + (m))
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#define DRCTL(n) (0xa00 + 8 * (n))
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#define RSELP(m) (0xc00 + (m))
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#define PM_MASK GENMASK(1, 0)
···
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#define PFC_MASK GENMASK_ULL(5, 0)
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#define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8))
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#define PFC_FUNC_INTERRUPT 0
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#define DRCTL_DRV_PIN_MASK(pin) (GENMASK_ULL(1, 0) << ((pin) * 8))
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#define DRCTL_PUD_PIN_MASK(pin) (GENMASK_ULL(3, 2) << ((pin) * 8))
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#define DRCTL_SMT_PIN_MASK(pin) (BIT_ULL(4) << ((pin) * 8))
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#define DRCTL_SR_PIN_MASK(pin) (BIT_ULL(5) << ((pin) * 8))
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#define DRCTL_PUD_NONE 0
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#define DRCTL_PUD_PULL_UP 1
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#define DRCTL_PUD_PULL_DOWN 2
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/*
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* Use 16 lower bits [15:0] for pin identifier
···
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atomic_t wakeup_path;
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};
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static const unsigned int rzt2h_drive_strength_ua[] = { 2500, 5000, 9000, 11800 };
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#define RZT2H_GET_BASE(pctrl, port) \
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((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1)
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···
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RZT2H_PINCTRL_REG_ACCESS(b, u8)
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RZT2H_PINCTRL_REG_ACCESS(w, u16)
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RZT2H_PINCTRL_REG_ACCESS(q, u64)
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static int rzt2h_drive_strength_ua_to_idx(unsigned int ua)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(rzt2h_drive_strength_ua); i++) {
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if (rzt2h_drive_strength_ua[i] == ua)
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return i;
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}
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return -EINVAL;
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}
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static int rzt2h_drive_strength_idx_to_ua(unsigned int idx)
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{
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if (idx >= ARRAY_SIZE(rzt2h_drive_strength_ua))
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return -EINVAL;
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return rzt2h_drive_strength_ua[idx];
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}
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static void rzt2h_pinctrl_drctl_rmwq(struct rzt2h_pinctrl *pctrl,
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u32 port, u64 mask, u64 val)
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{
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u32 offset = DRCTL(port);
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u64 drctl;
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guard(raw_spinlock_irqsave)(&pctrl->lock);
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drctl = rzt2h_pinctrl_readq(pctrl, port, offset) & ~mask;
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rzt2h_pinctrl_writeq(pctrl, port, drctl | val, offset);
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}
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static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset)
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{
···
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return ret;
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}
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static int rzt2h_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int pin,
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unsigned long *config)
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{
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struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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u32 port, param = pinconf_to_config_param(*config);
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unsigned int arg;
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u8 port_pin;
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u64 drctl;
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int ret;
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ret = rzt2h_validate_pin(pctrl, pin);
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if (ret)
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return ret;
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port = RZT2H_PIN_ID_TO_PORT(pin);
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port_pin = RZT2H_PIN_ID_TO_PIN(pin);
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switch (param) {
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case PIN_CONFIG_SLEW_RATE:
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drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port));
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arg = field_get(DRCTL_SR_PIN_MASK(port_pin), drctl);
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port));
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arg = field_get(DRCTL_PUD_PIN_MASK(port_pin), drctl);
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/* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */
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switch (arg) {
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case DRCTL_PUD_NONE:
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if (param != PIN_CONFIG_BIAS_DISABLE)
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return -EINVAL;
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break;
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case DRCTL_PUD_PULL_UP:
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if (param != PIN_CONFIG_BIAS_PULL_UP)
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return -EINVAL;
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arg = 1;
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break;
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case DRCTL_PUD_PULL_DOWN:
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if (param != PIN_CONFIG_BIAS_PULL_DOWN)
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return -EINVAL;
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arg = 1;
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break;
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default:
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return -EINVAL;
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}
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port));
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arg = field_get(DRCTL_SMT_PIN_MASK(port_pin), drctl);
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if (!arg)
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return -EINVAL;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH_UA: {
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int idx_drv;
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drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port));
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arg = field_get(DRCTL_DRV_PIN_MASK(port_pin), drctl);
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idx_drv = rzt2h_drive_strength_idx_to_ua(arg);
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if (idx_drv < 0)
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return idx_drv;
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arg = idx_drv;
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break;
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}
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int rzt2h_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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unsigned int pin,
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unsigned long *configs,
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unsigned int num_configs)
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{
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struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned int i;
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u8 port_pin;
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int ret;
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ret = rzt2h_validate_pin(pctrl, pin);
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if (ret)
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return ret;
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port_pin = RZT2H_PIN_ID_TO_PIN(pin);
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for (i = 0; i < num_configs; i++) {
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u32 arg = pinconf_to_config_argument(configs[i]);
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u32 param = pinconf_to_config_param(configs[i]);
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u64 mask, val;
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switch (param) {
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case PIN_CONFIG_SLEW_RATE:
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mask = DRCTL_SR_PIN_MASK(port_pin);
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val = field_prep(mask, !!arg);
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN: {
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u32 bias;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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bias = DRCTL_PUD_NONE;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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bias = DRCTL_PUD_PULL_UP;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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bias = DRCTL_PUD_PULL_DOWN;
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break;
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}
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mask = DRCTL_PUD_PIN_MASK(port_pin);
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val = field_prep(mask, bias);
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break;
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}
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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mask = DRCTL_SMT_PIN_MASK(port_pin);
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val = field_prep(mask, !!arg);
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break;
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case PIN_CONFIG_DRIVE_STRENGTH_UA: {
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int drv_idx;
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drv_idx = rzt2h_drive_strength_ua_to_idx(arg);
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if (drv_idx < 0)
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return drv_idx;
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mask = DRCTL_DRV_PIN_MASK(port_pin);
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val = field_prep(mask, drv_idx);
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break;
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}
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default:
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return -ENOTSUPP;
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}
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rzt2h_pinctrl_drctl_rmwq(pctrl, RZT2H_PIN_ID_TO_PORT(pin), mask, val);
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}
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return 0;
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}
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static int rzt2h_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
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unsigned int group,
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unsigned long *config)
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{
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unsigned long prev_config = 0;
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const unsigned int *pins;
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unsigned int i, npins;
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int ret;
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ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
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if (ret)
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return ret;
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for (i = 0; i < npins; i++) {
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ret = rzt2h_pinctrl_pinconf_get(pctldev, pins[i], config);
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if (ret)
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return ret;
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/* Check config matches previous pins */
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if (i && prev_config != *config)
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return -ENOTSUPP;
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prev_config = *config;
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}
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return 0;
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}
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static int rzt2h_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
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unsigned int group,
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unsigned long *configs,
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unsigned int num_configs)
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{
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const unsigned int *pins;
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unsigned int i, npins;
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int ret;
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ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
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if (ret)
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return ret;
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for (i = 0; i < npins; i++) {
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ret = rzt2h_pinctrl_pinconf_set(pctldev, pins[i], configs,
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num_configs);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct pinctrl_ops rzt2h_pinctrl_pctlops = {
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.get_groups_count = pinctrl_generic_get_group_count,
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.get_group_name = pinctrl_generic_get_group_name,
···
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.get_function_groups = pinmux_generic_get_function_groups,
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.set_mux = rzt2h_pinctrl_set_mux,
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.strict = true,
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};
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static const struct pinconf_ops rzt2h_pinctrl_confops = {
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.is_generic = true,
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.pin_config_get = rzt2h_pinctrl_pinconf_get,
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.pin_config_set = rzt2h_pinctrl_pinconf_set,
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.pin_config_group_set = rzt2h_pinctrl_pinconf_group_set,
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.pin_config_group_get = rzt2h_pinctrl_pinconf_group_get,
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.pin_config_config_dbg_show = pinconf_generic_dump_config,
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};
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static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset)
···
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desc->npins = pctrl->data->n_port_pins;
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desc->pctlops = &rzt2h_pinctrl_pctlops;
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desc->pmxops = &rzt2h_pinctrl_pmxops;
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desc->confops = &rzt2h_pinctrl_confops;
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desc->owner = THIS_MODULE;
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pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL);