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dt-bindings: clock: rzg2l: Drop power domain IDs

Since the configuration order between the individual MSTOP and CLKON
bits cannot be preserved with the power domain abstraction, drop the
power domain IDs. The corresponding code has also been removed.
Currently, there are no device tree users for these IDs.

Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-8-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Claudiu Beznea and committed by
Geert Uytterhoeven 4a59e02a 26a301a2

-240
-53
include/dt-bindings/clock/r9a07g043-cpg.h
··· 200 200 #define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ 201 201 #define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ 202 202 203 - /* Power domain IDs. */ 204 - #define R9A07G043_PD_ALWAYS_ON 0 205 - #define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */ 206 - #define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */ 207 - #define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */ 208 - #define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */ 209 - #define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */ 210 - #define R9A07G043_PD_DMAC 6 211 - #define R9A07G043_PD_GTM0 7 212 - #define R9A07G043_PD_GTM1 8 213 - #define R9A07G043_PD_GTM2 9 214 - #define R9A07G043_PD_MTU 10 215 - #define R9A07G043_PD_POE3 11 216 - #define R9A07G043_PD_WDT0 12 217 - #define R9A07G043_PD_SPI 13 218 - #define R9A07G043_PD_SDHI0 14 219 - #define R9A07G043_PD_SDHI1 15 220 - #define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */ 221 - #define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */ 222 - #define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */ 223 - #define R9A07G043_PD_SSI0 19 224 - #define R9A07G043_PD_SSI1 20 225 - #define R9A07G043_PD_SSI2 21 226 - #define R9A07G043_PD_SSI3 22 227 - #define R9A07G043_PD_SRC 23 228 - #define R9A07G043_PD_USB0 24 229 - #define R9A07G043_PD_USB1 25 230 - #define R9A07G043_PD_USB_PHY 26 231 - #define R9A07G043_PD_ETHER0 27 232 - #define R9A07G043_PD_ETHER1 28 233 - #define R9A07G043_PD_I2C0 29 234 - #define R9A07G043_PD_I2C1 30 235 - #define R9A07G043_PD_I2C2 31 236 - #define R9A07G043_PD_I2C3 32 237 - #define R9A07G043_PD_SCIF0 33 238 - #define R9A07G043_PD_SCIF1 34 239 - #define R9A07G043_PD_SCIF2 35 240 - #define R9A07G043_PD_SCIF3 36 241 - #define R9A07G043_PD_SCIF4 37 242 - #define R9A07G043_PD_SCI0 38 243 - #define R9A07G043_PD_SCI1 39 244 - #define R9A07G043_PD_IRDA 40 245 - #define R9A07G043_PD_RSPI0 41 246 - #define R9A07G043_PD_RSPI1 42 247 - #define R9A07G043_PD_RSPI2 43 248 - #define R9A07G043_PD_CANFD 44 249 - #define R9A07G043_PD_ADC 45 250 - #define R9A07G043_PD_TSU 46 251 - #define R9A07G043_PD_PLIC 47 /* RZ/Five Only */ 252 - #define R9A07G043_PD_IAX45 48 /* RZ/Five Only */ 253 - #define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */ 254 - #define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */ 255 - 256 203 #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
-58
include/dt-bindings/clock/r9a07g044-cpg.h
··· 217 217 #define R9A07G044_ADC_ADRST_N 82 218 218 #define R9A07G044_TSU_PRESETN 83 219 219 220 - /* Power domain IDs. */ 221 - #define R9A07G044_PD_ALWAYS_ON 0 222 - #define R9A07G044_PD_GIC 1 223 - #define R9A07G044_PD_IA55 2 224 - #define R9A07G044_PD_MHU 3 225 - #define R9A07G044_PD_CORESIGHT 4 226 - #define R9A07G044_PD_SYC 5 227 - #define R9A07G044_PD_DMAC 6 228 - #define R9A07G044_PD_GTM0 7 229 - #define R9A07G044_PD_GTM1 8 230 - #define R9A07G044_PD_GTM2 9 231 - #define R9A07G044_PD_MTU 10 232 - #define R9A07G044_PD_POE3 11 233 - #define R9A07G044_PD_GPT 12 234 - #define R9A07G044_PD_POEGA 13 235 - #define R9A07G044_PD_POEGB 14 236 - #define R9A07G044_PD_POEGC 15 237 - #define R9A07G044_PD_POEGD 16 238 - #define R9A07G044_PD_WDT0 17 239 - #define R9A07G044_PD_WDT1 18 240 - #define R9A07G044_PD_SPI 19 241 - #define R9A07G044_PD_SDHI0 20 242 - #define R9A07G044_PD_SDHI1 21 243 - #define R9A07G044_PD_3DGE 22 244 - #define R9A07G044_PD_ISU 23 245 - #define R9A07G044_PD_VCPL4 24 246 - #define R9A07G044_PD_CRU 25 247 - #define R9A07G044_PD_MIPI_DSI 26 248 - #define R9A07G044_PD_LCDC 27 249 - #define R9A07G044_PD_SSI0 28 250 - #define R9A07G044_PD_SSI1 29 251 - #define R9A07G044_PD_SSI2 30 252 - #define R9A07G044_PD_SSI3 31 253 - #define R9A07G044_PD_SRC 32 254 - #define R9A07G044_PD_USB0 33 255 - #define R9A07G044_PD_USB1 34 256 - #define R9A07G044_PD_USB_PHY 35 257 - #define R9A07G044_PD_ETHER0 36 258 - #define R9A07G044_PD_ETHER1 37 259 - #define R9A07G044_PD_I2C0 38 260 - #define R9A07G044_PD_I2C1 39 261 - #define R9A07G044_PD_I2C2 40 262 - #define R9A07G044_PD_I2C3 41 263 - #define R9A07G044_PD_SCIF0 42 264 - #define R9A07G044_PD_SCIF1 43 265 - #define R9A07G044_PD_SCIF2 44 266 - #define R9A07G044_PD_SCIF3 45 267 - #define R9A07G044_PD_SCIF4 46 268 - #define R9A07G044_PD_SCI0 47 269 - #define R9A07G044_PD_SCI1 48 270 - #define R9A07G044_PD_IRDA 49 271 - #define R9A07G044_PD_RSPI0 50 272 - #define R9A07G044_PD_RSPI1 51 273 - #define R9A07G044_PD_RSPI2 52 274 - #define R9A07G044_PD_CANFD 53 275 - #define R9A07G044_PD_ADC 54 276 - #define R9A07G044_PD_TSU 55 277 - 278 220 #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
-58
include/dt-bindings/clock/r9a07g054-cpg.h
··· 226 226 #define R9A07G054_TSU_PRESETN 83 227 227 #define R9A07G054_STPAI_ARESETN 84 228 228 229 - /* Power domain IDs. */ 230 - #define R9A07G054_PD_ALWAYS_ON 0 231 - #define R9A07G054_PD_GIC 1 232 - #define R9A07G054_PD_IA55 2 233 - #define R9A07G054_PD_MHU 3 234 - #define R9A07G054_PD_CORESIGHT 4 235 - #define R9A07G054_PD_SYC 5 236 - #define R9A07G054_PD_DMAC 6 237 - #define R9A07G054_PD_GTM0 7 238 - #define R9A07G054_PD_GTM1 8 239 - #define R9A07G054_PD_GTM2 9 240 - #define R9A07G054_PD_MTU 10 241 - #define R9A07G054_PD_POE3 11 242 - #define R9A07G054_PD_GPT 12 243 - #define R9A07G054_PD_POEGA 13 244 - #define R9A07G054_PD_POEGB 14 245 - #define R9A07G054_PD_POEGC 15 246 - #define R9A07G054_PD_POEGD 16 247 - #define R9A07G054_PD_WDT0 17 248 - #define R9A07G054_PD_WDT1 18 249 - #define R9A07G054_PD_SPI 19 250 - #define R9A07G054_PD_SDHI0 20 251 - #define R9A07G054_PD_SDHI1 21 252 - #define R9A07G054_PD_3DGE 22 253 - #define R9A07G054_PD_ISU 23 254 - #define R9A07G054_PD_VCPL4 24 255 - #define R9A07G054_PD_CRU 25 256 - #define R9A07G054_PD_MIPI_DSI 26 257 - #define R9A07G054_PD_LCDC 27 258 - #define R9A07G054_PD_SSI0 28 259 - #define R9A07G054_PD_SSI1 29 260 - #define R9A07G054_PD_SSI2 30 261 - #define R9A07G054_PD_SSI3 31 262 - #define R9A07G054_PD_SRC 32 263 - #define R9A07G054_PD_USB0 33 264 - #define R9A07G054_PD_USB1 34 265 - #define R9A07G054_PD_USB_PHY 35 266 - #define R9A07G054_PD_ETHER0 36 267 - #define R9A07G054_PD_ETHER1 37 268 - #define R9A07G054_PD_I2C0 38 269 - #define R9A07G054_PD_I2C1 39 270 - #define R9A07G054_PD_I2C2 40 271 - #define R9A07G054_PD_I2C3 41 272 - #define R9A07G054_PD_SCIF0 42 273 - #define R9A07G054_PD_SCIF1 43 274 - #define R9A07G054_PD_SCIF2 44 275 - #define R9A07G054_PD_SCIF3 45 276 - #define R9A07G054_PD_SCIF4 46 277 - #define R9A07G054_PD_SCI0 47 278 - #define R9A07G054_PD_SCI1 48 279 - #define R9A07G054_PD_IRDA 49 280 - #define R9A07G054_PD_RSPI0 50 281 - #define R9A07G054_PD_RSPI1 51 282 - #define R9A07G054_PD_RSPI2 52 283 - #define R9A07G054_PD_CANFD 53 284 - #define R9A07G054_PD_ADC 54 285 - #define R9A07G054_PD_TSU 55 286 - 287 229 #endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
-71
include/dt-bindings/clock/r9a08g045-cpg.h
··· 239 239 #define R9A08G045_I3C_PRESETN 92 240 240 #define R9A08G045_VBAT_BRESETN 93 241 241 242 - /* Power domain IDs. */ 243 - #define R9A08G045_PD_ALWAYS_ON 0 244 - #define R9A08G045_PD_GIC 1 245 - #define R9A08G045_PD_IA55 2 246 - #define R9A08G045_PD_MHU 3 247 - #define R9A08G045_PD_CORESIGHT 4 248 - #define R9A08G045_PD_SYC 5 249 - #define R9A08G045_PD_DMAC 6 250 - #define R9A08G045_PD_GTM0 7 251 - #define R9A08G045_PD_GTM1 8 252 - #define R9A08G045_PD_GTM2 9 253 - #define R9A08G045_PD_GTM3 10 254 - #define R9A08G045_PD_GTM4 11 255 - #define R9A08G045_PD_GTM5 12 256 - #define R9A08G045_PD_GTM6 13 257 - #define R9A08G045_PD_GTM7 14 258 - #define R9A08G045_PD_MTU 15 259 - #define R9A08G045_PD_POE3 16 260 - #define R9A08G045_PD_GPT 17 261 - #define R9A08G045_PD_POEGA 18 262 - #define R9A08G045_PD_POEGB 19 263 - #define R9A08G045_PD_POEGC 20 264 - #define R9A08G045_PD_POEGD 21 265 - #define R9A08G045_PD_WDT0 22 266 - #define R9A08G045_PD_XSPI 23 267 - #define R9A08G045_PD_SDHI0 24 268 - #define R9A08G045_PD_SDHI1 25 269 - #define R9A08G045_PD_SDHI2 26 270 - #define R9A08G045_PD_SSI0 27 271 - #define R9A08G045_PD_SSI1 28 272 - #define R9A08G045_PD_SSI2 29 273 - #define R9A08G045_PD_SSI3 30 274 - #define R9A08G045_PD_SRC 31 275 - #define R9A08G045_PD_USB0 32 276 - #define R9A08G045_PD_USB1 33 277 - #define R9A08G045_PD_USB_PHY 34 278 - #define R9A08G045_PD_ETHER0 35 279 - #define R9A08G045_PD_ETHER1 36 280 - #define R9A08G045_PD_I2C0 37 281 - #define R9A08G045_PD_I2C1 38 282 - #define R9A08G045_PD_I2C2 39 283 - #define R9A08G045_PD_I2C3 40 284 - #define R9A08G045_PD_SCIF0 41 285 - #define R9A08G045_PD_SCIF1 42 286 - #define R9A08G045_PD_SCIF2 43 287 - #define R9A08G045_PD_SCIF3 44 288 - #define R9A08G045_PD_SCIF4 45 289 - #define R9A08G045_PD_SCIF5 46 290 - #define R9A08G045_PD_SCI0 47 291 - #define R9A08G045_PD_SCI1 48 292 - #define R9A08G045_PD_IRDA 49 293 - #define R9A08G045_PD_RSPI0 50 294 - #define R9A08G045_PD_RSPI1 51 295 - #define R9A08G045_PD_RSPI2 52 296 - #define R9A08G045_PD_RSPI3 53 297 - #define R9A08G045_PD_RSPI4 54 298 - #define R9A08G045_PD_CANFD 55 299 - #define R9A08G045_PD_ADC 56 300 - #define R9A08G045_PD_TSU 57 301 - #define R9A08G045_PD_OCTA 58 302 - #define R9A08G045_PD_PDM 59 303 - #define R9A08G045_PD_PCI 60 304 - #define R9A08G045_PD_SPDIF 61 305 - #define R9A08G045_PD_I3C 62 306 - #define R9A08G045_PD_VBAT 63 307 - 308 - #define R9A08G045_PD_DDR 64 309 - #define R9A08G045_PD_TZCDDR 65 310 - #define R9A08G045_PD_OTFDE_DDR 66 311 - #define R9A08G045_PD_RTC 67 312 - 313 242 #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */