Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: Add TI ADS131M0x ADC driver
Add a new IIO ADC driver for Texas Instruments ADS131M0x devices
(ADS131M02/03/04/06/08). These are 24-bit, up to 64 kSPS, simultaneous-
sampling delta-sigma ADCs accessed via SPI.
Highlights:
- Supports 2/3/4/6/8-channel variants with per-channel RAW and SCALE.
- Implements device-required full-duplex fixed-frame transfers.
- Handles both input and output CRC
Note: Despite the almost identical name, this hardware is not
compatible with the ADS131E0x series handled by
drivers/iio/adc/ti-ads131e08.c.
Signed-off-by: David Jander <david@protonic.nl>
Co-developed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
David Jander
and committed by
Jonathan Cameron
4aa91223
1ca733e8
+980
+11
drivers/iio/adc/Kconfig
+11
drivers/iio/adc/Kconfig
···
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This driver can also be built as a module. If so, the module will be
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called ti-ads131e08.
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config TI_ADS131M02
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tristate "Texas Instruments ADS131M02"
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depends on SPI && REGULATOR
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select CRC_ITU_T
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help
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Say yes here to get support for Texas Instruments ADS131M02, ADS131M03,
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ADS131M04, ADS131M06 and ADS131M08 chips.
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This driver can also be built as a module. If so, the module will be
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called ti-ads131m02.
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config TI_ADS7138
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tristate "Texas Instruments ADS7128 and ADS7138 ADC driver"
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depends on I2C
+1
drivers/iio/adc/Makefile
+1
drivers/iio/adc/Makefile
···
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obj-$(CONFIG_TI_ADS124S08) += ti-ads124s08.o
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obj-$(CONFIG_TI_ADS1298) += ti-ads1298.o
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obj-$(CONFIG_TI_ADS131E08) += ti-ads131e08.o
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+
obj-$(CONFIG_TI_ADS131M02) += ti-ads131m02.o
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obj-$(CONFIG_TI_ADS7138) += ti-ads7138.o
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obj-$(CONFIG_TI_ADS7924) += ti-ads7924.o
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obj-$(CONFIG_TI_ADS7950) += ti-ads7950.o
+968
drivers/iio/adc/ti-ads131m02.c
+968
drivers/iio/adc/ti-ads131m02.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
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+
/*
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* Driver for Texas Instruments ADS131M02 family ADC chips.
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*
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* Copyright (C) 2024 Protonic Holland
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* Copyright (C) 2025 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
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*
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* Primary Datasheet Reference (used for citations):
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* ADS131M08 8-Channel, Simultaneously-Sampling, 24-Bit, Delta-Sigma ADC
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* Document SBAS950B, Revised February 2021
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* https://www.ti.com/lit/ds/symlink/ads131m08.pdf
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*/
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+
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/cleanup.h>
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#include <linux/clk.h>
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#include <linux/crc-itu-t.h>
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#include <linux/delay.h>
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#include <linux/dev_printk.h>
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#include <linux/device/devres.h>
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#include <linux/err.h>
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#include <linux/iio/iio.h>
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#include <linux/lockdep.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/unaligned.h>
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+
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/* Max channels supported by the largest variant in the family (ADS131M08) */
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#define ADS131M_MAX_CHANNELS 8
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+
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/* Section 6.7, t_REGACQ (min time after reset) is 5us */
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#define ADS131M_RESET_DELAY_US 5
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+
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#define ADS131M_WORD_SIZE_BYTES 3
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#define ADS131M_RESPONSE_WORDS 1
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#define ADS131M_CRC_WORDS 1
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+
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/*
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* SPI Frame word count calculation.
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* Frame = N channel words + 1 response word + 1 CRC word.
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* Word size depends on WLENGTH bits in MODE register (Default 24-bit).
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*/
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#define ADS131M_FRAME_WORDS(nch) \
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((nch) + ADS131M_RESPONSE_WORDS + ADS131M_CRC_WORDS)
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+
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/*
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* SPI Frame byte size calculation.
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* Assumes default word size of 24 bits (3 bytes).
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*/
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#define ADS131M_FRAME_BYTES(nch) \
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(ADS131M_FRAME_WORDS(nch) * ADS131M_WORD_SIZE_BYTES)
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+
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/*
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* Index calculation for the start byte of channel 'x' data within the RX buffer.
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* Assumes 24-bit words (3 bytes per word).
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* The received frame starts with the response word (e.g., STATUS register
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* content when NULL command was sent), followed by data for channels 0 to N-1,
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* and finally the output CRC word.
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* Response = index 0..2, Chan0 = index 3..5, Chan1 = index 6..8, ...
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* Index for ChanX = 3 (response) + x * 3 (channel data size).
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*/
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#define ADS131M_CHANNEL_INDEX(x) \
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((x) * ADS131M_WORD_SIZE_BYTES + ADS131M_WORD_SIZE_BYTES)
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+
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#define ADS131M_CMD_NULL 0x0000
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#define ADS131M_CMD_RESET 0x0011
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+
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#define ADS131M_CMD_ADDR_MASK GENMASK(11, 7)
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#define ADS131M_CMD_NUM_MASK GENMASK(6, 0)
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+
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#define ADS131M_CMD_RREG_OP 0xa000
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#define ADS131M_CMD_WREG_OP 0x6000
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+
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#define ADS131M_CMD_RREG(a, n) \
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(ADS131M_CMD_RREG_OP | \
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FIELD_PREP(ADS131M_CMD_ADDR_MASK, a) | \
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FIELD_PREP(ADS131M_CMD_NUM_MASK, n))
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#define ADS131M_CMD_WREG(a, n) \
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(ADS131M_CMD_WREG_OP | \
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FIELD_PREP(ADS131M_CMD_ADDR_MASK, a) | \
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FIELD_PREP(ADS131M_CMD_NUM_MASK, n))
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+
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/* STATUS Register (0x01h) bit definitions */
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#define ADS131M_STATUS_CRC_ERR BIT(12) /* Input CRC error */
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+
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#define ADS131M_REG_MODE 0x02
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#define ADS131M_MODE_RX_CRC_EN BIT(12) /* Enable Input CRC */
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#define ADS131M_MODE_CRC_TYPE_ANSI BIT(11) /* 0 = CCITT, 1 = ANSI */
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#define ADS131M_MODE_RESET_FLAG BIT(10)
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+
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#define ADS131M_REG_CLOCK 0x03
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#define ADS131M_CLOCK_XTAL_DIS BIT(7)
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#define ADS131M_CLOCK_EXTREF_EN BIT(6)
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/* 1.2V internal reference, in millivolts, for IIO_VAL_FRACTIONAL_LOG2 */
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#define ADS131M_VREF_INTERNAL_mV 1200
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/* 24-bit resolution */
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#define ADS131M_RESOLUTION_BITS 24
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/* Signed data uses (RESOLUTION_BITS - 1) magnitude bits */
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#define ADS131M_CODE_BITS (ADS131M_RESOLUTION_BITS - 1)
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/* External ref FSR = Vref * 0.96 */
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#define ADS131M_EXTREF_SCALE_NUM 96
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#define ADS131M_EXTREF_SCALE_DEN 100
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+
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struct ads131m_configuration {
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const struct iio_chan_spec *channels;
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const char *name;
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u16 reset_ack;
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u8 num_channels;
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u8 supports_extref:1;
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u8 supports_xtal:1;
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};
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+
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struct ads131m_priv {
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struct iio_dev *indio_dev;
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struct spi_device *spi;
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const struct ads131m_configuration *config;
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+
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bool use_external_ref;
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int scale_val;
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int scale_val2;
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+
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struct spi_transfer xfer;
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struct spi_message msg;
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+
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/*
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* Protects the shared tx_buffer and rx_buffer. More importantly,
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* this serializes all SPI communication to ensure the atomicity
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* of multi-cycle command sequences (like WREG, RREG, or RESET).
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*/
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struct mutex lock;
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+
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/* DMA-safe buffers should be placed at the end of the struct. */
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u8 tx_buffer[ADS131M_FRAME_BYTES(ADS131M_MAX_CHANNELS)]
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__aligned(IIO_DMA_MINALIGN);
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u8 rx_buffer[ADS131M_FRAME_BYTES(ADS131M_MAX_CHANNELS)];
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};
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+
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/**
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* ads131m_tx_frame_unlocked - Sends a command frame with Input CRC
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* @priv: Device private data structure.
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* @command: The 16-bit command to send (e.g., NULL, RREG, RESET).
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*
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* This function sends a command in Word 0, and its calculated 16-bit
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* CRC in Word 1, as required when Input CRC is enabled.
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*
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* Return: 0 on success, or a negative error code.
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*/
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static int ads131m_tx_frame_unlocked(struct ads131m_priv *priv, u32 command)
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+
{
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struct iio_dev *indio_dev = priv->indio_dev;
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u16 crc;
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+
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lockdep_assert_held(&priv->lock);
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+
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memset(priv->tx_buffer, 0, ADS131M_FRAME_BYTES(indio_dev->num_channels));
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+
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/* Word 0: 16-bit command, MSB-aligned in 24-bit word */
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put_unaligned_be16(command, &priv->tx_buffer[0]);
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+
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/* Word 1: Input CRC. Calculated over the 3 bytes of Word 0. */
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crc = crc_itu_t(0xffff, priv->tx_buffer, 3);
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put_unaligned_be16(crc, &priv->tx_buffer[3]);
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+
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return spi_sync(priv->spi, &priv->msg);
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}
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+
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/**
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* ads131m_rx_frame_unlocked - Receives a full SPI data frame.
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* @priv: Device private data structure.
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*
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* This function sends a NULL command (with its CRC) to clock out a
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* full SPI frame from the device (e.g., response + channel data + CRC).
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*
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* Return: 0 on success, or a negative error code.
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*/
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static int ads131m_rx_frame_unlocked(struct ads131m_priv *priv)
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{
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return ads131m_tx_frame_unlocked(priv, ADS131M_CMD_NULL);
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}
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+
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/**
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* ads131m_check_status_crc_err - Checks for an Input CRC error.
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* @priv: Device private data structure.
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*
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* Sends a NULL command to fetch the STATUS register and checks the
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* CRC_ERR bit. This is used to verify the integrity of the previous
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* command (like RREG or WREG).
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*
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* Return: 0 on success, -EIO if CRC_ERR bit is set.
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*/
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static int ads131m_check_status_crc_err(struct ads131m_priv *priv)
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{
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struct device *dev = &priv->spi->dev;
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u16 status;
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int ret;
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+
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lockdep_assert_held(&priv->lock);
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+
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ret = ads131m_rx_frame_unlocked(priv);
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if (ret < 0) {
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dev_err_ratelimited(dev,
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"SPI error on STATUS read for CRC check\n");
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return ret;
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}
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status = get_unaligned_be16(&priv->rx_buffer[0]);
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if (status & ADS131M_STATUS_CRC_ERR) {
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dev_err_ratelimited(dev,
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"Input CRC error reported in STATUS = 0x%04x\n",
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status);
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return -EIO;
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}
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+
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return 0;
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}
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+
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/**
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* ads131m_write_reg_unlocked - Writes a single register and verifies the ACK.
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* @priv: Device private data structure.
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* @reg: The 8-bit register address.
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* @val: The 16-bit value to write.
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*
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* This function performs the full 3-cycle WREG operation with Input CRC:
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* 1. (Cycle 1) Sends WREG command, data, and its calculated CRC.
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* 2. (Cycle 2) Sends NULL+CRC to retrieve the response from Cycle 1.
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* 3. Verifies the response is the correct ACK for the WREG.
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* 4. (Cycle 3) Sends NULL+CRC to retrieve STATUS and check for CRC_ERR.
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*
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* Return: 0 on success, or a negative error code.
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*/
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static int ads131m_write_reg_unlocked(struct ads131m_priv *priv, u8 reg, u16 val)
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+
{
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struct iio_dev *indio_dev = priv->indio_dev;
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u16 command, expected_ack, response, crc;
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struct device *dev = &priv->spi->dev;
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int ret_crc_err = 0;
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int ret;
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+
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lockdep_assert_held(&priv->lock);
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+
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command = ADS131M_CMD_WREG(reg, 0); /* n = 0 for 1 register */
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/*
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* Per Table 8-11, WREG response is: 010a aaaa ammm mmmm
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* For 1 reg (n = 0 -> m = 0): 010a aaaa a000 0000 = 0x4000 | (reg << 7)
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*/
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expected_ack = 0x4000 | (reg << 7);
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+
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/* Cycle 1: Send WREG Command + Data + Input CRC */
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+
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memset(priv->tx_buffer, 0, ADS131M_FRAME_BYTES(indio_dev->num_channels));
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+
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/* Word 0: WREG command, 1 reg (n = 0), MSB-aligned */
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put_unaligned_be16(command, &priv->tx_buffer[0]);
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+
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/* Word 1: Data, MSB-aligned */
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put_unaligned_be16(val, &priv->tx_buffer[3]);
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+
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/* Word 2: Input CRC. Calculated over Word 0 (Cmd) and Word 1 (Data). */
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crc = crc_itu_t(0xffff, priv->tx_buffer, 6);
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put_unaligned_be16(crc, &priv->tx_buffer[6]);
271
+
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/* Ignore the RX buffer (it's from the previous command) */
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ret = spi_sync(priv->spi, &priv->msg);
274
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if (ret < 0) {
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dev_err_ratelimited(dev, "SPI error on WREG (cycle 1)\n");
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return ret;
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}
278
+
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/* Cycle 2: Send NULL Command to get the WREG response */
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ret = ads131m_rx_frame_unlocked(priv);
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if (ret < 0) {
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dev_err_ratelimited(dev, "SPI error on WREG ACK (cycle 2)\n");
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return ret;
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+
}
285
+
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/*
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* Response is in the first 2 bytes of the RX buffer
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* (MSB-aligned 16-bit response)
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*/
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response = get_unaligned_be16(&priv->rx_buffer[0]);
291
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if (response != expected_ack) {
292
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dev_err_ratelimited(dev, "WREG(0x%02x) failed, expected ACK 0x%04x, got 0x%04x\n",
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reg, expected_ack, response);
294
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ret_crc_err = -EIO;
295
+
/*
296
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* Don't return yet, still need to do Cycle 3 to clear
297
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* any potential CRC_ERR flag from this failed command.
298
+
*/
299
+
}
300
+
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/*
302
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* Cycle 3: Check STATUS for Input CRC error.
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* This is necessary even if ACK was wrong, to clear the CRC_ERR flag.
304
+
*/
305
+
ret = ads131m_check_status_crc_err(priv);
306
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if (ret < 0)
307
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return ret;
308
+
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return ret_crc_err;
310
+
}
311
+
312
+
/**
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* ads131m_read_reg_unlocked - Reads a single register from the device.
314
+
* @priv: Device private data structure.
315
+
* @reg: The 8-bit register address.
316
+
* @val: Pointer to store the 16-bit register value.
317
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*
318
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* This function performs the full 3-cycle RREG operation with Input CRC:
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+
* 1. (Cycle 1) Sends the RREG command + Input CRC.
320
+
* 2. (Cycle 2) Sends NULL+CRC to retrieve the register data.
321
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* 3. (Cycle 3) Sends NULL+CRC to retrieve STATUS and check for CRC_ERR.
322
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*
323
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* Return: 0 on success, or a negative error code.
324
+
*/
325
+
static int ads131m_read_reg_unlocked(struct ads131m_priv *priv, u8 reg, u16 *val)
326
+
{
327
+
struct device *dev = &priv->spi->dev;
328
+
u16 command;
329
+
int ret;
330
+
331
+
lockdep_assert_held(&priv->lock);
332
+
333
+
command = ADS131M_CMD_RREG(reg, 0); /* n=0 for 1 register */
334
+
335
+
/*
336
+
* Cycle 1: Send RREG Command + Input CRC
337
+
* Ignore the RX buffer (it's from the previous command)
338
+
*/
339
+
ret = ads131m_tx_frame_unlocked(priv, command);
340
+
if (ret < 0) {
341
+
dev_err_ratelimited(dev, "SPI error on RREG (cycle 1)\n");
342
+
return ret;
343
+
}
344
+
345
+
/* Cycle 2: Send NULL Command to get the register data */
346
+
ret = ads131m_rx_frame_unlocked(priv);
347
+
if (ret < 0) {
348
+
dev_err_ratelimited(dev, "SPI error on RREG data (cycle 2)\n");
349
+
return ret;
350
+
}
351
+
352
+
/*
353
+
* Per datasheet, for a single reg read, the response is the data.
354
+
* It's in the first 2 bytes of the RX buffer (MSB-aligned 16-bit).
355
+
*/
356
+
*val = get_unaligned_be16(&priv->rx_buffer[0]);
357
+
358
+
/*
359
+
* Cycle 3: Check STATUS for Input CRC error.
360
+
* The RREG command does not execute if CRC is bad, but we read
361
+
* STATUS anyway to clear the flag in case it was set.
362
+
*/
363
+
return ads131m_check_status_crc_err(priv);
364
+
}
365
+
366
+
/**
367
+
* ads131m_rmw_reg - Reads, modifies, and writes a single register.
368
+
* @priv: Device private data structure.
369
+
* @reg: The 8-bit register address.
370
+
* @clear: Bitmask of bits to clear.
371
+
* @set: Bitmask of bits to set.
372
+
*
373
+
* This function performs an atomic read-modify-write operation on a register.
374
+
* It reads the register, applies the clear and set masks, and writes
375
+
* the new value back if it has changed.
376
+
*
377
+
* Return: 0 on success, or a negative error code.
378
+
*/
379
+
static int ads131m_rmw_reg(struct ads131m_priv *priv, u8 reg, u16 clear, u16 set)
380
+
{
381
+
u16 old_val, new_val;
382
+
int ret;
383
+
384
+
guard(mutex)(&priv->lock);
385
+
386
+
ret = ads131m_read_reg_unlocked(priv, reg, &old_val);
387
+
if (ret < 0)
388
+
return ret;
389
+
390
+
new_val = (old_val & ~clear) | set;
391
+
if (new_val == old_val)
392
+
return 0;
393
+
394
+
return ads131m_write_reg_unlocked(priv, reg, new_val);
395
+
}
396
+
397
+
/**
398
+
* ads131m_verify_output_crc - Verifies the CRC of the received SPI frame.
399
+
* @priv: Device private data structure.
400
+
*
401
+
* This function calculates the CRC-16-CCITT (Poly 0x1021, Seed 0xFFFF) over
402
+
* the received response and channel data, and compares it to the CRC word
403
+
* received at the end of the SPI frame.
404
+
*
405
+
* Return: 0 on success, -EIO on CRC mismatch.
406
+
*/
407
+
static int ads131m_verify_output_crc(struct ads131m_priv *priv)
408
+
{
409
+
struct iio_dev *indio_dev = priv->indio_dev;
410
+
struct device *dev = &priv->spi->dev;
411
+
u16 calculated_crc, received_crc;
412
+
size_t data_len;
413
+
414
+
lockdep_assert_held(&priv->lock);
415
+
416
+
/*
417
+
* Frame: [Response][Chan 0]...[Chan N-1][CRC Word]
418
+
* Data for CRC: [Response][Chan 0]...[Chan N-1]
419
+
* Data length = (N_channels + 1) * 3 bytes (at 24-bit word size)
420
+
*/
421
+
data_len = ADS131M_FRAME_BYTES(indio_dev->num_channels) - 3;
422
+
calculated_crc = crc_itu_t(0xffff, priv->rx_buffer, data_len);
423
+
424
+
/*
425
+
* The received 16-bit CRC is MSB-aligned in the last 24-bit word.
426
+
* We extract it from the first 2 bytes (BE) of that word.
427
+
*/
428
+
received_crc = get_unaligned_be16(&priv->rx_buffer[data_len]);
429
+
if (calculated_crc != received_crc) {
430
+
dev_err_ratelimited(dev, "Output CRC error. Got %04x, expected %04x\n",
431
+
received_crc, calculated_crc);
432
+
return -EIO;
433
+
}
434
+
435
+
return 0;
436
+
}
437
+
438
+
/**
439
+
* ads131m_adc_read - Reads channel data, checks input and output CRCs.
440
+
* @priv: Device private data structure.
441
+
* @channel: The channel number to read.
442
+
* @val: Pointer to store the raw 24-bit value.
443
+
*
444
+
* This function sends a NULL command (with Input CRC) to retrieve data.
445
+
* It checks the received STATUS word for any Input CRC errors from the
446
+
* previous command, and then verifies the Output CRC of the current
447
+
* data frame.
448
+
*
449
+
* Return: 0 on success, or a negative error code.
450
+
*/
451
+
static int ads131m_adc_read(struct ads131m_priv *priv, u8 channel, s32 *val)
452
+
{
453
+
struct device *dev = &priv->spi->dev;
454
+
u16 status;
455
+
int ret;
456
+
u8 *buf;
457
+
458
+
guard(mutex)(&priv->lock);
459
+
460
+
/* Send NULL command + Input CRC, and receive data frame */
461
+
ret = ads131m_rx_frame_unlocked(priv);
462
+
if (ret < 0)
463
+
return ret;
464
+
465
+
/*
466
+
* Check STATUS for Input CRC error from the previous command frame.
467
+
* Note: the STATUS word belongs to the frame before this NULL command.
468
+
*/
469
+
status = get_unaligned_be16(&priv->rx_buffer[0]);
470
+
if (status & ADS131M_STATUS_CRC_ERR) {
471
+
dev_err_ratelimited(dev,
472
+
"Previous input CRC error reported in STATUS (0x%04x)\n",
473
+
status);
474
+
}
475
+
476
+
ret = ads131m_verify_output_crc(priv);
477
+
if (ret < 0)
478
+
return ret;
479
+
480
+
buf = &priv->rx_buffer[ADS131M_CHANNEL_INDEX(channel)];
481
+
*val = sign_extend32(get_unaligned_be24(buf), ADS131M_CODE_BITS);
482
+
483
+
return 0;
484
+
}
485
+
486
+
static int ads131m_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *channel,
487
+
int *val, int *val2, long mask)
488
+
{
489
+
struct ads131m_priv *priv = iio_priv(indio_dev);
490
+
int ret;
491
+
492
+
switch (mask) {
493
+
case IIO_CHAN_INFO_RAW:
494
+
ret = ads131m_adc_read(priv, channel->channel, val);
495
+
if (ret)
496
+
return ret;
497
+
return IIO_VAL_INT;
498
+
case IIO_CHAN_INFO_SCALE:
499
+
*val = priv->scale_val;
500
+
*val2 = priv->scale_val2;
501
+
502
+
return IIO_VAL_FRACTIONAL;
503
+
default:
504
+
return -EINVAL;
505
+
}
506
+
}
507
+
508
+
#define ADS131M_VOLTAGE_CHANNEL(num) \
509
+
{ \
510
+
.type = IIO_VOLTAGE, \
511
+
.differential = 1, \
512
+
.indexed = 1, \
513
+
.channel = (num), \
514
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
515
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
516
+
}
517
+
518
+
static const struct iio_chan_spec ads131m02_channels[] = {
519
+
ADS131M_VOLTAGE_CHANNEL(0),
520
+
ADS131M_VOLTAGE_CHANNEL(1),
521
+
};
522
+
523
+
static const struct iio_chan_spec ads131m03_channels[] = {
524
+
ADS131M_VOLTAGE_CHANNEL(0),
525
+
ADS131M_VOLTAGE_CHANNEL(1),
526
+
ADS131M_VOLTAGE_CHANNEL(2),
527
+
};
528
+
529
+
static const struct iio_chan_spec ads131m04_channels[] = {
530
+
ADS131M_VOLTAGE_CHANNEL(0),
531
+
ADS131M_VOLTAGE_CHANNEL(1),
532
+
ADS131M_VOLTAGE_CHANNEL(2),
533
+
ADS131M_VOLTAGE_CHANNEL(3),
534
+
};
535
+
536
+
static const struct iio_chan_spec ads131m06_channels[] = {
537
+
ADS131M_VOLTAGE_CHANNEL(0),
538
+
ADS131M_VOLTAGE_CHANNEL(1),
539
+
ADS131M_VOLTAGE_CHANNEL(2),
540
+
ADS131M_VOLTAGE_CHANNEL(3),
541
+
ADS131M_VOLTAGE_CHANNEL(4),
542
+
ADS131M_VOLTAGE_CHANNEL(5),
543
+
};
544
+
545
+
static const struct iio_chan_spec ads131m08_channels[] = {
546
+
ADS131M_VOLTAGE_CHANNEL(0),
547
+
ADS131M_VOLTAGE_CHANNEL(1),
548
+
ADS131M_VOLTAGE_CHANNEL(2),
549
+
ADS131M_VOLTAGE_CHANNEL(3),
550
+
ADS131M_VOLTAGE_CHANNEL(4),
551
+
ADS131M_VOLTAGE_CHANNEL(5),
552
+
ADS131M_VOLTAGE_CHANNEL(6),
553
+
ADS131M_VOLTAGE_CHANNEL(7),
554
+
};
555
+
556
+
static const struct ads131m_configuration ads131m02_config = {
557
+
.channels = ads131m02_channels,
558
+
.num_channels = ARRAY_SIZE(ads131m02_channels),
559
+
.reset_ack = 0xff22,
560
+
.name = "ads131m02",
561
+
};
562
+
563
+
static const struct ads131m_configuration ads131m03_config = {
564
+
.channels = ads131m03_channels,
565
+
.num_channels = ARRAY_SIZE(ads131m03_channels),
566
+
.reset_ack = 0xff23,
567
+
.name = "ads131m03",
568
+
};
569
+
570
+
static const struct ads131m_configuration ads131m04_config = {
571
+
.channels = ads131m04_channels,
572
+
.num_channels = ARRAY_SIZE(ads131m04_channels),
573
+
.reset_ack = 0xff24,
574
+
.name = "ads131m04",
575
+
};
576
+
577
+
static const struct ads131m_configuration ads131m06_config = {
578
+
.channels = ads131m06_channels,
579
+
.num_channels = ARRAY_SIZE(ads131m06_channels),
580
+
.reset_ack = 0xff26,
581
+
.supports_extref = true,
582
+
.supports_xtal = true,
583
+
.name = "ads131m06",
584
+
};
585
+
586
+
static const struct ads131m_configuration ads131m08_config = {
587
+
.channels = ads131m08_channels,
588
+
.num_channels = ARRAY_SIZE(ads131m08_channels),
589
+
.reset_ack = 0xff28,
590
+
.supports_extref = true,
591
+
.supports_xtal = true,
592
+
.name = "ads131m08",
593
+
};
594
+
595
+
static const struct iio_info ads131m_info = {
596
+
.read_raw = ads131m_read_raw,
597
+
};
598
+
599
+
/*
600
+
* Prepares the reusable SPI message structure for a full-duplex transfer.
601
+
* The ADS131M requires sending a command frame while simultaneously
602
+
* receiving the response/data frame from the previous command cycle.
603
+
*
604
+
* This message is optimized for the primary data acquisition workflow:
605
+
* sending a single-word command (like NULL) and receiving a full data
606
+
* frame (Response + N*Channels + CRC).
607
+
*
608
+
* This message is sized for a full data frame and is reused for all
609
+
* command/data cycles. The driver does not implement variable-length SPI
610
+
* messages.
611
+
*
612
+
* Return: 0 on success, or a negative error code.
613
+
*/
614
+
static int ads131m_prepare_message(struct ads131m_priv *priv)
615
+
{
616
+
struct iio_dev *indio_dev = priv->indio_dev;
617
+
struct device *dev = &priv->spi->dev;
618
+
int ret;
619
+
620
+
priv->xfer.tx_buf = priv->tx_buffer;
621
+
priv->xfer.rx_buf = priv->rx_buffer;
622
+
priv->xfer.len = ADS131M_FRAME_BYTES(indio_dev->num_channels);
623
+
spi_message_init_with_transfers(&priv->msg, &priv->xfer, 1);
624
+
625
+
ret = devm_spi_optimize_message(dev, priv->spi, &priv->msg);
626
+
if (ret)
627
+
return dev_err_probe(dev, ret, "failed to optimize SPI message\n");
628
+
629
+
return 0;
630
+
}
631
+
632
+
/**
633
+
* ads131m_hw_reset - Pulses the optional hardware reset.
634
+
* @priv: Device private data structure.
635
+
* @rstc: Reset control for the /RESET line.
636
+
*
637
+
* Pulses the /RESET line to perform a hardware reset and waits the
638
+
* required t_REGACQ time for the device to be ready.
639
+
*
640
+
* Return: 0 on success, or a negative error code.
641
+
*/
642
+
static int ads131m_hw_reset(struct ads131m_priv *priv,
643
+
struct reset_control *rstc)
644
+
{
645
+
struct device *dev = &priv->spi->dev;
646
+
int ret;
647
+
648
+
/*
649
+
* Manually pulse the reset line using the framework.
650
+
* The reset-gpio provider does not implement the .reset op,
651
+
* so we must use .assert and .deassert.
652
+
*/
653
+
ret = reset_control_assert(rstc);
654
+
if (ret)
655
+
return dev_err_probe(dev, ret, "Failed to assert reset\n");
656
+
657
+
/* Datasheet: Hold /RESET low for > 2 f_CLKIN cycles. 1us is ample. */
658
+
fsleep(1);
659
+
660
+
ret = reset_control_deassert(rstc);
661
+
if (ret < 0)
662
+
return dev_err_probe(dev, ret, "Failed to deassert reset\n");
663
+
664
+
/* Wait t_REGACQ (5us) for registers to be accessible */
665
+
fsleep(ADS131M_RESET_DELAY_US);
666
+
667
+
return 0;
668
+
}
669
+
670
+
/**
671
+
* ads131m_sw_reset - Issues a software RESET and verifies ACK.
672
+
* @priv: Device private data structure.
673
+
*
674
+
* This function sends a RESET command (with Input CRC), waits t_REGACQ,
675
+
* reads back the RESET ACK, and then sends a final NULL to check for
676
+
* any input CRC errors.
677
+
*
678
+
* Return: 0 on success, or a negative error code.
679
+
*/
680
+
static int ads131m_sw_reset(struct ads131m_priv *priv)
681
+
{
682
+
u16 expected_ack = priv->config->reset_ack;
683
+
struct device *dev = &priv->spi->dev;
684
+
u16 response;
685
+
int ret;
686
+
687
+
guard(mutex)(&priv->lock);
688
+
689
+
ret = ads131m_tx_frame_unlocked(priv, ADS131M_CMD_RESET);
690
+
if (ret < 0)
691
+
return dev_err_probe(dev, ret, "Failed to send RESET command\n");
692
+
693
+
/* Wait t_REGACQ (5us) for device to be ready after reset */
694
+
fsleep(ADS131M_RESET_DELAY_US);
695
+
696
+
/* Cycle 2: Send NULL + CRC to retrieve the response to the RESET */
697
+
ret = ads131m_rx_frame_unlocked(priv);
698
+
if (ret < 0)
699
+
return dev_err_probe(dev, ret, "Failed to read RESET ACK\n");
700
+
701
+
response = get_unaligned_be16(&priv->rx_buffer[0]);
702
+
703
+
/* Check against the device-specific ACK value */
704
+
if (response != expected_ack)
705
+
return dev_err_probe(dev, -EIO,
706
+
"RESET ACK mismatch, got 0x%04x, expected 0x%04x\n",
707
+
response, expected_ack);
708
+
709
+
/* Cycle 3: Check STATUS for Input CRC error on the RESET command. */
710
+
return ads131m_check_status_crc_err(priv);
711
+
}
712
+
713
+
/**
714
+
* ads131m_reset - Resets the device using hardware or software.
715
+
* @priv: Device private data structure.
716
+
* @rstc: Optional reset control, or NULL for software reset.
717
+
*
718
+
* This function performs a hardware reset if supported (rstc provided),
719
+
* otherwise it issues a software RESET command via SPI.
720
+
*
721
+
* Note: The software reset path also validates the device's reset
722
+
* acknowledgment against the expected ID for the compatible string.
723
+
* The hardware reset path bypasses this ID check.
724
+
*
725
+
* Return: 0 on success, or a negative error code.
726
+
*/
727
+
static int ads131m_reset(struct ads131m_priv *priv, struct reset_control *rstc)
728
+
{
729
+
if (rstc)
730
+
return ads131m_hw_reset(priv, rstc);
731
+
732
+
return ads131m_sw_reset(priv);
733
+
}
734
+
735
+
static int ads131m_power_init(struct ads131m_priv *priv)
736
+
{
737
+
static const char * const supply_ids[] = { "avdd", "dvdd" };
738
+
struct device *dev = &priv->spi->dev;
739
+
int vref_uV;
740
+
int ret;
741
+
742
+
ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(supply_ids), supply_ids);
743
+
if (ret < 0)
744
+
return dev_err_probe(dev, ret, "failed to enable regulators\n");
745
+
746
+
/* Default to Internal 1.2V reference: 1200mV / 2^23 */
747
+
priv->scale_val = ADS131M_VREF_INTERNAL_mV;
748
+
priv->scale_val2 = BIT(ADS131M_CODE_BITS);
749
+
750
+
if (!priv->config->supports_extref)
751
+
return 0;
752
+
753
+
ret = devm_regulator_get_enable_read_voltage(dev, "refin");
754
+
if (ret < 0 && ret != -ENODEV)
755
+
return dev_err_probe(dev, ret, "failed to get refin supply\n");
756
+
757
+
if (ret == 0)
758
+
return dev_err_probe(dev, -EINVAL, "refin supply reports 0V\n");
759
+
760
+
if (ret == -ENODEV)
761
+
return 0;
762
+
763
+
vref_uV = ret;
764
+
765
+
/*
766
+
* External reference found: Scale(mV) = (vref_uV * 0.96) / 1000
767
+
* The denominator is 100 * 2^23 because of the 0.96 factor (96/100).
768
+
*/
769
+
priv->scale_val = div_s64((s64)vref_uV * ADS131M_EXTREF_SCALE_NUM, 1000);
770
+
priv->scale_val2 = ADS131M_EXTREF_SCALE_DEN * BIT(ADS131M_CODE_BITS);
771
+
priv->use_external_ref = true;
772
+
773
+
return 0;
774
+
}
775
+
776
+
/**
777
+
* ads131m_hw_init - Initialize the ADC hardware.
778
+
* @priv: Device private data structure.
779
+
* @rstc: Optional reset control, or NULL for software reset.
780
+
* @is_xtal: True if 'clock-names' is "xtal", false if "clkin".
781
+
*
782
+
* Return: 0 on success, or a negative error code.
783
+
*/
784
+
static int ads131m_hw_init(struct ads131m_priv *priv,
785
+
struct reset_control *rstc, bool is_xtal)
786
+
{
787
+
struct device *dev = &priv->spi->dev;
788
+
u16 mode_clear, mode_set;
789
+
int ret;
790
+
791
+
ret = ads131m_reset(priv, rstc);
792
+
if (ret < 0)
793
+
return ret;
794
+
795
+
/*
796
+
* Configure CLOCK register (0x03) based on DT properties.
797
+
* This register only needs configuration for 32-pin (M06/M08)
798
+
* variants, as the configurable bits (XTAL_DIS, EXTREF_EN)
799
+
* are reserved on 20-pin (M02/M03/M04) variants.
800
+
*/
801
+
if (priv->config->supports_xtal || priv->config->supports_extref) {
802
+
u16 clk_set = 0;
803
+
804
+
if (priv->config->supports_xtal && !is_xtal)
805
+
clk_set |= ADS131M_CLOCK_XTAL_DIS;
806
+
807
+
if (priv->config->supports_extref && priv->use_external_ref)
808
+
clk_set |= ADS131M_CLOCK_EXTREF_EN;
809
+
810
+
ret = ads131m_rmw_reg(priv, ADS131M_REG_CLOCK,
811
+
ADS131M_CLOCK_EXTREF_EN | ADS131M_CLOCK_XTAL_DIS,
812
+
clk_set);
813
+
if (ret < 0)
814
+
return dev_err_probe(dev, ret, "Failed to configure CLOCK register\n");
815
+
}
816
+
817
+
/*
818
+
* The RESET command sets all registers to default, which means:
819
+
* 1. The RESET bit (Bit 10) in MODE is set to '1'.
820
+
* 2. The CRC_TYPE bit (Bit 11) in MODE is '0' (CCITT).
821
+
* 3. The RX_CRC_EN bit (Bit 12) in MODE is '0' (Disabled).
822
+
*
823
+
* We must:
824
+
* 1. Clear the RESET bit.
825
+
* 2. Enable Input CRC (RX_CRC_EN).
826
+
* 3. Explicitly clear the ANSI CRC bit (for certainty).
827
+
*/
828
+
mode_clear = ADS131M_MODE_CRC_TYPE_ANSI | ADS131M_MODE_RESET_FLAG;
829
+
mode_set = ADS131M_MODE_RX_CRC_EN;
830
+
831
+
ret = ads131m_rmw_reg(priv, ADS131M_REG_MODE, mode_clear, mode_set);
832
+
if (ret < 0)
833
+
return dev_err_probe(dev, ret, "Failed to configure MODE register\n");
834
+
835
+
return 0;
836
+
}
837
+
838
+
/**
839
+
* ads131m_parse_clock - enable clock and detect "xtal" selection
840
+
* @priv: Device private data structure.
841
+
* @is_xtal: result flag (true if "xtal", false if default "clkin")
842
+
*
843
+
* Return: 0 on success, or a negative error code.
844
+
*/
845
+
static int ads131m_parse_clock(struct ads131m_priv *priv, bool *is_xtal)
846
+
{
847
+
struct device *dev = &priv->spi->dev;
848
+
struct clk *clk;
849
+
int ret;
850
+
851
+
clk = devm_clk_get_enabled(dev, NULL);
852
+
if (IS_ERR_OR_NULL(clk)) {
853
+
if (IS_ERR(clk))
854
+
ret = PTR_ERR(clk);
855
+
else
856
+
ret = -ENODEV;
857
+
858
+
return dev_err_probe(dev, ret, "clk get enabled failed\n");
859
+
}
860
+
861
+
ret = device_property_match_string(dev, "clock-names", "xtal");
862
+
if (ret > 0)
863
+
return dev_err_probe(dev, -EINVAL,
864
+
"'xtal' must be the only or first clock name");
865
+
866
+
if (ret < 0 && ret != -ENODATA)
867
+
return dev_err_probe(dev, ret,
868
+
"failed to read 'clock-names' property");
869
+
870
+
if (ret == 0 && !priv->config->supports_xtal)
871
+
return dev_err_probe(dev, -EINVAL,
872
+
"'xtal' clock not supported on this device");
873
+
874
+
*is_xtal = !ret;
875
+
876
+
return 0;
877
+
}
878
+
879
+
static int ads131m_probe(struct spi_device *spi)
880
+
{
881
+
const struct ads131m_configuration *config;
882
+
struct device *dev = &spi->dev;
883
+
struct reset_control *rstc;
884
+
struct iio_dev *indio_dev;
885
+
struct ads131m_priv *priv;
886
+
bool is_xtal;
887
+
int ret;
888
+
889
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
890
+
if (!indio_dev)
891
+
return -ENOMEM;
892
+
893
+
priv = iio_priv(indio_dev);
894
+
priv->indio_dev = indio_dev;
895
+
priv->spi = spi;
896
+
897
+
indio_dev->modes = INDIO_DIRECT_MODE;
898
+
indio_dev->info = &ads131m_info;
899
+
900
+
config = spi_get_device_match_data(spi);
901
+
902
+
priv->config = config;
903
+
indio_dev->name = config->name;
904
+
indio_dev->channels = config->channels;
905
+
indio_dev->num_channels = config->num_channels;
906
+
907
+
rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
908
+
if (IS_ERR(rstc))
909
+
return dev_err_probe(dev, PTR_ERR(rstc),
910
+
"Failed to get reset controller\n");
911
+
912
+
ret = devm_mutex_init(dev, &priv->lock);
913
+
if (ret < 0)
914
+
return ret;
915
+
916
+
ret = ads131m_prepare_message(priv);
917
+
if (ret < 0)
918
+
return ret;
919
+
920
+
ret = ads131m_power_init(priv);
921
+
if (ret < 0)
922
+
return ret;
923
+
924
+
/* Power must be applied and stable before the clock is enabled. */
925
+
ret = ads131m_parse_clock(priv, &is_xtal);
926
+
if (ret < 0)
927
+
return ret;
928
+
929
+
ret = ads131m_hw_init(priv, rstc, is_xtal);
930
+
if (ret < 0)
931
+
return ret;
932
+
933
+
return devm_iio_device_register(dev, indio_dev);
934
+
}
935
+
936
+
static const struct of_device_id ads131m_of_match[] = {
937
+
{ .compatible = "ti,ads131m02", .data = &ads131m02_config },
938
+
{ .compatible = "ti,ads131m03", .data = &ads131m03_config },
939
+
{ .compatible = "ti,ads131m04", .data = &ads131m04_config },
940
+
{ .compatible = "ti,ads131m06", .data = &ads131m06_config },
941
+
{ .compatible = "ti,ads131m08", .data = &ads131m08_config },
942
+
{ }
943
+
};
944
+
MODULE_DEVICE_TABLE(of, ads131m_of_match);
945
+
946
+
static const struct spi_device_id ads131m_id[] = {
947
+
{ "ads131m02", (kernel_ulong_t)&ads131m02_config },
948
+
{ "ads131m03", (kernel_ulong_t)&ads131m03_config },
949
+
{ "ads131m04", (kernel_ulong_t)&ads131m04_config },
950
+
{ "ads131m06", (kernel_ulong_t)&ads131m06_config },
951
+
{ "ads131m08", (kernel_ulong_t)&ads131m08_config },
952
+
{ }
953
+
};
954
+
MODULE_DEVICE_TABLE(spi, ads131m_id);
955
+
956
+
static struct spi_driver ads131m_driver = {
957
+
.driver = {
958
+
.name = "ads131m02",
959
+
.of_match_table = ads131m_of_match,
960
+
},
961
+
.probe = ads131m_probe,
962
+
.id_table = ads131m_id,
963
+
};
964
+
module_spi_driver(ads131m_driver);
965
+
966
+
MODULE_AUTHOR("David Jander <david@protonic.nl>");
967
+
MODULE_DESCRIPTION("Texas Instruments ADS131M02 ADC driver");
968
+
MODULE_LICENSE("GPL");