dt-bindings: clock: qcom: Add SM8750 GPU clocks

The SM8750 features a "traditional" GPU_CC block, much of which is
controlled through the GMU microcontroller. GPU_CC block requires the MX
and CX rail control and thus add the corresponding power-domains and
require-opps. Additionally, there's an separate GX_CC block, where
the GX GDSC is moved.

Update the bindings to accommodate for SM8750 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-1-78292b40b053@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Konrad Dybcio and committed by

Bjorn Andersson 1 month ago 4aeadf8a 4e36f8ab

+74

3 changed files

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Documentation

devicetree

bindings

clock

qcom,kaanapali-gxclkctl.yaml

qcom,sm8450-gpucc.yaml

include

dt-bindings

clock

qcom,sm8750-gpucc.h

Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml

··· 22 22 enum: 23 23 - qcom,glymur-gxclkctl 24 24 - qcom,kaanapali-gxclkctl 25 + - qcom,sm8750-gxclkctl 25 26 26 27 power-domains: 27 28 description:

+23

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

··· 8 8 9 9 maintainers: 10 10 - Konrad Dybcio <konradybcio@kernel.org> 11 + - Taniya Das <taniya.das@oss.qualcomm.com> 11 12 12 13 description: | 13 14 Qualcomm graphics clock control module provides the clocks, resets and power ··· 24 23 include/dt-bindings/clock/qcom,sm8550-gpucc.h 25 24 include/dt-bindings/reset/qcom,sm8450-gpucc.h 26 25 include/dt-bindings/reset/qcom,sm8650-gpucc.h 26 + include/dt-bindings/reset/qcom,sm8750-gpucc.h 27 27 include/dt-bindings/reset/qcom,x1e80100-gpucc.h 28 28 29 29 properties: ··· 39 37 - qcom,sm8475-gpucc 40 38 - qcom,sm8550-gpucc 41 39 - qcom,sm8650-gpucc 40 + - qcom,sm8750-gpucc 42 41 - qcom,x1e80100-gpucc 43 42 - qcom,x1p42100-gpucc 44 43 ··· 49 46 - description: GPLL0 main branch source 50 47 - description: GPLL0 div branch source 51 48 49 + power-domains: 50 + items: 51 + - description: A phandle to the MX power-domain 52 + - description: A phandle to the CX power-domain 53 + 54 + required-opps: 55 + items: 56 + - description: A phandle to an OPP node describing MX performance points 57 + - description: A phandle to an OPP node describing CX performance points 58 + 52 59 required: 53 60 - compatible 54 61 - clocks ··· 66 53 67 54 allOf: 68 55 - $ref: qcom,gcc.yaml# 56 + - if: 57 + properties: 58 + compatible: 59 + contains: 60 + enum: 61 + - qcom,sm8750-gpucc 62 + then: 63 + required: 64 + - power-domains 65 + - required-opps 69 66 70 67 unevaluatedProperties: false 71 68

+50

include/dt-bindings/clock/qcom,sm8750-gpucc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H 6 + #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H 7 + 8 + /* GPU_CC clocks */ 9 + #define GPU_CC_AHB_CLK 0 10 + #define GPU_CC_CB_CLK 1 11 + #define GPU_CC_CX_ACCU_SHIFT_CLK 2 12 + #define GPU_CC_CX_FF_CLK 3 13 + #define GPU_CC_CX_GMU_CLK 4 14 + #define GPU_CC_CXO_AON_CLK 5 15 + #define GPU_CC_CXO_CLK 6 16 + #define GPU_CC_DEMET_CLK 7 17 + #define GPU_CC_DPM_CLK 8 18 + #define GPU_CC_FF_CLK_SRC 9 19 + #define GPU_CC_FREQ_MEASURE_CLK 10 20 + #define GPU_CC_GMU_CLK_SRC 11 21 + #define GPU_CC_GX_ACCU_SHIFT_CLK 12 22 + #define GPU_CC_GX_ACD_AHB_FF_CLK 13 23 + #define GPU_CC_GX_AHB_FF_CLK 14 24 + #define GPU_CC_GX_GMU_CLK 15 25 + #define GPU_CC_GX_RCG_AHB_FF_CLK 16 26 + #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 27 + #define GPU_CC_HUB_AON_CLK 18 28 + #define GPU_CC_HUB_CLK_SRC 19 29 + #define GPU_CC_HUB_CX_INT_CLK 20 30 + #define GPU_CC_HUB_DIV_CLK_SRC 21 31 + #define GPU_CC_MEMNOC_GFX_CLK 22 32 + #define GPU_CC_PLL0 23 33 + #define GPU_CC_PLL0_OUT_EVEN 24 34 + #define GPU_CC_RSCC_HUB_AON_CLK 25 35 + #define GPU_CC_RSCC_XO_AON_CLK 26 36 + #define GPU_CC_SLEEP_CLK 27 37 + 38 + /* GPU_CC power domains */ 39 + #define GPU_CC_CX_GDSC 0 40 + 41 + /* GPU_CC resets */ 42 + #define GPU_CC_GPU_CC_CB_BCR 0 43 + #define GPU_CC_GPU_CC_CX_BCR 1 44 + #define GPU_CC_GPU_CC_FAST_HUB_BCR 2 45 + #define GPU_CC_GPU_CC_FF_BCR 3 46 + #define GPU_CC_GPU_CC_GMU_BCR 4 47 + #define GPU_CC_GPU_CC_GX_BCR 5 48 + #define GPU_CC_GPU_CC_XO_BCR 6 49 + 50 + #endif

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