Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Move FPU Guards From DML To DC - Part 2
[Why]
FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that
can manipulates floats. To do this properly, the FPU guards must be used
in a file that is not compiled as a FPU unit. If the guards are used in
a file that is a FPU unit, other sections in the file that aren't guarded
may be end up being compiled to use FPU operations.
[How]
Removed DC_FP_START and DC_FP_END.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rafal Ostrowski
and committed by
Alex Deucher
4bb2f072
3539437f
+484
-471
+22
-53
drivers/gpu/drm/amd/display/dc/dml2_0/Makefile
+22
-53
drivers/gpu/drm/amd/display/dc/dml2_0/Makefile
···
53
53
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/inc
54
54
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/
55
55
56
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag)
57
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_ccflags)
58
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper_fpu.o := $(dml2_ccflags)
59
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_ccflags)
60
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_ccflags)
61
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_ccflags)
62
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_ccflags)
63
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_ccflags)
64
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_ccflags)
56
+
# Add FPU flags to all dml2 files by default, remove NO_FPU flags.
57
+
# FPU flags step 1: Find all .c files in dal/dc/dml2_0 and it's subfolders
58
+
DML2_ABS_PATH := $(FULL_AMD_DISPLAY_PATH)/dc/dml2_0
59
+
DML2_C_FILES := $(shell find $(DML2_ABS_PATH) -name '*.c' -type f)
65
60
61
+
# FPU flags step 2: Convert to .o and make paths relative to $(AMDDALPATH)/dc/dml2_0/
62
+
DML2_RELATIVE_O_FILES := $(patsubst $(DML2_ABS_PATH)/%,dc/dml2_0/%,$(patsubst %.c,%.o,$(DML2_C_FILES)))
63
+
64
+
# FPU flags step 3: Apply FPU flags to all .o files from dal/dc/dml2_0 and it's subfolders
65
+
$(foreach obj,$(DML2_RELATIVE_O_FILES),$(eval CFLAGS_$(AMDDALPATH)/$(obj) := $(dml2_ccflags)))
66
+
$(foreach obj,$(DML2_RELATIVE_O_FILES),$(eval CFLAGS_REMOVE_$(AMDDALPATH)/$(obj) := $(dml2_rcflags)))
67
+
68
+
# FPU flags step 4: Replace CFLAGS per file for files with additional flags beyond dml2_ccflags and dml2_rcflags
69
+
CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag)
70
+
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag)
71
+
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag)
72
+
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_rcflags)
73
+
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_wrapper.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_rcflags)
67
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_rcflags)
68
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper_fpu.o := $(dml2_rcflags)
69
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_rcflags)
70
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_rcflags)
71
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_rcflags)
72
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_rcflags)
73
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_rcflags)
74
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_rcflags)
75
+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags)
76
+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags)
77
+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_ccflags)
78
+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_wrapper.o := $(dml2_ccflags)
75
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DML2 = display_mode_core.o display_mode_util.o dml2_wrapper_fpu.o dml2_wrapper.o \
77
81
dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \
···
84
80
AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2_0/,$(DML2))
85
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86
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AMD_DISPLAY_FILES += $(AMD_DAL_DML2)
87
-
88
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags)
89
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag)
90
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag)
91
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags)
92
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags)
93
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags)
94
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags)
95
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags)
96
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags)
97
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_ccflags)
98
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags)
99
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags)
100
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags)
101
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags)
102
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags)
103
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_ccflags)
104
-
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_ccflags)
105
-
106
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags)
107
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags)
108
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags)
109
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags)
110
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags)
111
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags)
112
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags)
113
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags)
114
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags)
115
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_rcflags)
116
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags)
117
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags)
118
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags)
119
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags)
120
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags)
121
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_rcflags)
122
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_rcflags)
123
83
124
84
DML21 := src/dml2_top/dml2_top_interfaces.o
125
85
DML21 += src/dml2_top/dml2_top_soc15.o
···
102
134
DML21 += src/dml2_standalone_libraries/lib_float_math.o
103
135
DML21 += dml21_translation_helper.o
104
136
DML21 += dml21_wrapper.o
137
+
DML21 += dml21_wrapper_fpu.o
105
138
DML21 += dml21_utils.o
106
139
107
140
AMD_DAL_DML21 = $(addprefix $(AMDDALPATH)/dc/dml2_0/dml21/,$(DML21))
+5
-374
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c
+5
-374
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c
···
9
9
#include "dml21_utils.h"
10
10
#include "dml21_translation_helper.h"
11
11
#include "dml2_dc_resource_mgmt.h"
12
+
#include "dml2_wrapper.h"
13
+
#include "dml2_wrapper_fpu.h"
14
+
#include "dml21_wrapper.h"
15
+
#include "dml21_wrapper_fpu.h"
12
16
#include "dc_fpu.h"
13
17
14
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#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED)
···
44
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return true;
45
41
}
46
42
47
-
static void dml21_populate_configuration_options(const struct dc *in_dc,
48
-
struct dml2_context *dml_ctx,
49
-
const struct dml2_configuration_options *config)
50
-
{
51
-
dml_ctx->config = *config;
52
-
53
-
/* UCLK P-State options */
54
-
if (in_dc->debug.dml21_force_pstate_method) {
55
-
dml_ctx->config.pmo.force_pstate_method_enable = true;
56
-
for (int i = 0; i < MAX_PIPES; i++)
57
-
dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i];
58
-
} else {
59
-
dml_ctx->config.pmo.force_pstate_method_enable = false;
60
-
}
61
-
}
62
-
63
-
static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)
64
-
{
65
-
66
-
dml_ctx->architecture = dml2_architecture_21;
67
-
68
-
dml21_populate_configuration_options(in_dc, dml_ctx, config);
69
-
70
-
DC_FP_START();
71
-
72
-
dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, &dml_ctx->config, in_dc);
73
-
74
-
dml2_initialize_instance(&dml_ctx->v21.dml_init);
75
-
76
-
DC_FP_END();
77
-
}
78
-
79
43
bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)
80
44
{
81
45
/* Allocate memory for initializing DML21 instance */
82
-
if (!dml21_allocate_memory(dml_ctx)) {
46
+
if (!dml21_allocate_memory(dml_ctx))
83
47
return false;
84
-
}
85
48
86
49
dml21_init(in_dc, *dml_ctx, config);
87
50
···
59
88
{
60
89
vfree(dml2->v21.dml_init.dml2_instance);
61
90
vfree(dml2->v21.mode_programming.programming);
62
-
}
63
-
64
-
static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,
65
-
struct dml2_context *in_ctx, unsigned int pipe_cnt)
66
-
{
67
-
unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0;
68
-
struct dml2_per_plane_programming *pln_prog = NULL;
69
-
struct dml2_per_stream_programming *stream_prog = NULL;
70
-
struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
71
-
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
72
-
int num_pipes;
73
-
unsigned int dml_phantom_prog_idx;
74
-
75
-
context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
76
-
77
-
/* copy global DCHUBBUB arbiter registers */
78
-
memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs));
79
-
80
-
/* legacy only */
81
-
context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64;
82
-
83
-
context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;
84
-
context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;
85
-
context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;
86
-
87
-
/* phantom's start after main planes */
88
-
dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes;
89
-
90
-
for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) {
91
-
pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
92
-
93
-
if (!pln_prog->plane_descriptor)
94
-
continue;
95
-
96
-
stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index];
97
-
num_dpps_required = pln_prog->num_dpps_required;
98
-
99
-
if (num_dpps_required == 0) {
100
-
continue;
101
-
}
102
-
num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
103
-
104
-
if (num_pipes <= 0)
105
-
continue;
106
-
107
-
/* program each pipe */
108
-
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
109
-
dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog);
110
-
111
-
if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) {
112
-
dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog);
113
-
}
114
-
}
115
-
116
-
/* copy per plane mcache allocation */
117
-
memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation));
118
-
if (pln_prog->phantom_plane.valid) {
119
-
memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx],
120
-
&pln_prog->phantom_plane.mcache_allocation,
121
-
sizeof(struct dml2_mcache_surface_allocation));
122
-
123
-
dml_phantom_prog_idx++;
124
-
}
125
-
}
126
-
127
-
/* assign global clocks */
128
-
context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
129
-
context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
130
-
if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) {
131
-
context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz =
132
-
in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000;
133
-
} else {
134
-
context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000;
135
-
}
136
-
137
-
if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) {
138
-
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
139
-
in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000;
140
-
} else {
141
-
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000;
142
-
}
143
-
144
-
/* get global mall allocation */
145
-
if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {
146
-
context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);
147
-
} else {
148
-
context->bw_ctx.bw.dcn.clk.num_ways = 0;
149
-
}
150
-
}
151
-
152
-
static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params)
153
-
{
154
-
int dc_plane_idx = 0;
155
-
int dml_prog_idx, stream_idx, plane_idx;
156
-
struct dml2_per_plane_programming *pln_prog = NULL;
157
-
158
-
for (stream_idx = 0; stream_idx < context->stream_count; stream_idx++) {
159
-
for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) {
160
-
dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].plane_states[plane_idx], context);
161
-
if (dml_prog_idx == INVALID) {
162
-
continue;
163
-
}
164
-
pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
165
-
mcache_params[dc_plane_idx].valid = pln_prog->mcache_allocation.valid;
166
-
mcache_params[dc_plane_idx].num_mcaches_plane0 = pln_prog->mcache_allocation.num_mcaches_plane0;
167
-
mcache_params[dc_plane_idx].num_mcaches_plane1 = pln_prog->mcache_allocation.num_mcaches_plane1;
168
-
mcache_params[dc_plane_idx].requires_dedicated_mall_mcache = pln_prog->mcache_allocation.requires_dedicated_mall_mcache;
169
-
mcache_params[dc_plane_idx].last_slice_sharing.plane0_plane1 = pln_prog->mcache_allocation.last_slice_sharing.plane0_plane1;
170
-
memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane0,
171
-
pln_prog->mcache_allocation.mcache_x_offsets_plane0,
172
-
sizeof(int) * (DML2_MAX_MCACHES + 1));
173
-
memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane1,
174
-
pln_prog->mcache_allocation.mcache_x_offsets_plane1,
175
-
sizeof(int) * (DML2_MAX_MCACHES + 1));
176
-
dc_plane_idx++;
177
-
}
178
-
}
179
-
}
180
-
181
-
static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
182
-
{
183
-
bool result = false;
184
-
struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming;
185
-
struct dc_mcache_params mcache_params[MAX_PLANES] = {0};
186
-
187
-
memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg));
188
-
memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));
189
-
memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out));
190
-
191
-
if (!context)
192
-
return true;
193
-
194
-
if (context->stream_count == 0) {
195
-
dml21_init_min_clocks_for_dc_state(dml_ctx, context);
196
-
dml21_build_fams2_programming(in_dc, context, dml_ctx);
197
-
return true;
198
-
}
199
-
200
-
/* scrub phantom's from current dc_state */
201
-
dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);
202
-
dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);
203
-
204
-
/* Populate stream, plane mappings and other fields in display config. */
205
-
result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);
206
-
if (!result)
207
-
return false;
208
-
209
-
DC_FP_START();
210
-
result = dml2_build_mode_programming(mode_programming);
211
-
DC_FP_END();
212
-
if (!result)
213
-
return false;
214
-
215
-
/* Check and map HW resources */
216
-
if (result && !dml_ctx->config.skip_hw_state_mapping) {
217
-
dml21_map_hw_resources(dml_ctx);
218
-
dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state);
219
-
/* if subvp phantoms are present, expand them into dc context */
220
-
dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx);
221
-
222
-
if (in_dc->res_pool->funcs->program_mcache_pipe_config) {
223
-
//Prepare mcache params for each plane based on mcache output from DML
224
-
dml21_prepare_mcache_params(dml_ctx, context, mcache_params);
225
-
226
-
//populate mcache regs to each pipe
227
-
dml_ctx->config.callbacks.allocate_mcache(context, mcache_params);
228
-
}
229
-
}
230
-
231
-
/* Copy DML CLK, WM and REG outputs to bandwidth context */
232
-
if (result && !dml_ctx->config.skip_hw_state_mapping) {
233
-
dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count);
234
-
dml21_copy_clocks_to_dc_state(dml_ctx, context);
235
-
dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx);
236
-
dml21_build_fams2_programming(in_dc, context, dml_ctx);
237
-
}
238
-
239
-
return true;
240
-
}
241
-
242
-
static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
243
-
{
244
-
bool is_supported = false;
245
-
struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init;
246
-
struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support;
247
-
248
-
memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg));
249
-
memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));
250
-
memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out));
251
-
252
-
if (!context || context->stream_count == 0)
253
-
return true;
254
-
255
-
/* Scrub phantom's from current dc_state */
256
-
dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);
257
-
dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);
258
-
259
-
mode_support->dml2_instance = dml_init->dml2_instance;
260
-
dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);
261
-
dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming;
262
-
DC_FP_START();
263
-
is_supported = dml2_check_mode_supported(mode_support);
264
-
DC_FP_END();
265
-
if (!is_supported)
266
-
return false;
267
-
268
-
return true;
269
-
}
270
-
271
-
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,
272
-
enum dc_validate_mode validate_mode)
273
-
{
274
-
bool out = false;
275
-
276
-
/* Use dml21_check_mode_support for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */
277
-
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
278
-
out = dml21_check_mode_support(in_dc, context, dml_ctx);
279
-
else
280
-
out = dml21_mode_check_and_programming(in_dc, context, dml_ctx);
281
-
282
-
return out;
283
-
}
284
-
285
-
void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
286
-
{
287
-
unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index;
288
-
int num_pipes;
289
-
struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
290
-
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
291
-
292
-
struct dml2_per_plane_programming *pln_prog = NULL;
293
-
struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL;
294
-
struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals;
295
-
296
-
if (context->stream_count == 0) {
297
-
return;
298
-
}
299
-
300
-
memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out));
301
-
l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance;
302
-
303
-
/* phantom's start after main planes */
304
-
dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes;
305
-
306
-
/* Build mcache programming parameters per plane per pipe */
307
-
for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) {
308
-
pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
309
-
310
-
mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx];
311
-
memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
312
-
mcache_config->plane_descriptor = pln_prog->plane_descriptor;
313
-
mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx];
314
-
mcache_config->num_pipes = pln_prog->num_dpps_required;
315
-
l->build_mcache_programming_params.num_configurations++;
316
-
317
-
if (pln_prog->num_dpps_required == 0) {
318
-
continue;
319
-
}
320
-
321
-
num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
322
-
if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
323
-
dc_main_pipes[0]->plane_state == NULL)
324
-
continue;
325
-
326
-
/* get config for each pipe */
327
-
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
328
-
ASSERT(dc_main_pipes[dc_pipe_index]);
329
-
dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]);
330
-
}
331
-
332
-
/* get config for each phantom pipe */
333
-
if (pln_prog->phantom_plane.valid &&
334
-
dc_phantom_pipes[0] &&
335
-
dc_main_pipes[0]->stream &&
336
-
dc_phantom_pipes[0]->plane_state) {
337
-
mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx];
338
-
memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
339
-
mcache_config->plane_descriptor = pln_prog->plane_descriptor;
340
-
mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx];
341
-
mcache_config->num_pipes = pln_prog->num_dpps_required;
342
-
l->build_mcache_programming_params.num_configurations++;
343
-
344
-
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
345
-
ASSERT(dc_phantom_pipes[dc_pipe_index]);
346
-
dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]);
347
-
}
348
-
349
-
/* increment phantom index */
350
-
dml_phantom_prog_idx++;
351
-
}
352
-
}
353
-
354
-
/* Call to generate mcache programming per plane per pipe for the given display configuration */
355
-
dml2_build_mcache_programming(&l->build_mcache_programming_params);
356
-
357
-
/* get per plane per pipe mcache programming */
358
-
for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) {
359
-
pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
360
-
361
-
num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
362
-
if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
363
-
dc_main_pipes[0]->plane_state == NULL)
364
-
continue;
365
-
366
-
/* get config for each pipe */
367
-
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
368
-
ASSERT(dc_main_pipes[dc_pipe_index]);
369
-
if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) {
370
-
memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs,
371
-
l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index],
372
-
sizeof(struct dml2_hubp_pipe_mcache_regs));
373
-
}
374
-
}
375
-
376
-
/* get config for each phantom pipe */
377
-
if (pln_prog->phantom_plane.valid &&
378
-
dc_phantom_pipes[0] &&
379
-
dc_main_pipes[0]->stream &&
380
-
dc_phantom_pipes[0]->plane_state) {
381
-
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
382
-
ASSERT(dc_phantom_pipes[dc_pipe_index]);
383
-
if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) {
384
-
memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs,
385
-
l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index],
386
-
sizeof(struct dml2_hubp_pipe_mcache_regs));
387
-
}
388
-
}
389
-
/* increment phantom index */
390
-
dml_phantom_prog_idx++;
391
-
}
392
-
}
393
91
}
394
92
395
93
void dml21_copy(struct dml2_context *dst_dml_ctx,
···
86
446
87
447
dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming;
88
448
89
-
DC_FP_START();
90
-
91
449
/* need to initialize copied instance for internal references to be correct */
92
450
dml2_initialize_instance(&dst_dml_ctx->v21.dml_init);
93
-
94
-
DC_FP_END();
95
451
}
96
452
97
453
bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
···
100
464
dml21_copy(*dst_dml_ctx, src_dml_ctx);
101
465
102
466
return true;
103
-
}
104
-
105
-
void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)
106
-
{
107
-
dml21_init(in_dc, dml_ctx, config);
108
467
}
109
468
-30
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h
-30
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h
···
34
34
struct dml2_context *src_dml_ctx);
35
35
bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
36
36
struct dml2_context *src_dml_ctx);
37
-
void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config);
38
-
39
-
/**
40
-
* dml21_validate - Determines if a display configuration is supported or not.
41
-
* @in_dc: dc.
42
-
* @context: dc_state to be validated.
43
-
* @dml_ctx: dml21 context.
44
-
* @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX
45
-
* will not populate context.res_ctx.
46
-
*
47
-
* Based on fast_validate option internally would call:
48
-
*
49
-
* -dml21_mode_check_and_programming - for DC_VALIDATE_MODE_AND_PROGRAMMING option
50
-
* Calculates if dc_state can be supported on the input display
51
-
* configuration. If supported, generates the necessary HW
52
-
* programming for the new dc_state.
53
-
*
54
-
* -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option
55
-
* Calculates if dc_state can be supported for the input display
56
-
* config.
57
-
*
58
-
* Context: Two threads may not invoke this function concurrently unless they reference
59
-
* separate dc_states for validation.
60
-
* Return: True if mode is supported, false otherwise.
61
-
*/
62
-
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,
63
-
enum dc_validate_mode validate_mode);
64
-
65
-
/* Prepare hubp mcache_regs for hubp mcache ID and split coordinate programming */
66
-
void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);
67
37
68
38
/* Structure for inputting external SOCBB and DCNIP values for tool based debugging. */
69
39
struct socbb_ip_params_external {
+381
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
+381
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
//
3
+
// Copyright 2024 Advanced Micro Devices, Inc.
4
+
5
+
#include "dml2_internal_types.h"
6
+
#include "dml_top.h"
7
+
#include "dml2_core_dcn4_calcs.h"
8
+
#include "dml2_internal_shared_types.h"
9
+
#include "dml21_utils.h"
10
+
#include "dml21_translation_helper.h"
11
+
#include "dml2_dc_resource_mgmt.h"
12
+
#include "dml2_wrapper.h"
13
+
#include "dml2_wrapper_fpu.h"
14
+
#include "dml21_wrapper.h"
15
+
#include "dml21_wrapper_fpu.h"
16
+
17
+
#define INVALID -1
18
+
19
+
static void dml21_populate_configuration_options(const struct dc *in_dc,
20
+
struct dml2_context *dml_ctx,
21
+
const struct dml2_configuration_options *config)
22
+
{
23
+
dml_ctx->config = *config;
24
+
25
+
/* UCLK P-State options */
26
+
if (in_dc->debug.dml21_force_pstate_method) {
27
+
dml_ctx->config.pmo.force_pstate_method_enable = true;
28
+
for (int i = 0; i < MAX_PIPES; i++)
29
+
dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i];
30
+
} else {
31
+
dml_ctx->config.pmo.force_pstate_method_enable = false;
32
+
}
33
+
}
34
+
35
+
void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)
36
+
{
37
+
dml_ctx->architecture = dml2_architecture_21;
38
+
39
+
dml21_populate_configuration_options(in_dc, dml_ctx, config);
40
+
41
+
dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, &dml_ctx->config, in_dc);
42
+
43
+
dml2_initialize_instance(&dml_ctx->v21.dml_init);
44
+
}
45
+
46
+
void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)
47
+
{
48
+
dml21_init(in_dc, dml_ctx, config);
49
+
}
50
+
51
+
static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,
52
+
struct dml2_context *in_ctx, unsigned int pipe_cnt)
53
+
{
54
+
unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0;
55
+
struct dml2_per_plane_programming *pln_prog = NULL;
56
+
struct dml2_per_stream_programming *stream_prog = NULL;
57
+
struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
58
+
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
59
+
int num_pipes;
60
+
unsigned int dml_phantom_prog_idx;
61
+
62
+
context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
63
+
64
+
/* copy global DCHUBBUB arbiter registers */
65
+
memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs));
66
+
67
+
/* legacy only */
68
+
context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64;
69
+
70
+
context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;
71
+
context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;
72
+
context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;
73
+
74
+
/* phantom's start after main planes */
75
+
dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes;
76
+
77
+
for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) {
78
+
pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
79
+
80
+
if (!pln_prog->plane_descriptor)
81
+
continue;
82
+
83
+
stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index];
84
+
num_dpps_required = pln_prog->num_dpps_required;
85
+
86
+
if (num_dpps_required == 0) {
87
+
continue;
88
+
}
89
+
num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
90
+
91
+
if (num_pipes <= 0)
92
+
continue;
93
+
94
+
/* program each pipe */
95
+
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
96
+
dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog);
97
+
98
+
if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) {
99
+
dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog);
100
+
}
101
+
}
102
+
103
+
/* copy per plane mcache allocation */
104
+
memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation));
105
+
if (pln_prog->phantom_plane.valid) {
106
+
memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx],
107
+
&pln_prog->phantom_plane.mcache_allocation,
108
+
sizeof(struct dml2_mcache_surface_allocation));
109
+
110
+
dml_phantom_prog_idx++;
111
+
}
112
+
}
113
+
114
+
/* assign global clocks */
115
+
context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
116
+
context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
117
+
if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) {
118
+
context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz =
119
+
in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000;
120
+
} else {
121
+
context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000;
122
+
}
123
+
124
+
if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) {
125
+
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
126
+
in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000;
127
+
} else {
128
+
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000;
129
+
}
130
+
131
+
/* get global mall allocation */
132
+
if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {
133
+
context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);
134
+
} else {
135
+
context->bw_ctx.bw.dcn.clk.num_ways = 0;
136
+
}
137
+
}
138
+
139
+
static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params)
140
+
{
141
+
int dc_plane_idx = 0;
142
+
int dml_prog_idx, stream_idx, plane_idx;
143
+
struct dml2_per_plane_programming *pln_prog = NULL;
144
+
145
+
for (stream_idx = 0; stream_idx < context->stream_count; stream_idx++) {
146
+
for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) {
147
+
dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].plane_states[plane_idx], context);
148
+
if (dml_prog_idx == INVALID) {
149
+
continue;
150
+
}
151
+
pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
152
+
mcache_params[dc_plane_idx].valid = pln_prog->mcache_allocation.valid;
153
+
mcache_params[dc_plane_idx].num_mcaches_plane0 = pln_prog->mcache_allocation.num_mcaches_plane0;
154
+
mcache_params[dc_plane_idx].num_mcaches_plane1 = pln_prog->mcache_allocation.num_mcaches_plane1;
155
+
mcache_params[dc_plane_idx].requires_dedicated_mall_mcache = pln_prog->mcache_allocation.requires_dedicated_mall_mcache;
156
+
mcache_params[dc_plane_idx].last_slice_sharing.plane0_plane1 = pln_prog->mcache_allocation.last_slice_sharing.plane0_plane1;
157
+
memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane0,
158
+
pln_prog->mcache_allocation.mcache_x_offsets_plane0,
159
+
sizeof(int) * (DML2_MAX_MCACHES + 1));
160
+
memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane1,
161
+
pln_prog->mcache_allocation.mcache_x_offsets_plane1,
162
+
sizeof(int) * (DML2_MAX_MCACHES + 1));
163
+
dc_plane_idx++;
164
+
}
165
+
}
166
+
}
167
+
168
+
static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
169
+
{
170
+
bool is_supported = false;
171
+
struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init;
172
+
struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support;
173
+
174
+
memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg));
175
+
memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));
176
+
memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out));
177
+
178
+
if (!context || context->stream_count == 0)
179
+
return true;
180
+
181
+
/* Scrub phantom's from current dc_state */
182
+
dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);
183
+
dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);
184
+
185
+
mode_support->dml2_instance = dml_init->dml2_instance;
186
+
dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);
187
+
dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming;
188
+
189
+
is_supported = dml2_check_mode_supported(mode_support);
190
+
191
+
if (!is_supported)
192
+
return false;
193
+
194
+
return true;
195
+
}
196
+
197
+
static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
198
+
{
199
+
bool result = false;
200
+
struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming;
201
+
struct dc_mcache_params mcache_params[MAX_PLANES] = {0};
202
+
203
+
memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg));
204
+
memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));
205
+
memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out));
206
+
207
+
if (!context)
208
+
return true;
209
+
210
+
if (context->stream_count == 0) {
211
+
dml21_init_min_clocks_for_dc_state(dml_ctx, context);
212
+
dml21_build_fams2_programming(in_dc, context, dml_ctx);
213
+
return true;
214
+
}
215
+
216
+
/* scrub phantom's from current dc_state */
217
+
dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);
218
+
dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);
219
+
220
+
/* Populate stream, plane mappings and other fields in display config. */
221
+
result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);
222
+
if (!result)
223
+
return false;
224
+
225
+
result = dml2_build_mode_programming(mode_programming);
226
+
227
+
if (!result)
228
+
return false;
229
+
230
+
/* Check and map HW resources */
231
+
if (result && !dml_ctx->config.skip_hw_state_mapping) {
232
+
dml21_map_hw_resources(dml_ctx);
233
+
dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state);
234
+
/* if subvp phantoms are present, expand them into dc context */
235
+
dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx);
236
+
237
+
if (in_dc->res_pool->funcs->program_mcache_pipe_config) {
238
+
//Prepare mcache params for each plane based on mcache output from DML
239
+
dml21_prepare_mcache_params(dml_ctx, context, mcache_params);
240
+
241
+
//populate mcache regs to each pipe
242
+
dml_ctx->config.callbacks.allocate_mcache(context, mcache_params);
243
+
}
244
+
}
245
+
246
+
/* Copy DML CLK, WM and REG outputs to bandwidth context */
247
+
if (result && !dml_ctx->config.skip_hw_state_mapping) {
248
+
dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count);
249
+
dml21_copy_clocks_to_dc_state(dml_ctx, context);
250
+
dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx);
251
+
dml21_build_fams2_programming(in_dc, context, dml_ctx);
252
+
}
253
+
254
+
return true;
255
+
}
256
+
257
+
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,
258
+
enum dc_validate_mode validate_mode)
259
+
{
260
+
bool out = false;
261
+
262
+
/* Use dml21_check_mode_support for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */
263
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
264
+
out = dml21_check_mode_support(in_dc, context, dml_ctx);
265
+
else
266
+
out = dml21_mode_check_and_programming(in_dc, context, dml_ctx);
267
+
268
+
return out;
269
+
}
270
+
271
+
void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
272
+
{
273
+
unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index;
274
+
int num_pipes;
275
+
struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
276
+
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
277
+
278
+
struct dml2_per_plane_programming *pln_prog = NULL;
279
+
struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL;
280
+
struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals;
281
+
282
+
if (context->stream_count == 0) {
283
+
return;
284
+
}
285
+
286
+
memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out));
287
+
l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance;
288
+
289
+
/* phantom's start after main planes */
290
+
dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes;
291
+
292
+
/* Build mcache programming parameters per plane per pipe */
293
+
for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) {
294
+
pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
295
+
296
+
mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx];
297
+
memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
298
+
mcache_config->plane_descriptor = pln_prog->plane_descriptor;
299
+
mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx];
300
+
mcache_config->num_pipes = pln_prog->num_dpps_required;
301
+
l->build_mcache_programming_params.num_configurations++;
302
+
303
+
if (pln_prog->num_dpps_required == 0) {
304
+
continue;
305
+
}
306
+
307
+
num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
308
+
if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
309
+
dc_main_pipes[0]->plane_state == NULL)
310
+
continue;
311
+
312
+
/* get config for each pipe */
313
+
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
314
+
ASSERT(dc_main_pipes[dc_pipe_index]);
315
+
dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]);
316
+
}
317
+
318
+
/* get config for each phantom pipe */
319
+
if (pln_prog->phantom_plane.valid &&
320
+
dc_phantom_pipes[0] &&
321
+
dc_main_pipes[0]->stream &&
322
+
dc_phantom_pipes[0]->plane_state) {
323
+
mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx];
324
+
memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
325
+
mcache_config->plane_descriptor = pln_prog->plane_descriptor;
326
+
mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx];
327
+
mcache_config->num_pipes = pln_prog->num_dpps_required;
328
+
l->build_mcache_programming_params.num_configurations++;
329
+
330
+
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
331
+
ASSERT(dc_phantom_pipes[dc_pipe_index]);
332
+
dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]);
333
+
}
334
+
335
+
/* increment phantom index */
336
+
dml_phantom_prog_idx++;
337
+
}
338
+
}
339
+
340
+
/* Call to generate mcache programming per plane per pipe for the given display configuration */
341
+
dml2_build_mcache_programming(&l->build_mcache_programming_params);
342
+
343
+
/* get per plane per pipe mcache programming */
344
+
for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) {
345
+
pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
346
+
347
+
num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
348
+
if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
349
+
dc_main_pipes[0]->plane_state == NULL)
350
+
continue;
351
+
352
+
/* get config for each pipe */
353
+
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
354
+
ASSERT(dc_main_pipes[dc_pipe_index]);
355
+
if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) {
356
+
memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs,
357
+
l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index],
358
+
sizeof(struct dml2_hubp_pipe_mcache_regs));
359
+
}
360
+
}
361
+
362
+
/* get config for each phantom pipe */
363
+
if (pln_prog->phantom_plane.valid &&
364
+
dc_phantom_pipes[0] &&
365
+
dc_main_pipes[0]->stream &&
366
+
dc_phantom_pipes[0]->plane_state) {
367
+
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
368
+
ASSERT(dc_phantom_pipes[dc_pipe_index]);
369
+
if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) {
370
+
memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs,
371
+
l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index],
372
+
sizeof(struct dml2_hubp_pipe_mcache_regs));
373
+
}
374
+
}
375
+
/* increment phantom index */
376
+
dml_phantom_prog_idx++;
377
+
}
378
+
}
379
+
}
380
+
381
+
+60
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h
+60
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h
···
1
+
// SPDX-License-Identifier: MIT
2
+
//
3
+
// Copyright 2024 Advanced Micro Devices, Inc.
4
+
5
+
#ifndef _DML21_WRAPPER_FPU_H_
6
+
#define _DML21_WRAPPER_FPU_H_
7
+
8
+
#include "os_types.h"
9
+
#include "dml_top_soc_parameter_types.h"
10
+
#include "dml_top_display_cfg_types.h"
11
+
12
+
struct dc;
13
+
struct dc_state;
14
+
struct dml2_configuration_options;
15
+
struct dml2_context;
16
+
enum dc_validate_mode;
17
+
18
+
/**
19
+
* dml21_init - Initialize DML21 context
20
+
* @in_dc: dc.
21
+
* @dml_ctx: DML21 context to initialize.
22
+
* @config: dml21 configuration options.
23
+
*
24
+
* Performs FPU-requiring initialization. Must be called with FPU protection.
25
+
*/
26
+
void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config);
27
+
28
+
/**
29
+
* dml21_validate - Determines if a display configuration is supported or not.
30
+
* @in_dc: dc.
31
+
* @context: dc_state to be validated.
32
+
* @dml_ctx: dml21 context.
33
+
* @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX
34
+
* will not populate context.res_ctx.
35
+
*
36
+
* Based on fast_validate option internally would call:
37
+
*
38
+
* -dml21_mode_check_and_programming - for DC_VALIDATE_MODE_AND_PROGRAMMING option
39
+
* Calculates if dc_state can be supported on the input display
40
+
* configuration. If supported, generates the necessary HW
41
+
* programming for the new dc_state.
42
+
*
43
+
* -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option
44
+
* Calculates if dc_state can be supported for the input display
45
+
* config.
46
+
*
47
+
* Context: Two threads may not invoke this function concurrently unless they reference
48
+
* separate dc_states for validation.
49
+
* Return: True if mode is supported, false otherwise.
50
+
*/
51
+
52
+
void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx,
53
+
const struct dml2_configuration_options *config);
54
+
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,
55
+
enum dc_validate_mode validate_mode);
56
+
57
+
/* Prepare hubp mcache_regs for hubp mcache ID and split coordinate programming */
58
+
void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);
59
+
60
+
#endif /* _DML21_WRAPPER_FPU_H_ */
+13
-8
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c
+13
-8
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c
···
6
6
*/
7
7
8
8
#include "dml2_internal_types.h"
9
+
#include "dml2_wrapper.h"
9
10
#include "dml2_wrapper_fpu.h"
11
+
#include "dml21_wrapper.h"
12
+
#include "dml21_wrapper_fpu.h"
13
+
14
+
#include "dc_fpu.h"
15
+
16
+
struct dml2_context *dml2_allocate_memory(void)
17
+
{
18
+
struct dml2_context *dml2;
19
+
20
+
DC_RUN_WITH_PREEMPTION_ENABLED(dml2 = vzalloc(sizeof(struct dml2_context)));
21
+
return dml2;
22
+
}
10
23
11
24
bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,
12
25
enum dc_validate_mode validate_mode)
···
36
23
return out;
37
24
}
38
25
39
-
DC_FP_START();
40
-
41
26
/* Use dml_validate_only for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */
42
27
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
43
28
out = dml2_validate_only(context, validate_mode);
44
29
else
45
30
out = dml2_validate_and_build_resource(in_dc, context, validate_mode);
46
-
47
-
DC_FP_END();
48
31
49
32
return out;
50
33
}
···
79
70
break;
80
71
}
81
72
82
-
DC_FP_START();
83
-
84
73
initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip);
85
74
86
75
initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);
87
76
88
77
initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states);
89
-
90
-
DC_FP_END();
91
78
}
92
79
93
80
bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
+3
-6
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c
+3
-6
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c
···
31
31
#include "dml2_translation_helper.h"
32
32
#include "dml2_mall_phantom.h"
33
33
#include "dml2_dc_resource_mgmt.h"
34
-
#include "dml21_wrapper.h"
34
+
#include "dml2_wrapper.h"
35
35
#include "dml2_wrapper_fpu.h"
36
+
#include "dml21_wrapper.h"
37
+
#include "dml21_wrapper_fpu.h"
36
38
37
39
void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)
38
40
{
···
546
544
if (dc->debug.override_odm_optimization) {
547
545
dml2->config.minimize_dispclk_using_odm = dc->debug.minimize_dispclk_using_odm;
548
546
}
549
-
}
550
-
551
-
inline struct dml2_context *dml2_allocate_memory(void)
552
-
{
553
-
return (struct dml2_context *) vzalloc(sizeof(struct dml2_context));
554
547
}
555
548
556
549
void dml2_destroy(struct dml2_context *dml2)