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drm/amd/display: Don't set 4to1MPC config dynamically

We were previously modifying the global dc->config.enable_4to1MPC
dynamically. These variables are meant as global configs, not to
by dynamically modified. Modifying them dynamically prevents us
from enabling/disabling functionality for debug purposes and can
easily lead to bad things since we're not operating on the current
state but on DC-wide variables.

Instead we should look at the existing split4mpc decision in
dcn20_validate_apply_split_flags and make the decision there,
if the global config.enable_4to1MPC is set to true for the
DCN version we're running.

This fixes corruption that is observed when running a new IGT
kms_colorop test for color-space-conversion that uses a
YUV plane and outputs to a writeback connector.

Co-developed by Claude Sonnet 4.5.

Assisted-by: Claude:claude-sonnet-4.5
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Harry Wentland and committed by
Alex Deucher 4c3aeb11 86117c5a

+39 -29
+1 -1
drivers/gpu/drm/amd/display/dc/dc.h
··· 521 521 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 522 522 bool multi_mon_pp_mclk_switch; 523 523 bool disable_dmcu; 524 - bool enable_4to1MPC; 524 + bool allow_4to1MPC; 525 525 bool enable_windowed_mpo_odm; 526 526 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 527 527 uint32_t allow_edp_hotplug_detection;
+1 -5
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
··· 391 391 } 392 392 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; 393 393 394 - dc->config.enable_4to1MPC = false; 395 394 if (pipe_cnt == 1 && pipe->plane_state 396 395 && pipe->plane_state->rotation == ROTATION_ANGLE_0 && !dc->debug.disable_z9_mpc) { 397 - if (is_dual_plane(pipe->plane_state->format) 398 - && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 399 - dc->config.enable_4to1MPC = true; 400 - } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 396 + if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 401 397 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 402 398 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 403 399 pipes[0].pipe.src.unbounded_req_mode = true;
+1 -6
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
··· 528 528 } 529 529 530 530 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ 531 - dc->config.enable_4to1MPC = false; 532 531 533 532 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 534 - if (is_dual_plane(pipe->plane_state->format) 535 - && pipe->plane_state->src_rect.width <= 1920 && 536 - pipe->plane_state->src_rect.height <= 1080) { 537 - dc->config.enable_4to1MPC = true; 538 - } else if (!is_dual_plane(pipe->plane_state->format) && 533 + if (!is_dual_plane(pipe->plane_state->format) && 539 534 pipe->plane_state->src_rect.width <= 5120) { 540 535 /* 541 536 * Limit to 5k max to avoid forced pipe split when there
+1 -6
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
··· 561 561 } 562 562 563 563 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ 564 - dc->config.enable_4to1MPC = false; 565 564 566 565 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 567 - if (is_dual_plane(pipe->plane_state->format) 568 - && pipe->plane_state->src_rect.width <= 1920 && 569 - pipe->plane_state->src_rect.height <= 1080) { 570 - dc->config.enable_4to1MPC = true; 571 - } else if (!is_dual_plane(pipe->plane_state->format) && 566 + if (!is_dual_plane(pipe->plane_state->format) && 572 567 pipe->plane_state->src_rect.width <= 5120) { 573 568 /* 574 569 * Limit to 5k max to avoid forced pipe split when there
+14 -2
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
··· 1814 1814 } 1815 1815 } 1816 1816 1817 + static bool is_dual_plane(enum surface_pixel_format format) 1818 + { 1819 + return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1820 + } 1821 + 1817 1822 int dcn20_validate_apply_pipe_split_flags( 1818 1823 struct dc *dc, 1819 1824 struct dc_state *context, ··· 1903 1898 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1904 1899 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1905 1900 int pipe_plane = v->pipe_plane[pipe_idx]; 1906 - bool split4mpc = context->stream_count == 1 && plane_count == 1 1907 - && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4; 1901 + bool split4mpc = false; 1902 + 1903 + if (context->stream_count == 1 && plane_count == 1 1904 + && dc->config.allow_4to1MPC && dc->res_pool->pipe_count >= 4 1905 + && !dc->debug.disable_z9_mpc 1906 + && pipe->plane_state && is_dual_plane(pipe->plane_state->format) 1907 + && pipe->plane_state->src_rect.width <= 1920 1908 + && pipe->plane_state->src_rect.height <= 1080) 1909 + split4mpc = true; 1908 1910 1909 1911 if (!context->res_ctx.pipe_ctx[i].stream) 1910 1912 continue;
+5 -5
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
··· 1699 1699 pipe_cnt++; 1700 1700 } 1701 1701 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; 1702 - dc->config.enable_4to1MPC = false; 1702 + 1703 1703 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1704 - if (is_dual_plane(pipe->plane_state->format) 1705 - && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1706 - dc->config.enable_4to1MPC = true; 1707 - } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1704 + if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1708 1705 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1709 1706 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1710 1707 pipes[0].pipe.src.unbounded_req_mode = true; ··· 1918 1921 dc->caps.dmcub_support = true; 1919 1922 dc->caps.is_apu = true; 1920 1923 dc->caps.zstate_support = true; 1924 + 1925 + /* Enable 4to1MPC by default */ 1926 + dc->config.allow_4to1MPC = true; 1921 1927 1922 1928 /* Color pipeline capabilities */ 1923 1929 dc->caps.color.dpp.dcn_arch = 1;
+3
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
··· 1830 1830 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1831 1831 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1832 1832 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1833 + 1834 + /* Enable 4to1MPC by default */ 1835 + dc->config.allow_4to1MPC = true; 1833 1836 dc->caps.max_downscale_ratio = 400; 1834 1837 dc->caps.i2c_speed_in_khz = 100; 1835 1838 dc->caps.i2c_speed_in_khz_hdcp = 100;
+3 -2
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
··· 1785 1785 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1786 1786 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1787 1787 1788 - dc->config.enable_4to1MPC = false; 1789 1788 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1790 1789 if (is_dual_plane(pipe->plane_state->format) 1791 1790 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1792 - dc->config.enable_4to1MPC = true; 1793 1791 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1794 1792 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1795 1793 } else if (!is_dual_plane(pipe->plane_state->format) ··· 1868 1870 *************************************************/ 1869 1871 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1870 1872 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1873 + 1874 + /* Enable 4to1MPC by default */ 1875 + dc->config.allow_4to1MPC = true; 1871 1876 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1872 1877 dc->caps.max_downscale_ratio = 600; 1873 1878 dc->caps.i2c_speed_in_khz = 100;
+4 -2
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
··· 1669 1669 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE) 1670 1670 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE; 1671 1671 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE); 1672 - dc->config.enable_4to1MPC = false; 1673 1672 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1674 1673 if (is_dual_plane(pipe->plane_state->format) 1675 1674 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1676 - dc->config.enable_4to1MPC = true; 1677 1675 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1678 1676 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB; 1679 1677 } else if (!is_dual_plane(pipe->plane_state->format)) { ··· 1744 1746 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1745 1747 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1746 1748 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1749 + 1750 + /* Enable 4to1MPC by default */ 1751 + dc->config.allow_4to1MPC = true; 1752 + 1747 1753 dc->caps.max_downscale_ratio = 600; 1748 1754 dc->caps.i2c_speed_in_khz = 100; 1749 1755 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
+3
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
··· 1827 1827 clk_src_regs_init(3, D), 1828 1828 clk_src_regs_init(4, E); 1829 1829 1830 + /* Enable 4to1MPC by default */ 1831 + dc->config.allow_4to1MPC = true; 1832 + 1830 1833 #undef REG_STRUCT 1831 1834 #define REG_STRUCT abm_regs 1832 1835 abm_regs_init(0),
+3
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
··· 1800 1800 clk_src_regs_init(3, D), 1801 1801 clk_src_regs_init(4, E); 1802 1802 1803 + /* Enable 4to1MPC by default */ 1804 + dc->config.allow_4to1MPC = true; 1805 + 1803 1806 #undef REG_STRUCT 1804 1807 #define REG_STRUCT abm_regs 1805 1808 abm_regs_init(0),