drm/i915/vrr: Write DC balance params to hw registers

Write DC Balance parameters to hw registers.

--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)

--v3:
- Write registers at compute config.
- Update condition for write.

--v4:
- Address issue with state checker.

--v5:
- Initialise some more dc balance register while enabling VRR.

--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.

--v7:
- Initialise and reset live value of vmax and vmin as well.

--v8:
- Add separate functions while writing hw registers. (Ankit)

--v9:
- Add DC Balance counter enable bit to this patch. (Ankit)

--v10:
- Add rigister writes to vrr_enable/disable. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-12-mitulkumar.ajitkumar.golani@intel.com

authored by

Mitul Golani and committed by

Ankit Nautiyal 5 months ago 4ca36702 d780bbeb

+76

1 changed file

expand all

drivers

gpu

drm

i915

display

intel_vrr.c

+76

drivers/gpu/drm/i915/display/intel_vrr.c

··· 781 781 intel_vrr_hw_flipline(crtc_state) - 1); 782 782 } 783 783 784 + static void 785 + intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state) 786 + { 787 + struct intel_display *display = to_intel_display(crtc_state); 788 + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 789 + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 790 + enum pipe pipe = crtc->pipe; 791 + 792 + if (!crtc_state->vrr.dc_balance.enable) 793 + return; 794 + 795 + intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 796 + VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1)); 797 + intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 798 + VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1)); 799 + intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 800 + VRR_DCB_VMAX(crtc_state->vrr.vmax - 1)); 801 + intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 802 + VRR_DCB_VMAX(crtc_state->vrr.vmax - 1)); 803 + intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 804 + VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1)); 805 + intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 806 + VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1)); 807 + intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 808 + VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1)); 809 + intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 810 + VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1)); 811 + intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 812 + crtc_state->vrr.dc_balance.vmin - 1); 813 + intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 814 + crtc_state->vrr.dc_balance.vmax - 1); 815 + intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 816 + crtc_state->vrr.dc_balance.max_increase); 817 + intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 818 + crtc_state->vrr.dc_balance.max_decrease); 819 + intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 820 + crtc_state->vrr.dc_balance.guardband); 821 + intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 822 + crtc_state->vrr.dc_balance.slope); 823 + intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 824 + crtc_state->vrr.dc_balance.vblank_target); 825 + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 826 + ADAPTIVE_SYNC_COUNTER_EN); 827 + } 828 + 829 + static void 830 + intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state) 831 + { 832 + struct intel_display *display = to_intel_display(old_crtc_state); 833 + enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 834 + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 835 + enum pipe pipe = crtc->pipe; 836 + 837 + if (!old_crtc_state->vrr.dc_balance.enable) 838 + return; 839 + 840 + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0); 841 + intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); 842 + intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0); 843 + intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0); 844 + intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0); 845 + intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0); 846 + intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0); 847 + intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0); 848 + intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0); 849 + intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0); 850 + intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0); 851 + intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0); 852 + intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0); 853 + intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0); 854 + intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0); 855 + intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0); 856 + } 857 + 784 858 static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state, 785 859 bool cmrr_enable) 786 860 { ··· 901 827 return; 902 828 903 829 intel_vrr_set_vrr_timings(crtc_state); 830 + intel_vrr_enable_dc_balancing(crtc_state); 904 831 905 832 if (!intel_vrr_always_use_vrr_tg(display)) 906 833 intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable); ··· 917 842 if (!intel_vrr_always_use_vrr_tg(display)) 918 843 intel_vrr_tg_disable(old_crtc_state); 919 844 845 + intel_vrr_disable_dc_balancing(old_crtc_state); 920 846 intel_vrr_set_fixed_rr_timings(old_crtc_state); 921 847 } 922 848

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