Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pci-v6.2-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI fixes from Bjorn Helgaas:
- Move to a shared PCI git tree (Bjorn Helgaas)
- Add Krzysztof Wilczyński as another PCI maintainer (Lorenzo
Pieralisi)
- Revert a couple ASPM patches to fix suspend/resume regressions (Bjorn
Helgaas)
* tag 'pci-v6.2-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
Revert "PCI/ASPM: Refactor L1 PM Substates Control Register programming"
Revert "PCI/ASPM: Save L1 PM Substates Capability for suspend/resume"
MAINTAINERS: Promote Krzysztof to PCI controller maintainer
MAINTAINERS: Move to shared PCI tree
+39
-93
+6
-6
MAINTAINERS
+6
-6
MAINTAINERS
···
16120
16120
16121
16121
PCI ENDPOINT SUBSYSTEM
16122
16122
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
16123
-
R: Krzysztof Wilczyński <kw@linux.com>
16123
+
M: Krzysztof Wilczyński <kw@linux.com>
16124
16124
R: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
16125
16125
R: Kishon Vijay Abraham I <kishon@kernel.org>
16126
16126
L: linux-pci@vger.kernel.org
···
16128
16128
Q: https://patchwork.kernel.org/project/linux-pci/list/
16129
16129
B: https://bugzilla.kernel.org
16130
16130
C: irc://irc.oftc.net/linux-pci
16131
-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git
16131
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
16132
16132
F: Documentation/PCI/endpoint/*
16133
16133
F: Documentation/misc-devices/pci-endpoint-test.rst
16134
16134
F: drivers/misc/pci_endpoint_test.c
···
16163
16163
Q: https://patchwork.kernel.org/project/linux-pci/list/
16164
16164
B: https://bugzilla.kernel.org
16165
16165
C: irc://irc.oftc.net/linux-pci
16166
-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
16166
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
16167
16167
F: Documentation/driver-api/pci/p2pdma.rst
16168
16168
F: drivers/pci/p2pdma.c
16169
16169
F: include/linux/pci-p2pdma.h
···
16185
16185
16186
16186
PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS
16187
16187
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
16188
+
M: Krzysztof Wilczyński <kw@linux.com>
16188
16189
R: Rob Herring <robh@kernel.org>
16189
-
R: Krzysztof Wilczyński <kw@linux.com>
16190
16190
L: linux-pci@vger.kernel.org
16191
16191
S: Supported
16192
16192
Q: https://patchwork.kernel.org/project/linux-pci/list/
16193
16193
B: https://bugzilla.kernel.org
16194
16194
C: irc://irc.oftc.net/linux-pci
16195
-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git
16195
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
16196
16196
F: Documentation/devicetree/bindings/pci/
16197
16197
F: drivers/pci/controller/
16198
16198
F: drivers/pci/pci-bridge-emul.c
···
16205
16205
Q: https://patchwork.kernel.org/project/linux-pci/list/
16206
16206
B: https://bugzilla.kernel.org
16207
16207
C: irc://irc.oftc.net/linux-pci
16208
-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
16208
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
16209
16209
F: Documentation/PCI/
16210
16210
F: Documentation/devicetree/bindings/pci/
16211
16211
F: arch/x86/kernel/early-quirks.c
-7
drivers/pci/pci.c
-7
drivers/pci/pci.c
···
1665
1665
return i;
1666
1666
1667
1667
pci_save_ltr_state(dev);
1668
-
pci_save_aspm_l1ss_state(dev);
1669
1668
pci_save_dpc_state(dev);
1670
1669
pci_save_aer_state(dev);
1671
1670
pci_save_ptm_state(dev);
···
1771
1772
* LTR itself (in the PCIe capability).
1772
1773
*/
1773
1774
pci_restore_ltr_state(dev);
1774
-
pci_restore_aspm_l1ss_state(dev);
1775
1775
1776
1776
pci_restore_pcie_state(dev);
1777
1777
pci_restore_pasid_state(dev);
···
3462
3464
2 * sizeof(u16));
3463
3465
if (error)
3464
3466
pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3465
-
3466
-
error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS,
3467
-
2 * sizeof(u32));
3468
-
if (error)
3469
-
pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n");
3470
3467
3471
3468
pci_allocate_vc_save_buffers(dev);
3472
3469
}
-4
drivers/pci/pci.h
-4
drivers/pci/pci.h
···
566
566
void pcie_aspm_init_link_state(struct pci_dev *pdev);
567
567
void pcie_aspm_exit_link_state(struct pci_dev *pdev);
568
568
void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
569
-
void pci_save_aspm_l1ss_state(struct pci_dev *dev);
570
-
void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
571
569
#else
572
570
static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
573
571
static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
574
572
static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
575
-
static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { }
576
-
static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { }
577
573
#endif
578
574
579
575
#ifdef CONFIG_PCIE_ECRC
+33
-76
drivers/pci/pcie/aspm.c
+33
-76
drivers/pci/pcie/aspm.c
···
470
470
pci_write_config_dword(pdev, pos, val);
471
471
}
472
472
473
-
static void aspm_program_l1ss(struct pci_dev *dev, u32 ctl1, u32 ctl2)
474
-
{
475
-
u16 l1ss = dev->l1ss;
476
-
u32 l1_2_enable;
477
-
478
-
/*
479
-
* Per PCIe r6.0, sec 5.5.4, T_POWER_ON in PCI_L1SS_CTL2 must be
480
-
* programmed prior to setting the L1.2 enable bits in PCI_L1SS_CTL1.
481
-
*/
482
-
pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL2, ctl2);
483
-
484
-
/*
485
-
* In addition, Common_Mode_Restore_Time and LTR_L1.2_THRESHOLD in
486
-
* PCI_L1SS_CTL1 must be programmed *before* setting the L1.2
487
-
* enable bits, even though they're all in PCI_L1SS_CTL1.
488
-
*/
489
-
l1_2_enable = ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
490
-
ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
491
-
492
-
pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL1, ctl1);
493
-
if (l1_2_enable)
494
-
pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL1,
495
-
ctl1 | l1_2_enable);
496
-
}
497
-
498
473
/* Calculate L1.2 PM substate timing parameters */
499
474
static void aspm_calc_l1ss_info(struct pcie_link_state *link,
500
475
u32 parent_l1ss_cap, u32 child_l1ss_cap)
···
479
504
u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
480
505
u32 ctl1 = 0, ctl2 = 0;
481
506
u32 pctl1, pctl2, cctl1, cctl2;
507
+
u32 pl1_2_enables, cl1_2_enables;
482
508
483
509
if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
484
510
return;
···
528
552
ctl2 == pctl2 && ctl2 == cctl2)
529
553
return;
530
554
531
-
pctl1 &= ~(PCI_L1SS_CTL1_CM_RESTORE_TIME |
532
-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
533
-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE);
534
-
pctl1 |= (ctl1 & (PCI_L1SS_CTL1_CM_RESTORE_TIME |
535
-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
536
-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE));
537
-
aspm_program_l1ss(parent, pctl1, ctl2);
555
+
/* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
556
+
pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
557
+
cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
538
558
539
-
cctl1 &= ~(PCI_L1SS_CTL1_CM_RESTORE_TIME |
540
-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
541
-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE);
542
-
cctl1 |= (ctl1 & (PCI_L1SS_CTL1_CM_RESTORE_TIME |
543
-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
544
-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE));
545
-
aspm_program_l1ss(child, cctl1, ctl2);
559
+
if (pl1_2_enables || cl1_2_enables) {
560
+
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
561
+
PCI_L1SS_CTL1_L1_2_MASK, 0);
562
+
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
563
+
PCI_L1SS_CTL1_L1_2_MASK, 0);
564
+
}
565
+
566
+
/* Program T_POWER_ON times in both ports */
567
+
pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
568
+
pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
569
+
570
+
/* Program Common_Mode_Restore_Time in upstream device */
571
+
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
572
+
PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
573
+
574
+
/* Program LTR_L1.2_THRESHOLD time in both ports */
575
+
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
576
+
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
577
+
PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
578
+
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
579
+
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
580
+
PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
581
+
582
+
if (pl1_2_enables || cl1_2_enables) {
583
+
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
584
+
pl1_2_enables);
585
+
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
586
+
cl1_2_enables);
587
+
}
546
588
}
547
589
548
590
static void aspm_l1ss_init(struct pcie_link_state *link)
···
749
755
PCI_L1SS_CTL1_L1SS_MASK, val);
750
756
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
751
757
PCI_L1SS_CTL1_L1SS_MASK, val);
752
-
}
753
-
754
-
void pci_save_aspm_l1ss_state(struct pci_dev *dev)
755
-
{
756
-
struct pci_cap_saved_state *save_state;
757
-
u16 l1ss = dev->l1ss;
758
-
u32 *cap;
759
-
760
-
if (!l1ss)
761
-
return;
762
-
763
-
save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);
764
-
if (!save_state)
765
-
return;
766
-
767
-
cap = (u32 *)&save_state->cap.data[0];
768
-
pci_read_config_dword(dev, l1ss + PCI_L1SS_CTL2, cap++);
769
-
pci_read_config_dword(dev, l1ss + PCI_L1SS_CTL1, cap++);
770
-
}
771
-
772
-
void pci_restore_aspm_l1ss_state(struct pci_dev *dev)
773
-
{
774
-
struct pci_cap_saved_state *save_state;
775
-
u32 *cap, ctl1, ctl2;
776
-
u16 l1ss = dev->l1ss;
777
-
778
-
if (!l1ss)
779
-
return;
780
-
781
-
save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);
782
-
if (!save_state)
783
-
return;
784
-
785
-
cap = (u32 *)&save_state->cap.data[0];
786
-
ctl2 = *cap++;
787
-
ctl1 = *cap;
788
-
aspm_program_l1ss(dev, ctl1, ctl2);
789
758
}
790
759
791
760
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)