Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sdm845: convert to dynamic IDs
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-rework-icc-v3-5-0575304c9624@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Georgi Djakov
4de68f33
0ab0f87d
+381
-533
+381
-393
drivers/interconnect/qcom/sdm845.c
+381
-393
drivers/interconnect/qcom/sdm845.c
···
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#include "bcm-voter.h"
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#include "icc-rpmh.h"
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-
#include "sdm845.h"
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static struct qcom_icc_node qhm_a1noc_cfg;
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static struct qcom_icc_node qhm_qup1;
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static struct qcom_icc_node qhm_tsif;
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static struct qcom_icc_node xm_sdc2;
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static struct qcom_icc_node xm_sdc4;
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static struct qcom_icc_node xm_ufs_card;
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static struct qcom_icc_node xm_ufs_mem;
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static struct qcom_icc_node xm_pcie_0;
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static struct qcom_icc_node qhm_a2noc_cfg;
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static struct qcom_icc_node qhm_qdss_bam;
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static struct qcom_icc_node qhm_qup2;
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static struct qcom_icc_node qnm_cnoc;
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static struct qcom_icc_node qxm_crypto;
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static struct qcom_icc_node qxm_ipa;
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static struct qcom_icc_node xm_pcie3_1;
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static struct qcom_icc_node xm_qdss_etr;
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static struct qcom_icc_node xm_usb3_0;
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static struct qcom_icc_node xm_usb3_1;
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static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
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static struct qcom_icc_node qxm_camnoc_hf1_uncomp;
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static struct qcom_icc_node qxm_camnoc_sf_uncomp;
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static struct qcom_icc_node qhm_spdm;
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static struct qcom_icc_node qhm_tic;
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static struct qcom_icc_node qnm_snoc;
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static struct qcom_icc_node xm_qdss_dap;
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static struct qcom_icc_node qhm_cnoc;
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static struct qcom_icc_node acm_l3;
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static struct qcom_icc_node pm_gnoc_cfg;
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static struct qcom_icc_node llcc_mc;
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static struct qcom_icc_node acm_tcu;
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static struct qcom_icc_node qhm_memnoc_cfg;
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static struct qcom_icc_node qnm_apps;
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static struct qcom_icc_node qnm_mnoc_hf;
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static struct qcom_icc_node qnm_mnoc_sf;
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static struct qcom_icc_node qnm_snoc_gc;
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static struct qcom_icc_node qnm_snoc_sf;
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static struct qcom_icc_node qxm_gpu;
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static struct qcom_icc_node qhm_mnoc_cfg;
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static struct qcom_icc_node qxm_camnoc_hf0;
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static struct qcom_icc_node qxm_camnoc_hf1;
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static struct qcom_icc_node qxm_camnoc_sf;
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static struct qcom_icc_node qxm_mdp0;
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static struct qcom_icc_node qxm_mdp1;
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static struct qcom_icc_node qxm_rot;
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static struct qcom_icc_node qxm_venus0;
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static struct qcom_icc_node qxm_venus1;
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static struct qcom_icc_node qxm_venus_arm9;
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static struct qcom_icc_node qhm_snoc_cfg;
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static struct qcom_icc_node qnm_aggre1_noc;
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static struct qcom_icc_node qnm_aggre2_noc;
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static struct qcom_icc_node qnm_gladiator_sodv;
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static struct qcom_icc_node qnm_memnoc;
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static struct qcom_icc_node qnm_pcie_anoc;
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static struct qcom_icc_node qxm_pimem;
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static struct qcom_icc_node xm_gic;
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static struct qcom_icc_node qns_a1noc_snoc;
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static struct qcom_icc_node srvc_aggre1_noc;
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static struct qcom_icc_node qns_pcie_a1noc_snoc;
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static struct qcom_icc_node qns_a2noc_snoc;
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static struct qcom_icc_node qns_pcie_snoc;
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static struct qcom_icc_node srvc_aggre2_noc;
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static struct qcom_icc_node qns_camnoc_uncomp;
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static struct qcom_icc_node qhs_a1_noc_cfg;
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static struct qcom_icc_node qhs_a2_noc_cfg;
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static struct qcom_icc_node qhs_aop;
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static struct qcom_icc_node qhs_aoss;
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static struct qcom_icc_node qhs_camera_cfg;
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static struct qcom_icc_node qhs_clk_ctl;
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static struct qcom_icc_node qhs_compute_dsp_cfg;
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static struct qcom_icc_node qhs_cpr_cx;
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static struct qcom_icc_node qhs_crypto0_cfg;
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static struct qcom_icc_node qhs_dcc_cfg;
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static struct qcom_icc_node qhs_ddrss_cfg;
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static struct qcom_icc_node qhs_display_cfg;
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static struct qcom_icc_node qhs_glm;
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static struct qcom_icc_node qhs_gpuss_cfg;
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static struct qcom_icc_node qhs_imem_cfg;
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static struct qcom_icc_node qhs_ipa;
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static struct qcom_icc_node qhs_mnoc_cfg;
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static struct qcom_icc_node qhs_pcie0_cfg;
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static struct qcom_icc_node qhs_pcie_gen3_cfg;
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static struct qcom_icc_node qhs_pdm;
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static struct qcom_icc_node qhs_phy_refgen_south;
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static struct qcom_icc_node qhs_pimem_cfg;
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static struct qcom_icc_node qhs_prng;
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static struct qcom_icc_node qhs_qdss_cfg;
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static struct qcom_icc_node qhs_qupv3_north;
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static struct qcom_icc_node qhs_qupv3_south;
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static struct qcom_icc_node qhs_sdc2;
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static struct qcom_icc_node qhs_sdc4;
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static struct qcom_icc_node qhs_snoc_cfg;
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static struct qcom_icc_node qhs_spdm;
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static struct qcom_icc_node qhs_spss_cfg;
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static struct qcom_icc_node qhs_tcsr;
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static struct qcom_icc_node qhs_tlmm_north;
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static struct qcom_icc_node qhs_tlmm_south;
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static struct qcom_icc_node qhs_tsif;
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static struct qcom_icc_node qhs_ufs_card_cfg;
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static struct qcom_icc_node qhs_ufs_mem_cfg;
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static struct qcom_icc_node qhs_usb3_0;
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static struct qcom_icc_node qhs_usb3_1;
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static struct qcom_icc_node qhs_venus_cfg;
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static struct qcom_icc_node qhs_vsense_ctrl_cfg;
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static struct qcom_icc_node qns_cnoc_a2noc;
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static struct qcom_icc_node srvc_cnoc;
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static struct qcom_icc_node qhs_llcc;
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static struct qcom_icc_node qhs_memnoc;
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static struct qcom_icc_node qns_gladiator_sodv;
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static struct qcom_icc_node qns_gnoc_memnoc;
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static struct qcom_icc_node srvc_gnoc;
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static struct qcom_icc_node ebi;
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static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
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static struct qcom_icc_node qns_apps_io;
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static struct qcom_icc_node qns_llcc;
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static struct qcom_icc_node qns_memnoc_snoc;
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static struct qcom_icc_node srvc_memnoc;
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static struct qcom_icc_node qns2_mem_noc;
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static struct qcom_icc_node qns_mem_noc_hf;
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static struct qcom_icc_node srvc_mnoc;
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static struct qcom_icc_node qhs_apss;
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static struct qcom_icc_node qns_cnoc;
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static struct qcom_icc_node qns_memnoc_gc;
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static struct qcom_icc_node qns_memnoc_sf;
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static struct qcom_icc_node qxs_imem;
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static struct qcom_icc_node qxs_pcie;
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static struct qcom_icc_node qxs_pcie_gen3;
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static struct qcom_icc_node qxs_pimem;
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static struct qcom_icc_node srvc_snoc;
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static struct qcom_icc_node xs_qdss_stm;
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static struct qcom_icc_node xs_sys_tcu_cfg;
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static struct qcom_icc_node qhm_a1noc_cfg = {
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.name = "qhm_a1noc_cfg",
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.id = SDM845_MASTER_A1NOC_CFG,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SDM845_SLAVE_SERVICE_A1NOC },
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.link_nodes = { &srvc_aggre1_noc },
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};
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static struct qcom_icc_node qhm_qup1 = {
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.name = "qhm_qup1",
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.id = SDM845_MASTER_BLSP_1,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SDM845_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node qhm_tsif = {
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.name = "qhm_tsif",
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.id = SDM845_MASTER_TSIF,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SDM845_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_sdc2 = {
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.name = "xm_sdc2",
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.id = SDM845_MASTER_SDCC_2,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_sdc4 = {
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.name = "xm_sdc4",
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.id = SDM845_MASTER_SDCC_4,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_ufs_card = {
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.name = "xm_ufs_card",
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.id = SDM845_MASTER_UFS_CARD,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_ufs_mem = {
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.name = "xm_ufs_mem",
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.id = SDM845_MASTER_UFS_MEM,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_pcie_0 = {
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.name = "xm_pcie_0",
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.id = SDM845_MASTER_PCIE_0,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC },
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.link_nodes = { &qns_pcie_a1noc_snoc },
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};
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static struct qcom_icc_node qhm_a2noc_cfg = {
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.name = "qhm_a2noc_cfg",
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.id = SDM845_MASTER_A2NOC_CFG,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SDM845_SLAVE_SERVICE_A2NOC },
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.link_nodes = { &srvc_aggre2_noc },
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};
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static struct qcom_icc_node qhm_qdss_bam = {
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.name = "qhm_qdss_bam",
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.id = SDM845_MASTER_QDSS_BAM,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SDM845_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qhm_qup2 = {
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.name = "qhm_qup2",
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.id = SDM845_MASTER_BLSP_2,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SDM845_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qnm_cnoc = {
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.name = "qnm_cnoc",
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.id = SDM845_MASTER_CNOC_A2NOC,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qxm_crypto = {
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.name = "qxm_crypto",
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.id = SDM845_MASTER_CRYPTO,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qxm_ipa = {
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.name = "qxm_ipa",
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.id = SDM845_MASTER_IPA,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node xm_pcie3_1 = {
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.name = "xm_pcie3_1",
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.id = SDM845_MASTER_PCIE_1,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_ANOC_PCIE_SNOC },
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.link_nodes = { &qns_pcie_snoc },
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};
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static struct qcom_icc_node xm_qdss_etr = {
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.name = "xm_qdss_etr",
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.id = SDM845_MASTER_QDSS_ETR,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node xm_usb3_0 = {
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.name = "xm_usb3_0",
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.id = SDM845_MASTER_USB3_0,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node xm_usb3_1 = {
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.name = "xm_usb3_1",
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.id = SDM845_MASTER_USB3_1,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SDM845_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
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.name = "qxm_camnoc_hf0_uncomp",
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.id = SDM845_MASTER_CAMNOC_HF0_UNCOMP,
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.channels = 1,
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.buswidth = 32,
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.num_links = 1,
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.links = { SDM845_SLAVE_CAMNOC_UNCOMP },
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.link_nodes = { &qns_camnoc_uncomp },
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};
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static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
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.name = "qxm_camnoc_hf1_uncomp",
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.id = SDM845_MASTER_CAMNOC_HF1_UNCOMP,
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.channels = 1,
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.buswidth = 32,
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.num_links = 1,
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.links = { SDM845_SLAVE_CAMNOC_UNCOMP },
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.link_nodes = { &qns_camnoc_uncomp },
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};
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static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
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.name = "qxm_camnoc_sf_uncomp",
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.id = SDM845_MASTER_CAMNOC_SF_UNCOMP,
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.channels = 1,
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.buswidth = 32,
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.num_links = 1,
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.links = { SDM845_SLAVE_CAMNOC_UNCOMP },
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.link_nodes = { &qns_camnoc_uncomp },
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};
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static struct qcom_icc_node qhm_spdm = {
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.name = "qhm_spdm",
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.id = SDM845_MASTER_SPDM,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SDM845_SLAVE_CNOC_A2NOC },
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.link_nodes = { &qns_cnoc_a2noc },
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};
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static struct qcom_icc_node qhm_tic = {
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.name = "qhm_tic",
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.id = SDM845_MASTER_TIC,
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.channels = 1,
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.buswidth = 4,
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.num_links = 43,
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-
.links = { SDM845_SLAVE_A1NOC_CFG,
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-
SDM845_SLAVE_A2NOC_CFG,
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SDM845_SLAVE_AOP,
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SDM845_SLAVE_AOSS,
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SDM845_SLAVE_CAMERA_CFG,
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SDM845_SLAVE_CLK_CTL,
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SDM845_SLAVE_CDSP_CFG,
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SDM845_SLAVE_RBCPR_CX_CFG,
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-
SDM845_SLAVE_CRYPTO_0_CFG,
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SDM845_SLAVE_DCC_CFG,
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-
SDM845_SLAVE_CNOC_DDRSS,
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SDM845_SLAVE_DISPLAY_CFG,
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SDM845_SLAVE_GLM,
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SDM845_SLAVE_GFX3D_CFG,
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SDM845_SLAVE_IMEM_CFG,
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-
SDM845_SLAVE_IPA_CFG,
239
-
SDM845_SLAVE_CNOC_MNOC_CFG,
240
-
SDM845_SLAVE_PCIE_0_CFG,
241
-
SDM845_SLAVE_PCIE_1_CFG,
242
-
SDM845_SLAVE_PDM,
243
-
SDM845_SLAVE_SOUTH_PHY_CFG,
244
-
SDM845_SLAVE_PIMEM_CFG,
245
-
SDM845_SLAVE_PRNG,
246
-
SDM845_SLAVE_QDSS_CFG,
247
-
SDM845_SLAVE_BLSP_2,
248
-
SDM845_SLAVE_BLSP_1,
249
-
SDM845_SLAVE_SDCC_2,
250
-
SDM845_SLAVE_SDCC_4,
251
-
SDM845_SLAVE_SNOC_CFG,
252
-
SDM845_SLAVE_SPDM_WRAPPER,
253
-
SDM845_SLAVE_SPSS_CFG,
254
-
SDM845_SLAVE_TCSR,
255
-
SDM845_SLAVE_TLMM_NORTH,
256
-
SDM845_SLAVE_TLMM_SOUTH,
257
-
SDM845_SLAVE_TSIF,
258
-
SDM845_SLAVE_UFS_CARD_CFG,
259
-
SDM845_SLAVE_UFS_MEM_CFG,
260
-
SDM845_SLAVE_USB3_0,
261
-
SDM845_SLAVE_USB3_1,
262
-
SDM845_SLAVE_VENUS_CFG,
263
-
SDM845_SLAVE_VSENSE_CTRL_CFG,
264
-
SDM845_SLAVE_CNOC_A2NOC,
265
-
SDM845_SLAVE_SERVICE_CNOC
266
-
},
330
+
.link_nodes = { &qhs_a1_noc_cfg,
331
+
&qhs_a2_noc_cfg,
332
+
&qhs_aop,
333
+
&qhs_aoss,
334
+
&qhs_camera_cfg,
335
+
&qhs_clk_ctl,
336
+
&qhs_compute_dsp_cfg,
337
+
&qhs_cpr_cx,
338
+
&qhs_crypto0_cfg,
339
+
&qhs_dcc_cfg,
340
+
&qhs_ddrss_cfg,
341
+
&qhs_display_cfg,
342
+
&qhs_glm,
343
+
&qhs_gpuss_cfg,
344
+
&qhs_imem_cfg,
345
+
&qhs_ipa,
346
+
&qhs_mnoc_cfg,
347
+
&qhs_pcie0_cfg,
348
+
&qhs_pcie_gen3_cfg,
349
+
&qhs_pdm,
350
+
&qhs_phy_refgen_south,
351
+
&qhs_pimem_cfg,
352
+
&qhs_prng,
353
+
&qhs_qdss_cfg,
354
+
&qhs_qupv3_north,
355
+
&qhs_qupv3_south,
356
+
&qhs_sdc2,
357
+
&qhs_sdc4,
358
+
&qhs_snoc_cfg,
359
+
&qhs_spdm,
360
+
&qhs_spss_cfg,
361
+
&qhs_tcsr,
362
+
&qhs_tlmm_north,
363
+
&qhs_tlmm_south,
364
+
&qhs_tsif,
365
+
&qhs_ufs_card_cfg,
366
+
&qhs_ufs_mem_cfg,
367
+
&qhs_usb3_0,
368
+
&qhs_usb3_1,
369
+
&qhs_venus_cfg,
370
+
&qhs_vsense_ctrl_cfg,
371
+
&qns_cnoc_a2noc,
372
+
&srvc_cnoc },
267
373
};
268
374
269
375
static struct qcom_icc_node qnm_snoc = {
270
376
.name = "qnm_snoc",
271
-
.id = SDM845_MASTER_SNOC_CNOC,
272
377
.channels = 1,
273
378
.buswidth = 8,
274
379
.num_links = 42,
275
-
.links = { SDM845_SLAVE_A1NOC_CFG,
276
-
SDM845_SLAVE_A2NOC_CFG,
277
-
SDM845_SLAVE_AOP,
278
-
SDM845_SLAVE_AOSS,
279
-
SDM845_SLAVE_CAMERA_CFG,
280
-
SDM845_SLAVE_CLK_CTL,
281
-
SDM845_SLAVE_CDSP_CFG,
282
-
SDM845_SLAVE_RBCPR_CX_CFG,
283
-
SDM845_SLAVE_CRYPTO_0_CFG,
284
-
SDM845_SLAVE_DCC_CFG,
285
-
SDM845_SLAVE_CNOC_DDRSS,
286
-
SDM845_SLAVE_DISPLAY_CFG,
287
-
SDM845_SLAVE_GLM,
288
-
SDM845_SLAVE_GFX3D_CFG,
289
-
SDM845_SLAVE_IMEM_CFG,
290
-
SDM845_SLAVE_IPA_CFG,
291
-
SDM845_SLAVE_CNOC_MNOC_CFG,
292
-
SDM845_SLAVE_PCIE_0_CFG,
293
-
SDM845_SLAVE_PCIE_1_CFG,
294
-
SDM845_SLAVE_PDM,
295
-
SDM845_SLAVE_SOUTH_PHY_CFG,
296
-
SDM845_SLAVE_PIMEM_CFG,
297
-
SDM845_SLAVE_PRNG,
298
-
SDM845_SLAVE_QDSS_CFG,
299
-
SDM845_SLAVE_BLSP_2,
300
-
SDM845_SLAVE_BLSP_1,
301
-
SDM845_SLAVE_SDCC_2,
302
-
SDM845_SLAVE_SDCC_4,
303
-
SDM845_SLAVE_SNOC_CFG,
304
-
SDM845_SLAVE_SPDM_WRAPPER,
305
-
SDM845_SLAVE_SPSS_CFG,
306
-
SDM845_SLAVE_TCSR,
307
-
SDM845_SLAVE_TLMM_NORTH,
308
-
SDM845_SLAVE_TLMM_SOUTH,
309
-
SDM845_SLAVE_TSIF,
310
-
SDM845_SLAVE_UFS_CARD_CFG,
311
-
SDM845_SLAVE_UFS_MEM_CFG,
312
-
SDM845_SLAVE_USB3_0,
313
-
SDM845_SLAVE_USB3_1,
314
-
SDM845_SLAVE_VENUS_CFG,
315
-
SDM845_SLAVE_VSENSE_CTRL_CFG,
316
-
SDM845_SLAVE_SERVICE_CNOC
317
-
},
380
+
.link_nodes = { &qhs_a1_noc_cfg,
381
+
&qhs_a2_noc_cfg,
382
+
&qhs_aop,
383
+
&qhs_aoss,
384
+
&qhs_camera_cfg,
385
+
&qhs_clk_ctl,
386
+
&qhs_compute_dsp_cfg,
387
+
&qhs_cpr_cx,
388
+
&qhs_crypto0_cfg,
389
+
&qhs_dcc_cfg,
390
+
&qhs_ddrss_cfg,
391
+
&qhs_display_cfg,
392
+
&qhs_glm,
393
+
&qhs_gpuss_cfg,
394
+
&qhs_imem_cfg,
395
+
&qhs_ipa,
396
+
&qhs_mnoc_cfg,
397
+
&qhs_pcie0_cfg,
398
+
&qhs_pcie_gen3_cfg,
399
+
&qhs_pdm,
400
+
&qhs_phy_refgen_south,
401
+
&qhs_pimem_cfg,
402
+
&qhs_prng,
403
+
&qhs_qdss_cfg,
404
+
&qhs_qupv3_north,
405
+
&qhs_qupv3_south,
406
+
&qhs_sdc2,
407
+
&qhs_sdc4,
408
+
&qhs_snoc_cfg,
409
+
&qhs_spdm,
410
+
&qhs_spss_cfg,
411
+
&qhs_tcsr,
412
+
&qhs_tlmm_north,
413
+
&qhs_tlmm_south,
414
+
&qhs_tsif,
415
+
&qhs_ufs_card_cfg,
416
+
&qhs_ufs_mem_cfg,
417
+
&qhs_usb3_0,
418
+
&qhs_usb3_1,
419
+
&qhs_venus_cfg,
420
+
&qhs_vsense_ctrl_cfg,
421
+
&srvc_cnoc },
318
422
};
319
423
320
424
static struct qcom_icc_node xm_qdss_dap = {
321
425
.name = "xm_qdss_dap",
322
-
.id = SDM845_MASTER_QDSS_DAP,
323
426
.channels = 1,
324
427
.buswidth = 8,
325
428
.num_links = 43,
326
-
.links = { SDM845_SLAVE_A1NOC_CFG,
327
-
SDM845_SLAVE_A2NOC_CFG,
328
-
SDM845_SLAVE_AOP,
329
-
SDM845_SLAVE_AOSS,
330
-
SDM845_SLAVE_CAMERA_CFG,
331
-
SDM845_SLAVE_CLK_CTL,
332
-
SDM845_SLAVE_CDSP_CFG,
333
-
SDM845_SLAVE_RBCPR_CX_CFG,
334
-
SDM845_SLAVE_CRYPTO_0_CFG,
335
-
SDM845_SLAVE_DCC_CFG,
336
-
SDM845_SLAVE_CNOC_DDRSS,
337
-
SDM845_SLAVE_DISPLAY_CFG,
338
-
SDM845_SLAVE_GLM,
339
-
SDM845_SLAVE_GFX3D_CFG,
340
-
SDM845_SLAVE_IMEM_CFG,
341
-
SDM845_SLAVE_IPA_CFG,
342
-
SDM845_SLAVE_CNOC_MNOC_CFG,
343
-
SDM845_SLAVE_PCIE_0_CFG,
344
-
SDM845_SLAVE_PCIE_1_CFG,
345
-
SDM845_SLAVE_PDM,
346
-
SDM845_SLAVE_SOUTH_PHY_CFG,
347
-
SDM845_SLAVE_PIMEM_CFG,
348
-
SDM845_SLAVE_PRNG,
349
-
SDM845_SLAVE_QDSS_CFG,
350
-
SDM845_SLAVE_BLSP_2,
351
-
SDM845_SLAVE_BLSP_1,
352
-
SDM845_SLAVE_SDCC_2,
353
-
SDM845_SLAVE_SDCC_4,
354
-
SDM845_SLAVE_SNOC_CFG,
355
-
SDM845_SLAVE_SPDM_WRAPPER,
356
-
SDM845_SLAVE_SPSS_CFG,
357
-
SDM845_SLAVE_TCSR,
358
-
SDM845_SLAVE_TLMM_NORTH,
359
-
SDM845_SLAVE_TLMM_SOUTH,
360
-
SDM845_SLAVE_TSIF,
361
-
SDM845_SLAVE_UFS_CARD_CFG,
362
-
SDM845_SLAVE_UFS_MEM_CFG,
363
-
SDM845_SLAVE_USB3_0,
364
-
SDM845_SLAVE_USB3_1,
365
-
SDM845_SLAVE_VENUS_CFG,
366
-
SDM845_SLAVE_VSENSE_CTRL_CFG,
367
-
SDM845_SLAVE_CNOC_A2NOC,
368
-
SDM845_SLAVE_SERVICE_CNOC
369
-
},
429
+
.link_nodes = { &qhs_a1_noc_cfg,
430
+
&qhs_a2_noc_cfg,
431
+
&qhs_aop,
432
+
&qhs_aoss,
433
+
&qhs_camera_cfg,
434
+
&qhs_clk_ctl,
435
+
&qhs_compute_dsp_cfg,
436
+
&qhs_cpr_cx,
437
+
&qhs_crypto0_cfg,
438
+
&qhs_dcc_cfg,
439
+
&qhs_ddrss_cfg,
440
+
&qhs_display_cfg,
441
+
&qhs_glm,
442
+
&qhs_gpuss_cfg,
443
+
&qhs_imem_cfg,
444
+
&qhs_ipa,
445
+
&qhs_mnoc_cfg,
446
+
&qhs_pcie0_cfg,
447
+
&qhs_pcie_gen3_cfg,
448
+
&qhs_pdm,
449
+
&qhs_phy_refgen_south,
450
+
&qhs_pimem_cfg,
451
+
&qhs_prng,
452
+
&qhs_qdss_cfg,
453
+
&qhs_qupv3_north,
454
+
&qhs_qupv3_south,
455
+
&qhs_sdc2,
456
+
&qhs_sdc4,
457
+
&qhs_snoc_cfg,
458
+
&qhs_spdm,
459
+
&qhs_spss_cfg,
460
+
&qhs_tcsr,
461
+
&qhs_tlmm_north,
462
+
&qhs_tlmm_south,
463
+
&qhs_tsif,
464
+
&qhs_ufs_card_cfg,
465
+
&qhs_ufs_mem_cfg,
466
+
&qhs_usb3_0,
467
+
&qhs_usb3_1,
468
+
&qhs_venus_cfg,
469
+
&qhs_vsense_ctrl_cfg,
470
+
&qns_cnoc_a2noc,
471
+
&srvc_cnoc },
370
472
};
371
473
372
474
static struct qcom_icc_node qhm_cnoc = {
373
475
.name = "qhm_cnoc",
374
-
.id = SDM845_MASTER_CNOC_DC_NOC,
375
476
.channels = 1,
376
477
.buswidth = 4,
377
478
.num_links = 2,
378
-
.links = { SDM845_SLAVE_LLCC_CFG,
379
-
SDM845_SLAVE_MEM_NOC_CFG
380
-
},
479
+
.link_nodes = { &qhs_llcc,
480
+
&qhs_memnoc },
381
481
};
382
482
383
483
static struct qcom_icc_node acm_l3 = {
384
484
.name = "acm_l3",
385
-
.id = SDM845_MASTER_APPSS_PROC,
386
485
.channels = 1,
387
486
.buswidth = 16,
388
487
.num_links = 3,
389
-
.links = { SDM845_SLAVE_GNOC_SNOC,
390
-
SDM845_SLAVE_GNOC_MEM_NOC,
391
-
SDM845_SLAVE_SERVICE_GNOC
392
-
},
488
+
.link_nodes = { &qns_gladiator_sodv,
489
+
&qns_gnoc_memnoc,
490
+
&srvc_gnoc },
393
491
};
394
492
395
493
static struct qcom_icc_node pm_gnoc_cfg = {
396
494
.name = "pm_gnoc_cfg",
397
-
.id = SDM845_MASTER_GNOC_CFG,
398
495
.channels = 1,
399
496
.buswidth = 4,
400
497
.num_links = 1,
401
-
.links = { SDM845_SLAVE_SERVICE_GNOC },
498
+
.link_nodes = { &srvc_gnoc },
402
499
};
403
500
404
501
static struct qcom_icc_node llcc_mc = {
405
502
.name = "llcc_mc",
406
-
.id = SDM845_MASTER_LLCC,
407
503
.channels = 4,
408
504
.buswidth = 4,
409
505
.num_links = 1,
410
-
.links = { SDM845_SLAVE_EBI1 },
506
+
.link_nodes = { &ebi },
411
507
};
412
508
413
509
static struct qcom_icc_node acm_tcu = {
414
510
.name = "acm_tcu",
415
-
.id = SDM845_MASTER_TCU_0,
416
511
.channels = 1,
417
512
.buswidth = 8,
418
513
.num_links = 3,
419
-
.links = { SDM845_SLAVE_MEM_NOC_GNOC,
420
-
SDM845_SLAVE_LLCC,
421
-
SDM845_SLAVE_MEM_NOC_SNOC
422
-
},
514
+
.link_nodes = { &qns_apps_io,
515
+
&qns_llcc,
516
+
&qns_memnoc_snoc },
423
517
};
424
518
425
519
static struct qcom_icc_node qhm_memnoc_cfg = {
426
520
.name = "qhm_memnoc_cfg",
427
-
.id = SDM845_MASTER_MEM_NOC_CFG,
428
521
.channels = 1,
429
522
.buswidth = 4,
430
523
.num_links = 2,
431
-
.links = { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
432
-
SDM845_SLAVE_SERVICE_MEM_NOC
433
-
},
524
+
.link_nodes = { &qhs_mdsp_ms_mpu_cfg,
525
+
&srvc_memnoc },
434
526
};
435
527
436
528
static struct qcom_icc_node qnm_apps = {
437
529
.name = "qnm_apps",
438
-
.id = SDM845_MASTER_GNOC_MEM_NOC,
439
530
.channels = 2,
440
531
.buswidth = 32,
441
532
.num_links = 1,
442
-
.links = { SDM845_SLAVE_LLCC },
533
+
.link_nodes = { &qns_llcc },
443
534
};
444
535
445
536
static struct qcom_icc_node qnm_mnoc_hf = {
446
537
.name = "qnm_mnoc_hf",
447
-
.id = SDM845_MASTER_MNOC_HF_MEM_NOC,
448
538
.channels = 2,
449
539
.buswidth = 32,
450
540
.num_links = 2,
451
-
.links = { SDM845_SLAVE_MEM_NOC_GNOC,
452
-
SDM845_SLAVE_LLCC
453
-
},
541
+
.link_nodes = { &qns_apps_io,
542
+
&qns_llcc },
454
543
};
455
544
456
545
static struct qcom_icc_node qnm_mnoc_sf = {
457
546
.name = "qnm_mnoc_sf",
458
-
.id = SDM845_MASTER_MNOC_SF_MEM_NOC,
459
547
.channels = 1,
460
548
.buswidth = 32,
461
549
.num_links = 3,
462
-
.links = { SDM845_SLAVE_MEM_NOC_GNOC,
463
-
SDM845_SLAVE_LLCC,
464
-
SDM845_SLAVE_MEM_NOC_SNOC
465
-
},
550
+
.link_nodes = { &qns_apps_io,
551
+
&qns_llcc,
552
+
&qns_memnoc_snoc },
466
553
};
467
554
468
555
static struct qcom_icc_node qnm_snoc_gc = {
469
556
.name = "qnm_snoc_gc",
470
-
.id = SDM845_MASTER_SNOC_GC_MEM_NOC,
471
557
.channels = 1,
472
558
.buswidth = 8,
473
559
.num_links = 1,
474
-
.links = { SDM845_SLAVE_LLCC },
560
+
.link_nodes = { &qns_llcc },
475
561
};
476
562
477
563
static struct qcom_icc_node qnm_snoc_sf = {
478
564
.name = "qnm_snoc_sf",
479
-
.id = SDM845_MASTER_SNOC_SF_MEM_NOC,
480
565
.channels = 1,
481
566
.buswidth = 16,
482
567
.num_links = 2,
483
-
.links = { SDM845_SLAVE_MEM_NOC_GNOC,
484
-
SDM845_SLAVE_LLCC
485
-
},
568
+
.link_nodes = { &qns_apps_io,
569
+
&qns_llcc },
486
570
};
487
571
488
572
static struct qcom_icc_node qxm_gpu = {
489
573
.name = "qxm_gpu",
490
-
.id = SDM845_MASTER_GFX3D,
491
574
.channels = 2,
492
575
.buswidth = 32,
493
576
.num_links = 3,
494
-
.links = { SDM845_SLAVE_MEM_NOC_GNOC,
495
-
SDM845_SLAVE_LLCC,
496
-
SDM845_SLAVE_MEM_NOC_SNOC
497
-
},
577
+
.link_nodes = { &qns_apps_io,
578
+
&qns_llcc,
579
+
&qns_memnoc_snoc },
498
580
};
499
581
500
582
static struct qcom_icc_node qhm_mnoc_cfg = {
501
583
.name = "qhm_mnoc_cfg",
502
-
.id = SDM845_MASTER_CNOC_MNOC_CFG,
503
584
.channels = 1,
504
585
.buswidth = 4,
505
586
.num_links = 1,
506
-
.links = { SDM845_SLAVE_SERVICE_MNOC },
587
+
.link_nodes = { &srvc_mnoc },
507
588
};
508
589
509
590
static struct qcom_icc_node qxm_camnoc_hf0 = {
510
591
.name = "qxm_camnoc_hf0",
511
-
.id = SDM845_MASTER_CAMNOC_HF0,
512
592
.channels = 1,
513
593
.buswidth = 32,
514
594
.num_links = 1,
515
-
.links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
595
+
.link_nodes = { &qns_mem_noc_hf },
516
596
};
517
597
518
598
static struct qcom_icc_node qxm_camnoc_hf1 = {
519
599
.name = "qxm_camnoc_hf1",
520
-
.id = SDM845_MASTER_CAMNOC_HF1,
521
600
.channels = 1,
522
601
.buswidth = 32,
523
602
.num_links = 1,
524
-
.links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
603
+
.link_nodes = { &qns_mem_noc_hf },
525
604
};
526
605
527
606
static struct qcom_icc_node qxm_camnoc_sf = {
528
607
.name = "qxm_camnoc_sf",
529
-
.id = SDM845_MASTER_CAMNOC_SF,
530
608
.channels = 1,
531
609
.buswidth = 32,
532
610
.num_links = 1,
533
-
.links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
611
+
.link_nodes = { &qns2_mem_noc },
534
612
};
535
613
536
614
static struct qcom_icc_node qxm_mdp0 = {
537
615
.name = "qxm_mdp0",
538
-
.id = SDM845_MASTER_MDP0,
539
616
.channels = 1,
540
617
.buswidth = 32,
541
618
.num_links = 1,
542
-
.links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
619
+
.link_nodes = { &qns_mem_noc_hf },
543
620
};
544
621
545
622
static struct qcom_icc_node qxm_mdp1 = {
546
623
.name = "qxm_mdp1",
547
-
.id = SDM845_MASTER_MDP1,
548
624
.channels = 1,
549
625
.buswidth = 32,
550
626
.num_links = 1,
551
-
.links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
627
+
.link_nodes = { &qns_mem_noc_hf },
552
628
};
553
629
554
630
static struct qcom_icc_node qxm_rot = {
555
631
.name = "qxm_rot",
556
-
.id = SDM845_MASTER_ROTATOR,
557
632
.channels = 1,
558
633
.buswidth = 32,
559
634
.num_links = 1,
560
-
.links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
635
+
.link_nodes = { &qns2_mem_noc },
561
636
};
562
637
563
638
static struct qcom_icc_node qxm_venus0 = {
564
639
.name = "qxm_venus0",
565
-
.id = SDM845_MASTER_VIDEO_P0,
566
640
.channels = 1,
567
641
.buswidth = 32,
568
642
.num_links = 1,
569
-
.links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
643
+
.link_nodes = { &qns2_mem_noc },
570
644
};
571
645
572
646
static struct qcom_icc_node qxm_venus1 = {
573
647
.name = "qxm_venus1",
574
-
.id = SDM845_MASTER_VIDEO_P1,
575
648
.channels = 1,
576
649
.buswidth = 32,
577
650
.num_links = 1,
578
-
.links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
651
+
.link_nodes = { &qns2_mem_noc },
579
652
};
580
653
581
654
static struct qcom_icc_node qxm_venus_arm9 = {
582
655
.name = "qxm_venus_arm9",
583
-
.id = SDM845_MASTER_VIDEO_PROC,
584
656
.channels = 1,
585
657
.buswidth = 8,
586
658
.num_links = 1,
587
-
.links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
659
+
.link_nodes = { &qns2_mem_noc },
588
660
};
589
661
590
662
static struct qcom_icc_node qhm_snoc_cfg = {
591
663
.name = "qhm_snoc_cfg",
592
-
.id = SDM845_MASTER_SNOC_CFG,
593
664
.channels = 1,
594
665
.buswidth = 4,
595
666
.num_links = 1,
596
-
.links = { SDM845_SLAVE_SERVICE_SNOC },
667
+
.link_nodes = { &srvc_snoc },
597
668
};
598
669
599
670
static struct qcom_icc_node qnm_aggre1_noc = {
600
671
.name = "qnm_aggre1_noc",
601
-
.id = SDM845_MASTER_A1NOC_SNOC,
602
672
.channels = 1,
603
673
.buswidth = 16,
604
674
.num_links = 6,
605
-
.links = { SDM845_SLAVE_APPSS,
606
-
SDM845_SLAVE_SNOC_CNOC,
607
-
SDM845_SLAVE_SNOC_MEM_NOC_SF,
608
-
SDM845_SLAVE_IMEM,
609
-
SDM845_SLAVE_PIMEM,
610
-
SDM845_SLAVE_QDSS_STM
611
-
},
675
+
.link_nodes = { &qhs_apss,
676
+
&qns_cnoc,
677
+
&qns_memnoc_sf,
678
+
&qxs_imem,
679
+
&qxs_pimem,
680
+
&xs_qdss_stm },
612
681
};
613
682
614
683
static struct qcom_icc_node qnm_aggre2_noc = {
615
684
.name = "qnm_aggre2_noc",
616
-
.id = SDM845_MASTER_A2NOC_SNOC,
617
685
.channels = 1,
618
686
.buswidth = 16,
619
687
.num_links = 9,
620
-
.links = { SDM845_SLAVE_APPSS,
621
-
SDM845_SLAVE_SNOC_CNOC,
622
-
SDM845_SLAVE_SNOC_MEM_NOC_SF,
623
-
SDM845_SLAVE_IMEM,
624
-
SDM845_SLAVE_PCIE_0,
625
-
SDM845_SLAVE_PCIE_1,
626
-
SDM845_SLAVE_PIMEM,
627
-
SDM845_SLAVE_QDSS_STM,
628
-
SDM845_SLAVE_TCU
629
-
},
688
+
.link_nodes = { &qhs_apss,
689
+
&qns_cnoc,
690
+
&qns_memnoc_sf,
691
+
&qxs_imem,
692
+
&qxs_pcie,
693
+
&qxs_pcie_gen3,
694
+
&qxs_pimem,
695
+
&xs_qdss_stm,
696
+
&xs_sys_tcu_cfg },
630
697
};
631
698
632
699
static struct qcom_icc_node qnm_gladiator_sodv = {
633
700
.name = "qnm_gladiator_sodv",
634
-
.id = SDM845_MASTER_GNOC_SNOC,
635
701
.channels = 1,
636
702
.buswidth = 8,
637
703
.num_links = 8,
638
-
.links = { SDM845_SLAVE_APPSS,
639
-
SDM845_SLAVE_SNOC_CNOC,
640
-
SDM845_SLAVE_IMEM,
641
-
SDM845_SLAVE_PCIE_0,
642
-
SDM845_SLAVE_PCIE_1,
643
-
SDM845_SLAVE_PIMEM,
644
-
SDM845_SLAVE_QDSS_STM,
645
-
SDM845_SLAVE_TCU
646
-
},
704
+
.link_nodes = { &qhs_apss,
705
+
&qns_cnoc,
706
+
&qxs_imem,
707
+
&qxs_pcie,
708
+
&qxs_pcie_gen3,
709
+
&qxs_pimem,
710
+
&xs_qdss_stm,
711
+
&xs_sys_tcu_cfg },
647
712
};
648
713
649
714
static struct qcom_icc_node qnm_memnoc = {
650
715
.name = "qnm_memnoc",
651
-
.id = SDM845_MASTER_MEM_NOC_SNOC,
652
716
.channels = 1,
653
717
.buswidth = 8,
654
718
.num_links = 5,
655
-
.links = { SDM845_SLAVE_APPSS,
656
-
SDM845_SLAVE_SNOC_CNOC,
657
-
SDM845_SLAVE_IMEM,
658
-
SDM845_SLAVE_PIMEM,
659
-
SDM845_SLAVE_QDSS_STM
660
-
},
719
+
.link_nodes = { &qhs_apss,
720
+
&qns_cnoc,
721
+
&qxs_imem,
722
+
&qxs_pimem,
723
+
&xs_qdss_stm },
661
724
};
662
725
663
726
static struct qcom_icc_node qnm_pcie_anoc = {
664
727
.name = "qnm_pcie_anoc",
665
-
.id = SDM845_MASTER_ANOC_PCIE_SNOC,
666
728
.channels = 1,
667
729
.buswidth = 16,
668
730
.num_links = 5,
669
-
.links = { SDM845_SLAVE_APPSS,
670
-
SDM845_SLAVE_SNOC_CNOC,
671
-
SDM845_SLAVE_SNOC_MEM_NOC_SF,
672
-
SDM845_SLAVE_IMEM,
673
-
SDM845_SLAVE_QDSS_STM
674
-
},
731
+
.link_nodes = { &qhs_apss,
732
+
&qns_cnoc,
733
+
&qns_memnoc_sf,
734
+
&qxs_imem,
735
+
&xs_qdss_stm },
675
736
};
676
737
677
738
static struct qcom_icc_node qxm_pimem = {
678
739
.name = "qxm_pimem",
679
-
.id = SDM845_MASTER_PIMEM,
680
740
.channels = 1,
681
741
.buswidth = 8,
682
742
.num_links = 2,
683
-
.links = { SDM845_SLAVE_SNOC_MEM_NOC_GC,
684
-
SDM845_SLAVE_IMEM
685
-
},
743
+
.link_nodes = { &qns_memnoc_gc,
744
+
&qxs_imem },
686
745
};
687
746
688
747
static struct qcom_icc_node xm_gic = {
689
748
.name = "xm_gic",
690
-
.id = SDM845_MASTER_GIC,
691
749
.channels = 1,
692
750
.buswidth = 8,
693
751
.num_links = 2,
694
-
.links = { SDM845_SLAVE_SNOC_MEM_NOC_GC,
695
-
SDM845_SLAVE_IMEM
696
-
},
752
+
.link_nodes = { &qns_memnoc_gc,
753
+
&qxs_imem },
697
754
};
698
755
699
756
static struct qcom_icc_node qns_a1noc_snoc = {
700
757
.name = "qns_a1noc_snoc",
701
-
.id = SDM845_SLAVE_A1NOC_SNOC,
702
758
.channels = 1,
703
759
.buswidth = 16,
704
760
.num_links = 1,
705
-
.links = { SDM845_MASTER_A1NOC_SNOC },
761
+
.link_nodes = { &qnm_aggre1_noc },
706
762
};
707
763
708
764
static struct qcom_icc_node srvc_aggre1_noc = {
709
765
.name = "srvc_aggre1_noc",
710
-
.id = SDM845_SLAVE_SERVICE_A1NOC,
711
766
.channels = 1,
712
767
.buswidth = 4,
713
-
.num_links = 1,
714
-
.links = { 0 },
715
768
};
716
769
717
770
static struct qcom_icc_node qns_pcie_a1noc_snoc = {
718
771
.name = "qns_pcie_a1noc_snoc",
719
-
.id = SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC,
720
772
.channels = 1,
721
773
.buswidth = 16,
722
774
.num_links = 1,
723
-
.links = { SDM845_MASTER_ANOC_PCIE_SNOC },
775
+
.link_nodes = { &qnm_pcie_anoc },
724
776
};
725
777
726
778
static struct qcom_icc_node qns_a2noc_snoc = {
727
779
.name = "qns_a2noc_snoc",
728
-
.id = SDM845_SLAVE_A2NOC_SNOC,
729
780
.channels = 1,
730
781
.buswidth = 16,
731
782
.num_links = 1,
732
-
.links = { SDM845_MASTER_A2NOC_SNOC },
783
+
.link_nodes = { &qnm_aggre2_noc },
733
784
};
734
785
735
786
static struct qcom_icc_node qns_pcie_snoc = {
736
787
.name = "qns_pcie_snoc",
737
-
.id = SDM845_SLAVE_ANOC_PCIE_SNOC,
738
788
.channels = 1,
739
789
.buswidth = 16,
740
790
.num_links = 1,
741
-
.links = { SDM845_MASTER_ANOC_PCIE_SNOC },
791
+
.link_nodes = { &qnm_pcie_anoc },
742
792
};
743
793
744
794
static struct qcom_icc_node srvc_aggre2_noc = {
745
795
.name = "srvc_aggre2_noc",
746
-
.id = SDM845_SLAVE_SERVICE_A2NOC,
747
796
.channels = 1,
748
797
.buswidth = 4,
749
798
};
750
799
751
800
static struct qcom_icc_node qns_camnoc_uncomp = {
752
801
.name = "qns_camnoc_uncomp",
753
-
.id = SDM845_SLAVE_CAMNOC_UNCOMP,
754
802
.channels = 1,
755
803
.buswidth = 32,
756
804
};
757
805
758
806
static struct qcom_icc_node qhs_a1_noc_cfg = {
759
807
.name = "qhs_a1_noc_cfg",
760
-
.id = SDM845_SLAVE_A1NOC_CFG,
761
808
.channels = 1,
762
809
.buswidth = 4,
763
810
.num_links = 1,
764
-
.links = { SDM845_MASTER_A1NOC_CFG },
811
+
.link_nodes = { &qhm_a1noc_cfg },
765
812
};
766
813
767
814
static struct qcom_icc_node qhs_a2_noc_cfg = {
768
815
.name = "qhs_a2_noc_cfg",
769
-
.id = SDM845_SLAVE_A2NOC_CFG,
770
816
.channels = 1,
771
817
.buswidth = 4,
772
818
.num_links = 1,
773
-
.links = { SDM845_MASTER_A2NOC_CFG },
819
+
.link_nodes = { &qhm_a2noc_cfg },
774
820
};
775
821
776
822
static struct qcom_icc_node qhs_aop = {
777
823
.name = "qhs_aop",
778
-
.id = SDM845_SLAVE_AOP,
779
824
.channels = 1,
780
825
.buswidth = 4,
781
826
};
782
827
783
828
static struct qcom_icc_node qhs_aoss = {
784
829
.name = "qhs_aoss",
785
-
.id = SDM845_SLAVE_AOSS,
786
830
.channels = 1,
787
831
.buswidth = 4,
788
832
};
789
833
790
834
static struct qcom_icc_node qhs_camera_cfg = {
791
835
.name = "qhs_camera_cfg",
792
-
.id = SDM845_SLAVE_CAMERA_CFG,
793
836
.channels = 1,
794
837
.buswidth = 4,
795
838
};
796
839
797
840
static struct qcom_icc_node qhs_clk_ctl = {
798
841
.name = "qhs_clk_ctl",
799
-
.id = SDM845_SLAVE_CLK_CTL,
800
842
.channels = 1,
801
843
.buswidth = 4,
802
844
};
803
845
804
846
static struct qcom_icc_node qhs_compute_dsp_cfg = {
805
847
.name = "qhs_compute_dsp_cfg",
806
-
.id = SDM845_SLAVE_CDSP_CFG,
807
848
.channels = 1,
808
849
.buswidth = 4,
809
850
};
810
851
811
852
static struct qcom_icc_node qhs_cpr_cx = {
812
853
.name = "qhs_cpr_cx",
813
-
.id = SDM845_SLAVE_RBCPR_CX_CFG,
814
854
.channels = 1,
815
855
.buswidth = 4,
816
856
};
817
857
818
858
static struct qcom_icc_node qhs_crypto0_cfg = {
819
859
.name = "qhs_crypto0_cfg",
820
-
.id = SDM845_SLAVE_CRYPTO_0_CFG,
821
860
.channels = 1,
822
861
.buswidth = 4,
823
862
};
824
863
825
864
static struct qcom_icc_node qhs_dcc_cfg = {
826
865
.name = "qhs_dcc_cfg",
827
-
.id = SDM845_SLAVE_DCC_CFG,
828
866
.channels = 1,
829
867
.buswidth = 4,
830
868
.num_links = 1,
831
-
.links = { SDM845_MASTER_CNOC_DC_NOC },
869
+
.link_nodes = { &qhm_cnoc },
832
870
};
833
871
834
872
static struct qcom_icc_node qhs_ddrss_cfg = {
835
873
.name = "qhs_ddrss_cfg",
836
-
.id = SDM845_SLAVE_CNOC_DDRSS,
837
874
.channels = 1,
838
875
.buswidth = 4,
839
876
};
840
877
841
878
static struct qcom_icc_node qhs_display_cfg = {
842
879
.name = "qhs_display_cfg",
843
-
.id = SDM845_SLAVE_DISPLAY_CFG,
844
880
.channels = 1,
845
881
.buswidth = 4,
846
882
};
847
883
848
884
static struct qcom_icc_node qhs_glm = {
849
885
.name = "qhs_glm",
850
-
.id = SDM845_SLAVE_GLM,
851
886
.channels = 1,
852
887
.buswidth = 4,
853
888
};
854
889
855
890
static struct qcom_icc_node qhs_gpuss_cfg = {
856
891
.name = "qhs_gpuss_cfg",
857
-
.id = SDM845_SLAVE_GFX3D_CFG,
858
892
.channels = 1,
859
893
.buswidth = 8,
860
894
};
861
895
862
896
static struct qcom_icc_node qhs_imem_cfg = {
863
897
.name = "qhs_imem_cfg",
864
-
.id = SDM845_SLAVE_IMEM_CFG,
865
898
.channels = 1,
866
899
.buswidth = 4,
867
900
};
868
901
869
902
static struct qcom_icc_node qhs_ipa = {
870
903
.name = "qhs_ipa",
871
-
.id = SDM845_SLAVE_IPA_CFG,
872
904
.channels = 1,
873
905
.buswidth = 4,
874
906
};
875
907
876
908
static struct qcom_icc_node qhs_mnoc_cfg = {
877
909
.name = "qhs_mnoc_cfg",
878
-
.id = SDM845_SLAVE_CNOC_MNOC_CFG,
879
910
.channels = 1,
880
911
.buswidth = 4,
881
912
.num_links = 1,
882
-
.links = { SDM845_MASTER_CNOC_MNOC_CFG },
913
+
.link_nodes = { &qhm_mnoc_cfg },
883
914
};
884
915
885
916
static struct qcom_icc_node qhs_pcie0_cfg = {
886
917
.name = "qhs_pcie0_cfg",
887
-
.id = SDM845_SLAVE_PCIE_0_CFG,
888
918
.channels = 1,
889
919
.buswidth = 4,
890
920
};
891
921
892
922
static struct qcom_icc_node qhs_pcie_gen3_cfg = {
893
923
.name = "qhs_pcie_gen3_cfg",
894
-
.id = SDM845_SLAVE_PCIE_1_CFG,
895
924
.channels = 1,
896
925
.buswidth = 4,
897
926
};
898
927
899
928
static struct qcom_icc_node qhs_pdm = {
900
929
.name = "qhs_pdm",
901
-
.id = SDM845_SLAVE_PDM,
902
930
.channels = 1,
903
931
.buswidth = 4,
904
932
};
905
933
906
934
static struct qcom_icc_node qhs_phy_refgen_south = {
907
935
.name = "qhs_phy_refgen_south",
908
-
.id = SDM845_SLAVE_SOUTH_PHY_CFG,
909
936
.channels = 1,
910
937
.buswidth = 4,
911
938
};
912
939
913
940
static struct qcom_icc_node qhs_pimem_cfg = {
914
941
.name = "qhs_pimem_cfg",
915
-
.id = SDM845_SLAVE_PIMEM_CFG,
916
942
.channels = 1,
917
943
.buswidth = 4,
918
944
};
919
945
920
946
static struct qcom_icc_node qhs_prng = {
921
947
.name = "qhs_prng",
922
-
.id = SDM845_SLAVE_PRNG,
923
948
.channels = 1,
924
949
.buswidth = 4,
925
950
};
926
951
927
952
static struct qcom_icc_node qhs_qdss_cfg = {
928
953
.name = "qhs_qdss_cfg",
929
-
.id = SDM845_SLAVE_QDSS_CFG,
930
954
.channels = 1,
931
955
.buswidth = 4,
932
956
};
933
957
934
958
static struct qcom_icc_node qhs_qupv3_north = {
935
959
.name = "qhs_qupv3_north",
936
-
.id = SDM845_SLAVE_BLSP_2,
937
960
.channels = 1,
938
961
.buswidth = 4,
939
962
};
940
963
941
964
static struct qcom_icc_node qhs_qupv3_south = {
942
965
.name = "qhs_qupv3_south",
943
-
.id = SDM845_SLAVE_BLSP_1,
944
966
.channels = 1,
945
967
.buswidth = 4,
946
968
};
947
969
948
970
static struct qcom_icc_node qhs_sdc2 = {
949
971
.name = "qhs_sdc2",
950
-
.id = SDM845_SLAVE_SDCC_2,
951
972
.channels = 1,
952
973
.buswidth = 4,
953
974
};
954
975
955
976
static struct qcom_icc_node qhs_sdc4 = {
956
977
.name = "qhs_sdc4",
957
-
.id = SDM845_SLAVE_SDCC_4,
958
978
.channels = 1,
959
979
.buswidth = 4,
960
980
};
961
981
962
982
static struct qcom_icc_node qhs_snoc_cfg = {
963
983
.name = "qhs_snoc_cfg",
964
-
.id = SDM845_SLAVE_SNOC_CFG,
965
984
.channels = 1,
966
985
.buswidth = 4,
967
986
.num_links = 1,
968
-
.links = { SDM845_MASTER_SNOC_CFG },
987
+
.link_nodes = { &qhm_snoc_cfg },
969
988
};
970
989
971
990
static struct qcom_icc_node qhs_spdm = {
972
991
.name = "qhs_spdm",
973
-
.id = SDM845_SLAVE_SPDM_WRAPPER,
974
992
.channels = 1,
975
993
.buswidth = 4,
976
994
};
977
995
978
996
static struct qcom_icc_node qhs_spss_cfg = {
979
997
.name = "qhs_spss_cfg",
980
-
.id = SDM845_SLAVE_SPSS_CFG,
981
998
.channels = 1,
982
999
.buswidth = 4,
983
1000
};
984
1001
985
1002
static struct qcom_icc_node qhs_tcsr = {
986
1003
.name = "qhs_tcsr",
987
-
.id = SDM845_SLAVE_TCSR,
988
1004
.channels = 1,
989
1005
.buswidth = 4,
990
1006
};
991
1007
992
1008
static struct qcom_icc_node qhs_tlmm_north = {
993
1009
.name = "qhs_tlmm_north",
994
-
.id = SDM845_SLAVE_TLMM_NORTH,
995
1010
.channels = 1,
996
1011
.buswidth = 4,
997
1012
};
998
1013
999
1014
static struct qcom_icc_node qhs_tlmm_south = {
1000
1015
.name = "qhs_tlmm_south",
1001
-
.id = SDM845_SLAVE_TLMM_SOUTH,
1002
1016
.channels = 1,
1003
1017
.buswidth = 4,
1004
1018
};
1005
1019
1006
1020
static struct qcom_icc_node qhs_tsif = {
1007
1021
.name = "qhs_tsif",
1008
-
.id = SDM845_SLAVE_TSIF,
1009
1022
.channels = 1,
1010
1023
.buswidth = 4,
1011
1024
};
1012
1025
1013
1026
static struct qcom_icc_node qhs_ufs_card_cfg = {
1014
1027
.name = "qhs_ufs_card_cfg",
1015
-
.id = SDM845_SLAVE_UFS_CARD_CFG,
1016
1028
.channels = 1,
1017
1029
.buswidth = 4,
1018
1030
};
1019
1031
1020
1032
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1021
1033
.name = "qhs_ufs_mem_cfg",
1022
-
.id = SDM845_SLAVE_UFS_MEM_CFG,
1023
1034
.channels = 1,
1024
1035
.buswidth = 4,
1025
1036
};
1026
1037
1027
1038
static struct qcom_icc_node qhs_usb3_0 = {
1028
1039
.name = "qhs_usb3_0",
1029
-
.id = SDM845_SLAVE_USB3_0,
1030
1040
.channels = 1,
1031
1041
.buswidth = 4,
1032
1042
};
1033
1043
1034
1044
static struct qcom_icc_node qhs_usb3_1 = {
1035
1045
.name = "qhs_usb3_1",
1036
-
.id = SDM845_SLAVE_USB3_1,
1037
1046
.channels = 1,
1038
1047
.buswidth = 4,
1039
1048
};
1040
1049
1041
1050
static struct qcom_icc_node qhs_venus_cfg = {
1042
1051
.name = "qhs_venus_cfg",
1043
-
.id = SDM845_SLAVE_VENUS_CFG,
1044
1052
.channels = 1,
1045
1053
.buswidth = 4,
1046
1054
};
1047
1055
1048
1056
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1049
1057
.name = "qhs_vsense_ctrl_cfg",
1050
-
.id = SDM845_SLAVE_VSENSE_CTRL_CFG,
1051
1058
.channels = 1,
1052
1059
.buswidth = 4,
1053
1060
};
1054
1061
1055
1062
static struct qcom_icc_node qns_cnoc_a2noc = {
1056
1063
.name = "qns_cnoc_a2noc",
1057
-
.id = SDM845_SLAVE_CNOC_A2NOC,
1058
1064
.channels = 1,
1059
1065
.buswidth = 8,
1060
1066
.num_links = 1,
1061
-
.links = { SDM845_MASTER_CNOC_A2NOC },
1067
+
.link_nodes = { &qnm_cnoc },
1062
1068
};
1063
1069
1064
1070
static struct qcom_icc_node srvc_cnoc = {
1065
1071
.name = "srvc_cnoc",
1066
-
.id = SDM845_SLAVE_SERVICE_CNOC,
1067
1072
.channels = 1,
1068
1073
.buswidth = 4,
1069
1074
};
1070
1075
1071
1076
static struct qcom_icc_node qhs_llcc = {
1072
1077
.name = "qhs_llcc",
1073
-
.id = SDM845_SLAVE_LLCC_CFG,
1074
1078
.channels = 1,
1075
1079
.buswidth = 4,
1076
1080
};
1077
1081
1078
1082
static struct qcom_icc_node qhs_memnoc = {
1079
1083
.name = "qhs_memnoc",
1080
-
.id = SDM845_SLAVE_MEM_NOC_CFG,
1081
1084
.channels = 1,
1082
1085
.buswidth = 4,
1083
1086
.num_links = 1,
1084
-
.links = { SDM845_MASTER_MEM_NOC_CFG },
1087
+
.link_nodes = { &qhm_memnoc_cfg },
1085
1088
};
1086
1089
1087
1090
static struct qcom_icc_node qns_gladiator_sodv = {
1088
1091
.name = "qns_gladiator_sodv",
1089
-
.id = SDM845_SLAVE_GNOC_SNOC,
1090
1092
.channels = 1,
1091
1093
.buswidth = 8,
1092
1094
.num_links = 1,
1093
-
.links = { SDM845_MASTER_GNOC_SNOC },
1095
+
.link_nodes = { &qnm_gladiator_sodv },
1094
1096
};
1095
1097
1096
1098
static struct qcom_icc_node qns_gnoc_memnoc = {
1097
1099
.name = "qns_gnoc_memnoc",
1098
-
.id = SDM845_SLAVE_GNOC_MEM_NOC,
1099
1100
.channels = 2,
1100
1101
.buswidth = 32,
1101
1102
.num_links = 1,
1102
-
.links = { SDM845_MASTER_GNOC_MEM_NOC },
1103
+
.link_nodes = { &qnm_apps },
1103
1104
};
1104
1105
1105
1106
static struct qcom_icc_node srvc_gnoc = {
1106
1107
.name = "srvc_gnoc",
1107
-
.id = SDM845_SLAVE_SERVICE_GNOC,
1108
1108
.channels = 1,
1109
1109
.buswidth = 4,
1110
1110
};
1111
1111
1112
1112
static struct qcom_icc_node ebi = {
1113
1113
.name = "ebi",
1114
-
.id = SDM845_SLAVE_EBI1,
1115
1114
.channels = 4,
1116
1115
.buswidth = 4,
1117
1116
};
1118
1117
1119
1118
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1120
1119
.name = "qhs_mdsp_ms_mpu_cfg",
1121
-
.id = SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
1122
1120
.channels = 1,
1123
1121
.buswidth = 4,
1124
1122
};
1125
1123
1126
1124
static struct qcom_icc_node qns_apps_io = {
1127
1125
.name = "qns_apps_io",
1128
-
.id = SDM845_SLAVE_MEM_NOC_GNOC,
1129
1126
.channels = 1,
1130
1127
.buswidth = 32,
1131
1128
};
1132
1129
1133
1130
static struct qcom_icc_node qns_llcc = {
1134
1131
.name = "qns_llcc",
1135
-
.id = SDM845_SLAVE_LLCC,
1136
1132
.channels = 4,
1137
1133
.buswidth = 16,
1138
1134
.num_links = 1,
1139
-
.links = { SDM845_MASTER_LLCC },
1135
+
.link_nodes = { &llcc_mc },
1140
1136
};
1141
1137
1142
1138
static struct qcom_icc_node qns_memnoc_snoc = {
1143
1139
.name = "qns_memnoc_snoc",
1144
-
.id = SDM845_SLAVE_MEM_NOC_SNOC,
1145
1140
.channels = 1,
1146
1141
.buswidth = 8,
1147
1142
.num_links = 1,
1148
-
.links = { SDM845_MASTER_MEM_NOC_SNOC },
1143
+
.link_nodes = { &qnm_memnoc },
1149
1144
};
1150
1145
1151
1146
static struct qcom_icc_node srvc_memnoc = {
1152
1147
.name = "srvc_memnoc",
1153
-
.id = SDM845_SLAVE_SERVICE_MEM_NOC,
1154
1148
.channels = 1,
1155
1149
.buswidth = 4,
1156
1150
};
1157
1151
1158
1152
static struct qcom_icc_node qns2_mem_noc = {
1159
1153
.name = "qns2_mem_noc",
1160
-
.id = SDM845_SLAVE_MNOC_SF_MEM_NOC,
1161
1154
.channels = 1,
1162
1155
.buswidth = 32,
1163
1156
.num_links = 1,
1164
-
.links = { SDM845_MASTER_MNOC_SF_MEM_NOC },
1157
+
.link_nodes = { &qnm_mnoc_sf },
1165
1158
};
1166
1159
1167
1160
static struct qcom_icc_node qns_mem_noc_hf = {
1168
1161
.name = "qns_mem_noc_hf",
1169
-
.id = SDM845_SLAVE_MNOC_HF_MEM_NOC,
1170
1162
.channels = 2,
1171
1163
.buswidth = 32,
1172
1164
.num_links = 1,
1173
-
.links = { SDM845_MASTER_MNOC_HF_MEM_NOC },
1165
+
.link_nodes = { &qnm_mnoc_hf },
1174
1166
};
1175
1167
1176
1168
static struct qcom_icc_node srvc_mnoc = {
1177
1169
.name = "srvc_mnoc",
1178
-
.id = SDM845_SLAVE_SERVICE_MNOC,
1179
1170
.channels = 1,
1180
1171
.buswidth = 4,
1181
1172
};
1182
1173
1183
1174
static struct qcom_icc_node qhs_apss = {
1184
1175
.name = "qhs_apss",
1185
-
.id = SDM845_SLAVE_APPSS,
1186
1176
.channels = 1,
1187
1177
.buswidth = 8,
1188
1178
};
1189
1179
1190
1180
static struct qcom_icc_node qns_cnoc = {
1191
1181
.name = "qns_cnoc",
1192
-
.id = SDM845_SLAVE_SNOC_CNOC,
1193
1182
.channels = 1,
1194
1183
.buswidth = 8,
1195
1184
.num_links = 1,
1196
-
.links = { SDM845_MASTER_SNOC_CNOC },
1185
+
.link_nodes = { &qnm_snoc },
1197
1186
};
1198
1187
1199
1188
static struct qcom_icc_node qns_memnoc_gc = {
1200
1189
.name = "qns_memnoc_gc",
1201
-
.id = SDM845_SLAVE_SNOC_MEM_NOC_GC,
1202
1190
.channels = 1,
1203
1191
.buswidth = 8,
1204
1192
.num_links = 1,
1205
-
.links = { SDM845_MASTER_SNOC_GC_MEM_NOC },
1193
+
.link_nodes = { &qnm_snoc_gc },
1206
1194
};
1207
1195
1208
1196
static struct qcom_icc_node qns_memnoc_sf = {
1209
1197
.name = "qns_memnoc_sf",
1210
-
.id = SDM845_SLAVE_SNOC_MEM_NOC_SF,
1211
1198
.channels = 1,
1212
1199
.buswidth = 16,
1213
1200
.num_links = 1,
1214
-
.links = { SDM845_MASTER_SNOC_SF_MEM_NOC },
1201
+
.link_nodes = { &qnm_snoc_sf },
1215
1202
};
1216
1203
1217
1204
static struct qcom_icc_node qxs_imem = {
1218
1205
.name = "qxs_imem",
1219
-
.id = SDM845_SLAVE_IMEM,
1220
1206
.channels = 1,
1221
1207
.buswidth = 8,
1222
1208
};
1223
1209
1224
1210
static struct qcom_icc_node qxs_pcie = {
1225
1211
.name = "qxs_pcie",
1226
-
.id = SDM845_SLAVE_PCIE_0,
1227
1212
.channels = 1,
1228
1213
.buswidth = 8,
1229
1214
};
1230
1215
1231
1216
static struct qcom_icc_node qxs_pcie_gen3 = {
1232
1217
.name = "qxs_pcie_gen3",
1233
-
.id = SDM845_SLAVE_PCIE_1,
1234
1218
.channels = 1,
1235
1219
.buswidth = 8,
1236
1220
};
1237
1221
1238
1222
static struct qcom_icc_node qxs_pimem = {
1239
1223
.name = "qxs_pimem",
1240
-
.id = SDM845_SLAVE_PIMEM,
1241
1224
.channels = 1,
1242
1225
.buswidth = 8,
1243
1226
};
1244
1227
1245
1228
static struct qcom_icc_node srvc_snoc = {
1246
1229
.name = "srvc_snoc",
1247
-
.id = SDM845_SLAVE_SERVICE_SNOC,
1248
1230
.channels = 1,
1249
1231
.buswidth = 4,
1250
1232
};
1251
1233
1252
1234
static struct qcom_icc_node xs_qdss_stm = {
1253
1235
.name = "xs_qdss_stm",
1254
-
.id = SDM845_SLAVE_QDSS_STM,
1255
1236
.channels = 1,
1256
1237
.buswidth = 4,
1257
1238
};
1258
1239
1259
1240
static struct qcom_icc_node xs_sys_tcu_cfg = {
1260
1241
.name = "xs_sys_tcu_cfg",
1261
-
.id = SDM845_SLAVE_TCU,
1262
1242
.channels = 1,
1263
1243
.buswidth = 8,
1264
1244
};
···
1514
1534
};
1515
1535
1516
1536
static const struct qcom_icc_desc sdm845_aggre1_noc = {
1537
+
.alloc_dyn_id = true,
1517
1538
.nodes = aggre1_noc_nodes,
1518
1539
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1519
1540
.bcms = aggre1_noc_bcms,
···
1544
1563
};
1545
1564
1546
1565
static const struct qcom_icc_desc sdm845_aggre2_noc = {
1566
+
.alloc_dyn_id = true,
1547
1567
.nodes = aggre2_noc_nodes,
1548
1568
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1549
1569
.bcms = aggre2_noc_bcms,
···
1606
1624
};
1607
1625
1608
1626
static const struct qcom_icc_desc sdm845_config_noc = {
1627
+
.alloc_dyn_id = true,
1609
1628
.nodes = config_noc_nodes,
1610
1629
.num_nodes = ARRAY_SIZE(config_noc_nodes),
1611
1630
.bcms = config_noc_bcms,
···
1623
1640
};
1624
1641
1625
1642
static const struct qcom_icc_desc sdm845_dc_noc = {
1643
+
.alloc_dyn_id = true,
1626
1644
.nodes = dc_noc_nodes,
1627
1645
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1628
1646
.bcms = dc_noc_bcms,
···
1642
1658
};
1643
1659
1644
1660
static const struct qcom_icc_desc sdm845_gladiator_noc = {
1661
+
.alloc_dyn_id = true,
1645
1662
.nodes = gladiator_noc_nodes,
1646
1663
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
1647
1664
.bcms = gladiator_noc_bcms,
···
1678
1693
};
1679
1694
1680
1695
static const struct qcom_icc_desc sdm845_mem_noc = {
1696
+
.alloc_dyn_id = true,
1681
1697
.nodes = mem_noc_nodes,
1682
1698
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
1683
1699
.bcms = mem_noc_bcms,
···
1713
1727
};
1714
1728
1715
1729
static const struct qcom_icc_desc sdm845_mmss_noc = {
1730
+
.alloc_dyn_id = true,
1716
1731
.nodes = mmss_noc_nodes,
1717
1732
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1718
1733
.bcms = mmss_noc_bcms,
···
1760
1773
};
1761
1774
1762
1775
static const struct qcom_icc_desc sdm845_system_noc = {
1776
+
.alloc_dyn_id = true,
1763
1777
.nodes = system_noc_nodes,
1764
1778
.num_nodes = ARRAY_SIZE(system_noc_nodes),
1765
1779
.bcms = system_noc_bcms,
-140
drivers/interconnect/qcom/sdm845.h
-140
drivers/interconnect/qcom/sdm845.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4
-
*/
5
-
6
-
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
7
-
#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
8
-
9
-
#define SDM845_MASTER_A1NOC_CFG 1
10
-
#define SDM845_MASTER_BLSP_1 2
11
-
#define SDM845_MASTER_TSIF 3
12
-
#define SDM845_MASTER_SDCC_2 4
13
-
#define SDM845_MASTER_SDCC_4 5
14
-
#define SDM845_MASTER_UFS_CARD 6
15
-
#define SDM845_MASTER_UFS_MEM 7
16
-
#define SDM845_MASTER_PCIE_0 8
17
-
#define SDM845_MASTER_A2NOC_CFG 9
18
-
#define SDM845_MASTER_QDSS_BAM 10
19
-
#define SDM845_MASTER_BLSP_2 11
20
-
#define SDM845_MASTER_CNOC_A2NOC 12
21
-
#define SDM845_MASTER_CRYPTO 13
22
-
#define SDM845_MASTER_IPA 14
23
-
#define SDM845_MASTER_PCIE_1 15
24
-
#define SDM845_MASTER_QDSS_ETR 16
25
-
#define SDM845_MASTER_USB3_0 17
26
-
#define SDM845_MASTER_USB3_1 18
27
-
#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19
28
-
#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20
29
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#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21
30
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#define SDM845_MASTER_SPDM 22
31
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#define SDM845_MASTER_TIC 23
32
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#define SDM845_MASTER_SNOC_CNOC 24
33
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#define SDM845_MASTER_QDSS_DAP 25
34
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#define SDM845_MASTER_CNOC_DC_NOC 26
35
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#define SDM845_MASTER_APPSS_PROC 27
36
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#define SDM845_MASTER_GNOC_CFG 28
37
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#define SDM845_MASTER_LLCC 29
38
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#define SDM845_MASTER_TCU_0 30
39
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#define SDM845_MASTER_MEM_NOC_CFG 31
40
-
#define SDM845_MASTER_GNOC_MEM_NOC 32
41
-
#define SDM845_MASTER_MNOC_HF_MEM_NOC 33
42
-
#define SDM845_MASTER_MNOC_SF_MEM_NOC 34
43
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#define SDM845_MASTER_SNOC_GC_MEM_NOC 35
44
-
#define SDM845_MASTER_SNOC_SF_MEM_NOC 36
45
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#define SDM845_MASTER_GFX3D 37
46
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#define SDM845_MASTER_CNOC_MNOC_CFG 38
47
-
#define SDM845_MASTER_CAMNOC_HF0 39
48
-
#define SDM845_MASTER_CAMNOC_HF1 40
49
-
#define SDM845_MASTER_CAMNOC_SF 41
50
-
#define SDM845_MASTER_MDP0 42
51
-
#define SDM845_MASTER_MDP1 43
52
-
#define SDM845_MASTER_ROTATOR 44
53
-
#define SDM845_MASTER_VIDEO_P0 45
54
-
#define SDM845_MASTER_VIDEO_P1 46
55
-
#define SDM845_MASTER_VIDEO_PROC 47
56
-
#define SDM845_MASTER_SNOC_CFG 48
57
-
#define SDM845_MASTER_A1NOC_SNOC 49
58
-
#define SDM845_MASTER_A2NOC_SNOC 50
59
-
#define SDM845_MASTER_GNOC_SNOC 51
60
-
#define SDM845_MASTER_MEM_NOC_SNOC 52
61
-
#define SDM845_MASTER_ANOC_PCIE_SNOC 53
62
-
#define SDM845_MASTER_PIMEM 54
63
-
#define SDM845_MASTER_GIC 55
64
-
#define SDM845_SLAVE_A1NOC_SNOC 56
65
-
#define SDM845_SLAVE_SERVICE_A1NOC 57
66
-
#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58
67
-
#define SDM845_SLAVE_A2NOC_SNOC 59
68
-
#define SDM845_SLAVE_ANOC_PCIE_SNOC 60
69
-
#define SDM845_SLAVE_SERVICE_A2NOC 61
70
-
#define SDM845_SLAVE_CAMNOC_UNCOMP 62
71
-
#define SDM845_SLAVE_A1NOC_CFG 63
72
-
#define SDM845_SLAVE_A2NOC_CFG 64
73
-
#define SDM845_SLAVE_AOP 65
74
-
#define SDM845_SLAVE_AOSS 66
75
-
#define SDM845_SLAVE_CAMERA_CFG 67
76
-
#define SDM845_SLAVE_CLK_CTL 68
77
-
#define SDM845_SLAVE_CDSP_CFG 69
78
-
#define SDM845_SLAVE_RBCPR_CX_CFG 70
79
-
#define SDM845_SLAVE_CRYPTO_0_CFG 71
80
-
#define SDM845_SLAVE_DCC_CFG 72
81
-
#define SDM845_SLAVE_CNOC_DDRSS 73
82
-
#define SDM845_SLAVE_DISPLAY_CFG 74
83
-
#define SDM845_SLAVE_GLM 75
84
-
#define SDM845_SLAVE_GFX3D_CFG 76
85
-
#define SDM845_SLAVE_IMEM_CFG 77
86
-
#define SDM845_SLAVE_IPA_CFG 78
87
-
#define SDM845_SLAVE_CNOC_MNOC_CFG 79
88
-
#define SDM845_SLAVE_PCIE_0_CFG 80
89
-
#define SDM845_SLAVE_PCIE_1_CFG 81
90
-
#define SDM845_SLAVE_PDM 82
91
-
#define SDM845_SLAVE_SOUTH_PHY_CFG 83
92
-
#define SDM845_SLAVE_PIMEM_CFG 84
93
-
#define SDM845_SLAVE_PRNG 85
94
-
#define SDM845_SLAVE_QDSS_CFG 86
95
-
#define SDM845_SLAVE_BLSP_2 87
96
-
#define SDM845_SLAVE_BLSP_1 88
97
-
#define SDM845_SLAVE_SDCC_2 89
98
-
#define SDM845_SLAVE_SDCC_4 90
99
-
#define SDM845_SLAVE_SNOC_CFG 91
100
-
#define SDM845_SLAVE_SPDM_WRAPPER 92
101
-
#define SDM845_SLAVE_SPSS_CFG 93
102
-
#define SDM845_SLAVE_TCSR 94
103
-
#define SDM845_SLAVE_TLMM_NORTH 95
104
-
#define SDM845_SLAVE_TLMM_SOUTH 96
105
-
#define SDM845_SLAVE_TSIF 97
106
-
#define SDM845_SLAVE_UFS_CARD_CFG 98
107
-
#define SDM845_SLAVE_UFS_MEM_CFG 99
108
-
#define SDM845_SLAVE_USB3_0 100
109
-
#define SDM845_SLAVE_USB3_1 101
110
-
#define SDM845_SLAVE_VENUS_CFG 102
111
-
#define SDM845_SLAVE_VSENSE_CTRL_CFG 103
112
-
#define SDM845_SLAVE_CNOC_A2NOC 104
113
-
#define SDM845_SLAVE_SERVICE_CNOC 105
114
-
#define SDM845_SLAVE_LLCC_CFG 106
115
-
#define SDM845_SLAVE_MEM_NOC_CFG 107
116
-
#define SDM845_SLAVE_GNOC_SNOC 108
117
-
#define SDM845_SLAVE_GNOC_MEM_NOC 109
118
-
#define SDM845_SLAVE_SERVICE_GNOC 110
119
-
#define SDM845_SLAVE_EBI1 111
120
-
#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112
121
-
#define SDM845_SLAVE_MEM_NOC_GNOC 113
122
-
#define SDM845_SLAVE_LLCC 114
123
-
#define SDM845_SLAVE_MEM_NOC_SNOC 115
124
-
#define SDM845_SLAVE_SERVICE_MEM_NOC 116
125
-
#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117
126
-
#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118
127
-
#define SDM845_SLAVE_SERVICE_MNOC 119
128
-
#define SDM845_SLAVE_APPSS 120
129
-
#define SDM845_SLAVE_SNOC_CNOC 121
130
-
#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122
131
-
#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123
132
-
#define SDM845_SLAVE_IMEM 124
133
-
#define SDM845_SLAVE_PCIE_0 125
134
-
#define SDM845_SLAVE_PCIE_1 126
135
-
#define SDM845_SLAVE_PIMEM 127
136
-
#define SDM845_SLAVE_SERVICE_SNOC 128
137
-
#define SDM845_SLAVE_QDSS_STM 129
138
-
#define SDM845_SLAVE_TCU 130
139
-
140
-
#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */