tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

When set, starting xe3p_lpg, the L2 flush optimization
feature will control whether L2 is in Persistent or
Transient mode through monitoring of media activity.

To enable L2 flush optimization include new feature flag
GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
media type is detected.

Tighten UAPI validation to restrict userptr, svm and
dmabuf mappings to be either 2WAY or XA+1WAY

V5(Thomas): logic correction
V4(MattA): Modify uapi doc and commit
V3(MattA): check valid op and pat_index value
V2(MattA): validate dma-buf bos and madvise pat-index

Acked-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
Acked-by: Carl Zhang <carl.zhang@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260305121902.1892593-9-tejas.upadhyay@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

Tejas Upadhyay 4f39a194 411389d2

+38 -1
+3
drivers/gpu/drm/xe/xe_guc.c
··· 98 98 if (xe_guc_using_main_gamctrl_queues(guc)) 99 99 flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES; 100 100 101 + if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc))) 102 + flags |= GUC_CTL_ENABLE_L2FLUSH_OPT; 103 + 101 104 return flags; 102 105 } 103 106
+1
drivers/gpu/drm/xe/xe_guc_fwif.h
··· 67 67 #define GUC_CTL_ENABLE_PSMI_LOGGING BIT(7) 68 68 #define GUC_CTL_MAIN_GAMCTRL_QUEUES BIT(9) 69 69 #define GUC_CTL_DISABLE_SCHEDULER BIT(14) 70 + #define GUC_CTL_ENABLE_L2FLUSH_OPT BIT(15) 70 71 71 72 #define GUC_CTL_DEBUG 3 72 73 #define GUC_LOG_VERBOSITY REG_GENMASK(1, 0)
+8
drivers/gpu/drm/xe/xe_vm.c
··· 3492 3492 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || 3493 3493 XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE && 3494 3494 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || 3495 + XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) && 3496 + (op == DRM_XE_VM_BIND_OP_MAP_USERPTR || 3497 + is_cpu_addr_mirror) && 3498 + (pat_index != 19 && coh_mode != XE_COH_2WAY)) || 3495 3499 XE_IOCTL_DBG(xe, comp_en && 3496 3500 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || 3497 3501 XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR && ··· 3635 3631 */ 3636 3632 comp_en = xe_pat_index_get_comp_en(xe, pat_index); 3637 3633 if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en)) 3634 + return -EINVAL; 3635 + 3636 + if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && xe_device_is_l2_flush_optimized(xe) && 3637 + (pat_index != 19 && coh_mode != XE_COH_2WAY))) 3638 3638 return -EINVAL; 3639 3639 3640 3640 /* If a BO is protected it can only be mapped if the key is still valid */
+23
drivers/gpu/drm/xe/xe_vm_madvise.c
··· 419 419 struct xe_vmas_in_madvise_range madvise_range = {.addr = args->start, 420 420 .range = args->range, }; 421 421 struct xe_madvise_details details; 422 + u16 pat_index, coh_mode; 422 423 struct xe_vm *vm; 423 424 struct drm_exec exec; 424 425 int err, attr_type; ··· 456 455 if (err || !madvise_range.num_vmas) 457 456 goto madv_fini; 458 457 458 + if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) { 459 + pat_index = array_index_nospec(args->pat_index.val, xe->pat.n_entries); 460 + coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); 461 + if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas && 462 + xe_device_is_l2_flush_optimized(xe) && 463 + (pat_index != 19 && coh_mode != XE_COH_2WAY))) { 464 + err = -EINVAL; 465 + goto madv_fini; 466 + } 467 + } 468 + 459 469 if (madvise_range.has_bo_vmas) { 460 470 if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) { 461 471 if (!check_bo_args_are_sane(vm, madvise_range.vmas, ··· 484 472 485 473 if (!bo) 486 474 continue; 475 + 476 + if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) { 477 + if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && 478 + xe_device_is_l2_flush_optimized(xe) && 479 + (pat_index != 19 && 480 + coh_mode != XE_COH_2WAY))) { 481 + err = -EINVAL; 482 + goto err_fini; 483 + } 484 + } 485 + 487 486 err = drm_exec_lock_obj(&exec, &bo->ttm.base); 488 487 drm_exec_retry_on_contention(&exec); 489 488 if (err)
+3 -1
include/uapi/drm/xe_drm.h
··· 1114 1114 * incoherent GT access is possible. 1115 1115 * 1116 1116 * Note: For userptr and externally imported dma-buf the kernel expects 1117 - * either 1WAY or 2WAY for the @pat_index. 1117 + * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for 1118 + * userptr, svm, madvise and externally imported dma-buf the kernel expects 1119 + * either 2WAY or 1WAY and XA @pat_index. 1118 1120 * 1119 1121 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions 1120 1122 * on the @pat_index. For such mappings there is no actual memory being