Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/rcar-du: dsi: Convert register bitfields to GENMASK() macro
Convert register bitfields to GENMASK() macro where applicable.
Use FIELD_PREP() throughout the driver.
Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/20251028232959.109936-12-marek.vasut+renesas@mailbox.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
authored by
Marek Vasut
and committed by
Tomi Valkeinen
4f716a1d
6ade1742
+70
-48
+70
-48
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
+70
-48
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
···
13
13
#define LINKSR_HSBUSY BIT_U32(0)
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14
15
15
#define TXSETR 0x100
16
-
#define TXSETR_LANECNT_MASK GENMASK(1, 0)
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+
#define TXSETR_LANECNT_MASK GENMASK_U32(1, 0)
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/*
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* DSI Command Transfer Registers
···
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#define TXCMADDRSET0R 0x140
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#define TXCMPHDR 0x150
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#define TXCMPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */
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-
#define TXCMPHDR_VC(n) (((n) & 0x3) << 22)
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-
#define TXCMPHDR_DT(n) (((n) & 0x3f) << 16)
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-
#define TXCMPHDR_DATA1(n) (((n) & 0xff) << 8)
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-
#define TXCMPHDR_DATA0(n) (((n) & 0xff) << 0)
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#define TXCMPHDR_VC_MASK GENMASK_U32(23, 22)
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#define TXCMPHDR_VC(n) FIELD_PREP(TXCMPHDR_VC_MASK, (n))
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#define TXCMPHDR_DT_MASK GENMASK_U32(21, 16)
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#define TXCMPHDR_DT(n) FIELD_PREP(TXCMPHDR_DT_MASK, (n))
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#define TXCMPHDR_DATA1_MASK GENMASK_U32(15, 8)
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#define TXCMPHDR_DATA1(n) FIELD_PREP(TXCMPHDR_DATA1_MASK, (n))
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#define TXCMPHDR_DATA0_MASK GENMASK_U32(7, 0)
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#define TXCMPHDR_DATA0(n) FIELD_PREP(TXCMPHDR_DATA0_MASK, (n))
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#define TXCMPPD0R 0x160
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#define TXCMPPD1R 0x164
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#define TXCMPPD2R 0x168
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#define TXCMPPD3R 0x16c
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#define RXSETR 0x200
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-
#define RXSETR_CRCEN(n) (((n) & 0xf) << 24)
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-
#define RXSETR_ECCEN(n) (((n) & 0xf) << 16)
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+
#define RXSETR_CRCEN_MASK GENMASK_U32(27, 24)
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+
#define RXSETR_ECCEN_MASK GENMASK_U32(19, 16)
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#define RXPSETR 0x210
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#define RXPSETR_LPPDACC BIT_U32(0)
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#define RXPSR 0x220
···
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107
#define RXPIER_BTAREQEND BIT_U32(0)
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#define RXPADDRSET0R 0x230
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#define RXPSIZESETR 0x238
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-
#define RXPSIZESETR_SIZE(n) (((n) & 0xf) << 3)
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#define RXPSIZESETR_SIZE_MASK GENMASK_U32(6, 3)
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111
#define RXPHDR 0x240
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#define RXPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */
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-
#define RXPHDR_VC(n) (((n) & 0x3) << 22)
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-
#define RXPHDR_DT(n) (((n) & 0x3f) << 16)
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-
#define RXPHDR_DATA1(n) (((n) & 0xff) << 8)
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-
#define RXPHDR_DATA0(n) (((n) & 0xff) << 0)
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#define RXPHDR_VC_MASK GENMASK_U32(23, 22)
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#define RXPHDR_DT_MASK GENMASK_U32(21, 16)
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#define RXPHDR_DATA1_MASK GENMASK_U32(15, 8)
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#define RXPHDR_DATA0_MASK GENMASK_U32(7, 0)
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#define RXPPD0R 0x250
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#define RXPPD1R 0x254
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#define RXPPD2R 0x258
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#define RXPPD3R 0x25c
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#define AKEPR 0x300
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-
#define AKEPR_VC(n) (((n) & 0x3) << 22)
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-
#define AKEPR_DT(n) (((n) & 0x3f) << 16)
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-
#define AKEPR_ERRRPT(n) (((n) & 0xffff) << 0)
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#define AKEPR_VC_MASK GENMASK_U32(23, 22)
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#define AKEPR_DT_MASK GENMASK_U32(21, 16)
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#define AKEPR_ERRRPT_MASK GENMASK_U32(15, 0)
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#define RXRESPTOSETR 0x400
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#define TACR 0x500
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127
#define TASR 0x510
···
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#define TXVMSETR 0x180
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#define TXVMSETR_SYNSEQ_EVENTS BIT_U32(16) /* 0:Pulses 1:Events */
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#define TXVMSETR_VSTPM BIT_U32(15)
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-
#define TXVMSETR_PIXWDTH_MASK GENMASK(10, 8)
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#define TXVMSETR_PIXWDTH_MASK GENMASK_U32(10, 8)
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#define TXVMSETR_PIXWDTH BIT_U32(8) /* Only allowed value */
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#define TXVMSETR_VSEN BIT_U32(4)
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#define TXVMSETR_HFPBPEN BIT_U32(2)
···
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#define TXVMVPRMSET0R_HSPOL_LOW BIT_U32(17) /* 0:High 1:Low */
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#define TXVMVPRMSET0R_VSPOL_LOW BIT_U32(16) /* 0:High 1:Low */
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#define TXVMVPRMSET0R_CSPC_YCbCr BIT_U32(4) /* 0:RGB 1:YCbCr */
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-
#define TXVMVPRMSET0R_BPP_MASK GENMASK(2, 0)
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#define TXVMVPRMSET0R_BPP_MASK GENMASK_U32(2, 0)
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#define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0)
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#define TXVMVPRMSET0R_BPP_18 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1)
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#define TXVMVPRMSET0R_BPP_24 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2)
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#define TXVMVPRMSET1R 0x1d4
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-
#define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16)
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-
#define TXVMVPRMSET1R_VSA(x) (((x) & 0xfff) << 0)
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#define TXVMVPRMSET1R_VACTIVE_MASK GENMASK_U32(30, 16)
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#define TXVMVPRMSET1R_VACTIVE(n) FIELD_PREP(TXVMVPRMSET1R_VACTIVE_MASK, (n))
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#define TXVMVPRMSET1R_VSA_MASK GENMASK_U32(11, 0)
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#define TXVMVPRMSET1R_VSA(n) FIELD_PREP(TXVMVPRMSET1R_VSA_MASK, (n))
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#define TXVMVPRMSET2R 0x1d8
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-
#define TXVMVPRMSET2R_VFP(x) (((x) & 0x1fff) << 16)
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-
#define TXVMVPRMSET2R_VBP(x) (((x) & 0x1fff) << 0)
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+
#define TXVMVPRMSET2R_VFP_MASK GENMASK_U32(28, 16)
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#define TXVMVPRMSET2R_VFP(n) FIELD_PREP(TXVMVPRMSET2R_VFP_MASK, (n))
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#define TXVMVPRMSET2R_VBP_MASK GENMASK_U32(12, 0)
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#define TXVMVPRMSET2R_VBP(n) FIELD_PREP(TXVMVPRMSET2R_VBP_MASK, (n))
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#define TXVMVPRMSET3R 0x1dc
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-
#define TXVMVPRMSET3R_HACTIVE(x) (((x) & 0x7fff) << 16)
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-
#define TXVMVPRMSET3R_HSA(x) (((x) & 0xfff) << 0)
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+
#define TXVMVPRMSET3R_HACTIVE_MASK GENMASK_U32(30, 16)
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#define TXVMVPRMSET3R_HACTIVE(n) FIELD_PREP(TXVMVPRMSET3R_HACTIVE_MASK, (n))
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#define TXVMVPRMSET3R_HSA_MASK GENMASK_U32(11, 0)
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#define TXVMVPRMSET3R_HSA(n) FIELD_PREP(TXVMVPRMSET3R_HSA_MASK, (n))
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#define TXVMVPRMSET4R 0x1e0
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-
#define TXVMVPRMSET4R_HFP(x) (((x) & 0x1fff) << 16)
200
-
#define TXVMVPRMSET4R_HBP(x) (((x) & 0x1fff) << 0)
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+
#define TXVMVPRMSET4R_HFP_MASK GENMASK_U32(28, 16)
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#define TXVMVPRMSET4R_HFP(n) FIELD_PREP(TXVMVPRMSET4R_HFP_MASK, (n))
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#define TXVMVPRMSET4R_HBP_MASK GENMASK_U32(12, 0)
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+
#define TXVMVPRMSET4R_HBP(n) FIELD_PREP(TXVMVPRMSET4R_HBP_MASK, (n))
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/*
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* PHY-Protocol Interface (PPI) Registers
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*/
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#define PPISETR 0x700
206
-
#define PPISETR_DLEN_MASK GENMASK(3, 0)
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+
#define PPISETR_DLEN_MASK GENMASK_U32(3, 0)
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#define PPISETR_CLEN BIT_U32(8)
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#define PPICLCR 0x710
···
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#define PPIDL0SR_STPST BIT_U32(6)
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#define PPIDLSR 0x760
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-
#define PPIDLSR_STPST GENMASK(3, 0)
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+
#define PPIDLSR_STPST GENMASK_U32(3, 0)
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/*
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* Clocks registers
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*/
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#define LPCLKSET 0x1000
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230
#define LPCLKSET_CKEN BIT_U32(8)
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-
#define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0)
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+
#define LPCLKSET_LPCLKDIV_MASK GENMASK_U32(5, 0)
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#define CFGCLKSET 0x1004
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#define CFGCLKSET_CKEN BIT_U32(8)
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-
#define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0)
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+
#define CFGCLKSET_CFGCLKDIV_MASK GENMASK_U32(5, 0)
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#define DOTCLKDIV 0x1008
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#define DOTCLKDIV_CKEN BIT_U32(8)
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-
#define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0)
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+
#define DOTCLKDIV_DOTCLKDIV_MASK GENMASK_U32(5, 0)
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240
253
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#define VCLKSET 0x100c
254
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#define VCLKSET_CKEN BIT_U32(16)
255
243
#define VCLKSET_COLOR_YCC BIT_U32(8) /* 0:RGB 1:YCbCr */
256
-
#define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4)
257
-
#define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4)
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-
#define VCLKSET_BPP_MASK GENMASK(3, 2)
244
+
#define VCLKSET_DIV_V3U_MASK GENMASK_U32(5, 4)
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+
#define VCLKSET_DIV_V3U(n) FIELD_PREP(VCLKSET_DIV_V3U_MASK, (n))
246
+
#define VCLKSET_DIV_V4H_MASK GENMASK_U32(6, 4)
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+
#define VCLKSET_DIV_V4H(n) FIELD_PREP(VCLKSET_DIV_V4H_MASK, (n))
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+
#define VCLKSET_BPP_MASK GENMASK_U32(3, 2)
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#define VCLKSET_BPP_16 FIELD_PREP(VCLKSET_BPP_MASK, 0)
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#define VCLKSET_BPP_18 FIELD_PREP(VCLKSET_BPP_MASK, 1)
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#define VCLKSET_BPP_18L FIELD_PREP(VCLKSET_BPP_MASK, 2)
262
252
#define VCLKSET_BPP_24 FIELD_PREP(VCLKSET_BPP_MASK, 3)
263
-
#define VCLKSET_LANE(x) (((x) & 0x3) << 0)
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+
#define VCLKSET_LANE_MASK GENMASK_U32(1, 0)
254
+
#define VCLKSET_LANE(n) FIELD_PREP(VCLKSET_LANE_MASK, (n))
264
255
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#define VCLKEN 0x1010
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#define VCLKEN_CKEN BIT_U32(0)
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#define PHYSETUP 0x1014
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-
#define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16)
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-
#define PHYSETUP_HSFREQRANGE_MASK GENMASK(22, 16)
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-
#define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8)
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+
#define PHYSETUP_HSFREQRANGE_MASK GENMASK_U32(22, 16)
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+
#define PHYSETUP_HSFREQRANGE(n) FIELD_PREP(PHYSETUP_HSFREQRANGE_MASK, (n))
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+
#define PHYSETUP_CFGCLKFREQRANGE_MASK GENMASK_U32(13, 8)
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#define PHYSETUP_SHUTDOWNZ BIT_U32(1)
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#define PHYSETUP_RSTZ BIT_U32(0)
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#define CLOCKSET1 0x101c
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#define CLOCKSET1_LOCK_PHY BIT_U32(17)
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#define CLOCKSET1_CLKSEL BIT_U32(8)
278
-
#define CLOCKSET1_CLKINSEL_MASK GENMASK(3, 2)
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+
#define CLOCKSET1_CLKINSEL_MASK GENMASK_U32(3, 2)
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#define CLOCKSET1_CLKINSEL_EXTAL FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 0)
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#define CLOCKSET1_CLKINSEL_DIG FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 1)
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#define CLOCKSET1_CLKINSEL_DU FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 2)
···
286
271
#define CLOCKSET1_UPDATEPLL BIT_U32(0)
287
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#define CLOCKSET2 0x1020
289
-
#define CLOCKSET2_M(x) (((x) & 0xfff) << 16)
290
-
#define CLOCKSET2_VCO_CNTRL(x) (((x) & 0x3f) << 8)
291
-
#define CLOCKSET2_N(x) (((x) & 0xf) << 0)
274
+
#define CLOCKSET2_M_MASK GENMASK_U32(27, 16)
275
+
#define CLOCKSET2_M(n) FIELD_PREP(CLOCKSET2_M_MASK, (n))
276
+
#define CLOCKSET2_VCO_CNTRL_MASK GENMASK_U32(13, 8)
277
+
#define CLOCKSET2_VCO_CNTRL(n) FIELD_PREP(CLOCKSET2_VCO_CNTRL_MASK, (n))
278
+
#define CLOCKSET2_N_MASK GENMASK_U32(3, 0)
279
+
#define CLOCKSET2_N(n) FIELD_PREP(CLOCKSET2_N_MASK, (n))
292
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#define CLOCKSET3 0x1024
294
-
#define CLOCKSET3_PROP_CNTRL(x) (((x) & 0x3f) << 24)
295
-
#define CLOCKSET3_INT_CNTRL(x) (((x) & 0x3f) << 16)
296
-
#define CLOCKSET3_CPBIAS_CNTRL(x) (((x) & 0x7f) << 8)
297
-
#define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0)
282
+
#define CLOCKSET3_PROP_CNTRL_MASK GENMASK_U32(29, 24)
283
+
#define CLOCKSET3_PROP_CNTRL(n) FIELD_PREP(CLOCKSET3_PROP_CNTRL_MASK, (n))
284
+
#define CLOCKSET3_INT_CNTRL_MASK GENMASK_U32(21, 16)
285
+
#define CLOCKSET3_INT_CNTRL(n) FIELD_PREP(CLOCKSET3_INT_CNTRL_MASK, (n))
286
+
#define CLOCKSET3_CPBIAS_CNTRL_MASK GENMASK_U32(14, 8)
287
+
#define CLOCKSET3_CPBIAS_CNTRL(n) FIELD_PREP(CLOCKSET3_CPBIAS_CNTRL_MASK, (n))
288
+
#define CLOCKSET3_GMP_CNTRL_MASK GENMASK_U32(1, 0)
289
+
#define CLOCKSET3_GMP_CNTRL(n) FIELD_PREP(CLOCKSET3_GMP_CNTRL_MASK, (n))
298
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299
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#define PHTW 0x1034
300
292
#define PHTW_DWEN BIT_U32(24)
301
-
#define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16)
293
+
#define PHTW_TESTDIN_DATA_MASK GENMASK_U32(23, 16)
302
294
#define PHTW_CWEN BIT_U32(8)
303
-
#define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0)
295
+
#define PHTW_TESTDIN_CODE_MASK GENMASK_U32(7, 0)
304
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305
297
#define PHTR 0x1038
306
-
#define PHTR_TESTDOUT GENMASK(23, 16)
298
+
#define PHTR_TESTDOUT GENMASK_U32(23, 16)
307
299
#define PHTR_TESTDOUT_TEST BIT_U32(16)
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#define PHTC 0x103c