Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/rcar-du: dsi: Convert register bits to BIT() macro
Convert register bits to BIT() macro where applicable. This is done
automatically using regex 's@(1 << \([0-9]\+\))@BIT(\1)', except for
bitfields which are manually updated to use GENMASK().
Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/20251028232959.109936-11-marek.vasut+renesas@mailbox.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
authored by
Marek Vasut
and committed by
Tomi Valkeinen
6ade1742
94fe479f
+126
-126
+126
-126
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
+126
-126
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
···
9
9
#define __RCAR_MIPI_DSI_REGS_H__
10
10
11
11
#define LINKSR 0x010
12
-
#define LINKSR_LPBUSY (1 << 1)
13
-
#define LINKSR_HSBUSY (1 << 0)
12
+
#define LINKSR_LPBUSY BIT_U32(1)
13
+
#define LINKSR_HSBUSY BIT_U32(0)
14
14
15
15
#define TXSETR 0x100
16
-
#define TXSETR_LANECNT_MASK (0x3 << 0)
16
+
#define TXSETR_LANECNT_MASK GENMASK(1, 0)
17
17
18
18
/*
19
19
* DSI Command Transfer Registers
20
20
*/
21
21
#define TXCMSETR 0x110
22
-
#define TXCMSETR_SPDTYP (1 << 8) /* 0:HS 1:LP */
23
-
#define TXCMSETR_LPPDACC (1 << 0)
22
+
#define TXCMSETR_SPDTYP BIT_U32(8) /* 0:HS 1:LP */
23
+
#define TXCMSETR_LPPDACC BIT_U32(0)
24
24
#define TXCMCR 0x120
25
-
#define TXCMCR_BTATYP (1 << 2)
26
-
#define TXCMCR_BTAREQ (1 << 1)
27
-
#define TXCMCR_TXREQ (1 << 0)
25
+
#define TXCMCR_BTATYP BIT_U32(2)
26
+
#define TXCMCR_BTAREQ BIT_U32(1)
27
+
#define TXCMCR_TXREQ BIT_U32(0)
28
28
#define TXCMSR 0x130
29
-
#define TXCMSR_CLSNERR (1 << 18)
30
-
#define TXCMSR_AXIERR (1 << 16)
31
-
#define TXCMSR_TXREQEND (1 << 0)
29
+
#define TXCMSR_CLSNERR BIT_U32(18)
30
+
#define TXCMSR_AXIERR BIT_U32(16)
31
+
#define TXCMSR_TXREQEND BIT_U32(0)
32
32
#define TXCMSCR 0x134
33
-
#define TXCMSCR_CLSNERR (1 << 18)
34
-
#define TXCMSCR_AXIERR (1 << 16)
35
-
#define TXCMSCR_TXREQEND (1 << 0)
33
+
#define TXCMSCR_CLSNERR BIT_U32(18)
34
+
#define TXCMSCR_AXIERR BIT_U32(16)
35
+
#define TXCMSCR_TXREQEND BIT_U32(0)
36
36
#define TXCMIER 0x138
37
-
#define TXCMIER_CLSNERR (1 << 18)
38
-
#define TXCMIER_AXIERR (1 << 16)
39
-
#define TXCMIER_TXREQEND (1 << 0)
37
+
#define TXCMIER_CLSNERR BIT_U32(18)
38
+
#define TXCMIER_AXIERR BIT_U32(16)
39
+
#define TXCMIER_TXREQEND BIT_U32(0)
40
40
#define TXCMADDRSET0R 0x140
41
41
#define TXCMPHDR 0x150
42
-
#define TXCMPHDR_FMT (1 << 24) /* 0:SP 1:LP */
42
+
#define TXCMPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */
43
43
#define TXCMPHDR_VC(n) (((n) & 0x3) << 22)
44
44
#define TXCMPHDR_DT(n) (((n) & 0x3f) << 16)
45
45
#define TXCMPHDR_DATA1(n) (((n) & 0xff) << 8)
···
53
53
#define RXSETR_CRCEN(n) (((n) & 0xf) << 24)
54
54
#define RXSETR_ECCEN(n) (((n) & 0xf) << 16)
55
55
#define RXPSETR 0x210
56
-
#define RXPSETR_LPPDACC (1 << 0)
56
+
#define RXPSETR_LPPDACC BIT_U32(0)
57
57
#define RXPSR 0x220
58
-
#define RXPSR_ECCERR1B (1 << 28)
59
-
#define RXPSR_UEXTRGERR (1 << 25)
60
-
#define RXPSR_RESPTOERR (1 << 24)
61
-
#define RXPSR_OVRERR (1 << 23)
62
-
#define RXPSR_AXIERR (1 << 22)
63
-
#define RXPSR_CRCERR (1 << 21)
64
-
#define RXPSR_WCERR (1 << 20)
65
-
#define RXPSR_UEXDTERR (1 << 19)
66
-
#define RXPSR_UEXPKTERR (1 << 18)
67
-
#define RXPSR_ECCERR (1 << 17)
68
-
#define RXPSR_MLFERR (1 << 16)
69
-
#define RXPSR_RCVACK (1 << 14)
70
-
#define RXPSR_RCVEOT (1 << 10)
71
-
#define RXPSR_RCVAKE (1 << 9)
72
-
#define RXPSR_RCVRESP (1 << 8)
73
-
#define RXPSR_BTAREQEND (1 << 0)
58
+
#define RXPSR_ECCERR1B BIT_U32(28)
59
+
#define RXPSR_UEXTRGERR BIT_U32(25)
60
+
#define RXPSR_RESPTOERR BIT_U32(24)
61
+
#define RXPSR_OVRERR BIT_U32(23)
62
+
#define RXPSR_AXIERR BIT_U32(22)
63
+
#define RXPSR_CRCERR BIT_U32(21)
64
+
#define RXPSR_WCERR BIT_U32(20)
65
+
#define RXPSR_UEXDTERR BIT_U32(19)
66
+
#define RXPSR_UEXPKTERR BIT_U32(18)
67
+
#define RXPSR_ECCERR BIT_U32(17)
68
+
#define RXPSR_MLFERR BIT_U32(16)
69
+
#define RXPSR_RCVACK BIT_U32(14)
70
+
#define RXPSR_RCVEOT BIT_U32(10)
71
+
#define RXPSR_RCVAKE BIT_U32(9)
72
+
#define RXPSR_RCVRESP BIT_U32(8)
73
+
#define RXPSR_BTAREQEND BIT_U32(0)
74
74
#define RXPSCR 0x224
75
-
#define RXPSCR_ECCERR1B (1 << 28)
76
-
#define RXPSCR_UEXTRGERR (1 << 25)
77
-
#define RXPSCR_RESPTOERR (1 << 24)
78
-
#define RXPSCR_OVRERR (1 << 23)
79
-
#define RXPSCR_AXIERR (1 << 22)
80
-
#define RXPSCR_CRCERR (1 << 21)
81
-
#define RXPSCR_WCERR (1 << 20)
82
-
#define RXPSCR_UEXDTERR (1 << 19)
83
-
#define RXPSCR_UEXPKTERR (1 << 18)
84
-
#define RXPSCR_ECCERR (1 << 17)
85
-
#define RXPSCR_MLFERR (1 << 16)
86
-
#define RXPSCR_RCVACK (1 << 14)
87
-
#define RXPSCR_RCVEOT (1 << 10)
88
-
#define RXPSCR_RCVAKE (1 << 9)
89
-
#define RXPSCR_RCVRESP (1 << 8)
90
-
#define RXPSCR_BTAREQEND (1 << 0)
75
+
#define RXPSCR_ECCERR1B BIT_U32(28)
76
+
#define RXPSCR_UEXTRGERR BIT_U32(25)
77
+
#define RXPSCR_RESPTOERR BIT_U32(24)
78
+
#define RXPSCR_OVRERR BIT_U32(23)
79
+
#define RXPSCR_AXIERR BIT_U32(22)
80
+
#define RXPSCR_CRCERR BIT_U32(21)
81
+
#define RXPSCR_WCERR BIT_U32(20)
82
+
#define RXPSCR_UEXDTERR BIT_U32(19)
83
+
#define RXPSCR_UEXPKTERR BIT_U32(18)
84
+
#define RXPSCR_ECCERR BIT_U32(17)
85
+
#define RXPSCR_MLFERR BIT_U32(16)
86
+
#define RXPSCR_RCVACK BIT_U32(14)
87
+
#define RXPSCR_RCVEOT BIT_U32(10)
88
+
#define RXPSCR_RCVAKE BIT_U32(9)
89
+
#define RXPSCR_RCVRESP BIT_U32(8)
90
+
#define RXPSCR_BTAREQEND BIT_U32(0)
91
91
#define RXPIER 0x228
92
-
#define RXPIER_ECCERR1B (1 << 28)
93
-
#define RXPIER_UEXTRGERR (1 << 25)
94
-
#define RXPIER_RESPTOERR (1 << 24)
95
-
#define RXPIER_OVRERR (1 << 23)
96
-
#define RXPIER_AXIERR (1 << 22)
97
-
#define RXPIER_CRCERR (1 << 21)
98
-
#define RXPIER_WCERR (1 << 20)
99
-
#define RXPIER_UEXDTERR (1 << 19)
100
-
#define RXPIER_UEXPKTERR (1 << 18)
101
-
#define RXPIER_ECCERR (1 << 17)
102
-
#define RXPIER_MLFERR (1 << 16)
103
-
#define RXPIER_RCVACK (1 << 14)
104
-
#define RXPIER_RCVEOT (1 << 10)
105
-
#define RXPIER_RCVAKE (1 << 9)
106
-
#define RXPIER_RCVRESP (1 << 8)
107
-
#define RXPIER_BTAREQEND (1 << 0)
92
+
#define RXPIER_ECCERR1B BIT_U32(28)
93
+
#define RXPIER_UEXTRGERR BIT_U32(25)
94
+
#define RXPIER_RESPTOERR BIT_U32(24)
95
+
#define RXPIER_OVRERR BIT_U32(23)
96
+
#define RXPIER_AXIERR BIT_U32(22)
97
+
#define RXPIER_CRCERR BIT_U32(21)
98
+
#define RXPIER_WCERR BIT_U32(20)
99
+
#define RXPIER_UEXDTERR BIT_U32(19)
100
+
#define RXPIER_UEXPKTERR BIT_U32(18)
101
+
#define RXPIER_ECCERR BIT_U32(17)
102
+
#define RXPIER_MLFERR BIT_U32(16)
103
+
#define RXPIER_RCVACK BIT_U32(14)
104
+
#define RXPIER_RCVEOT BIT_U32(10)
105
+
#define RXPIER_RCVAKE BIT_U32(9)
106
+
#define RXPIER_RCVRESP BIT_U32(8)
107
+
#define RXPIER_BTAREQEND BIT_U32(0)
108
108
#define RXPADDRSET0R 0x230
109
109
#define RXPSIZESETR 0x238
110
110
#define RXPSIZESETR_SIZE(n) (((n) & 0xf) << 3)
111
111
#define RXPHDR 0x240
112
-
#define RXPHDR_FMT (1 << 24) /* 0:SP 1:LP */
112
+
#define RXPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */
113
113
#define RXPHDR_VC(n) (((n) & 0x3) << 22)
114
114
#define RXPHDR_DT(n) (((n) & 0x3f) << 16)
115
115
#define RXPHDR_DATA1(n) (((n) & 0xff) << 8)
···
128
128
#define TASCR 0x514
129
129
#define TAIER 0x518
130
130
#define TOSR 0x610
131
-
#define TOSR_TATO (1 << 2)
132
-
#define TOSR_LRXHTO (1 << 1)
133
-
#define TOSR_HRXTO (1 << 0)
131
+
#define TOSR_TATO BIT_U32(2)
132
+
#define TOSR_LRXHTO BIT_U32(1)
133
+
#define TOSR_HRXTO BIT_U32(0)
134
134
#define TOSCR 0x614
135
-
#define TOSCR_TATO (1 << 2)
136
-
#define TOSCR_LRXHTO (1 << 1)
137
-
#define TOSCR_HRXTO (1 << 0)
135
+
#define TOSCR_TATO BIT_U32(2)
136
+
#define TOSCR_LRXHTO BIT_U32(1)
137
+
#define TOSCR_HRXTO BIT_U32(0)
138
138
139
139
/*
140
140
* Video Mode Register
141
141
*/
142
142
#define TXVMSETR 0x180
143
-
#define TXVMSETR_SYNSEQ_EVENTS (1 << 16) /* 0:Pulses 1:Events */
144
-
#define TXVMSETR_VSTPM (1 << 15)
145
-
#define TXVMSETR_PIXWDTH_MASK (7 << 8)
146
-
#define TXVMSETR_PIXWDTH (1 << 8) /* Only allowed value */
147
-
#define TXVMSETR_VSEN (1 << 4)
148
-
#define TXVMSETR_HFPBPEN (1 << 2)
149
-
#define TXVMSETR_HBPBPEN (1 << 1)
150
-
#define TXVMSETR_HSABPEN (1 << 0)
143
+
#define TXVMSETR_SYNSEQ_EVENTS BIT_U32(16) /* 0:Pulses 1:Events */
144
+
#define TXVMSETR_VSTPM BIT_U32(15)
145
+
#define TXVMSETR_PIXWDTH_MASK GENMASK(10, 8)
146
+
#define TXVMSETR_PIXWDTH BIT_U32(8) /* Only allowed value */
147
+
#define TXVMSETR_VSEN BIT_U32(4)
148
+
#define TXVMSETR_HFPBPEN BIT_U32(2)
149
+
#define TXVMSETR_HBPBPEN BIT_U32(1)
150
+
#define TXVMSETR_HSABPEN BIT_U32(0)
151
151
152
152
#define TXVMCR 0x190
153
-
#define TXVMCR_VFCLR (1 << 12)
154
-
#define TXVMCR_EN_VIDEO (1 << 0)
153
+
#define TXVMCR_VFCLR BIT_U32(12)
154
+
#define TXVMCR_EN_VIDEO BIT_U32(0)
155
155
156
156
#define TXVMSR 0x1a0
157
-
#define TXVMSR_STR (1 << 16)
158
-
#define TXVMSR_VFRDY (1 << 12)
159
-
#define TXVMSR_ACT (1 << 8)
160
-
#define TXVMSR_RDY (1 << 0)
157
+
#define TXVMSR_STR BIT_U32(16)
158
+
#define TXVMSR_VFRDY BIT_U32(12)
159
+
#define TXVMSR_ACT BIT_U32(8)
160
+
#define TXVMSR_RDY BIT_U32(0)
161
161
162
162
#define TXVMSCR 0x1a4
163
-
#define TXVMSCR_STR (1 << 16)
163
+
#define TXVMSCR_STR BIT_U32(16)
164
164
165
165
#define TXVMPSPHSETR 0x1c0
166
166
#define TXVMPSPHSETR_DT_MASK (0x3f << 16)
···
171
171
#define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c)
172
172
173
173
#define TXVMVPRMSET0R 0x1d0
174
-
#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) /* 0:High 1:Low */
175
-
#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) /* 0:High 1:Low */
176
-
#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) /* 0:RGB 1:YCbCr */
177
-
#define TXVMVPRMSET0R_BPP_MASK (7 << 0)
174
+
#define TXVMVPRMSET0R_HSPOL_LOW BIT_U32(17) /* 0:High 1:Low */
175
+
#define TXVMVPRMSET0R_VSPOL_LOW BIT_U32(16) /* 0:High 1:Low */
176
+
#define TXVMVPRMSET0R_CSPC_YCbCr BIT_U32(4) /* 0:RGB 1:YCbCr */
177
+
#define TXVMVPRMSET0R_BPP_MASK GENMASK(2, 0)
178
178
#define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0)
179
179
#define TXVMVPRMSET0R_BPP_18 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1)
180
180
#define TXVMVPRMSET0R_BPP_24 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2)
···
199
199
* PHY-Protocol Interface (PPI) Registers
200
200
*/
201
201
#define PPISETR 0x700
202
-
#define PPISETR_DLEN_MASK (0xf << 0)
203
-
#define PPISETR_CLEN (1 << 8)
202
+
#define PPISETR_DLEN_MASK GENMASK(3, 0)
203
+
#define PPISETR_CLEN BIT_U32(8)
204
204
205
205
#define PPICLCR 0x710
206
-
#define PPICLCR_TXREQHS (1 << 8)
207
-
#define PPICLCR_TXULPSEXT (1 << 1)
208
-
#define PPICLCR_TXULPSCLK (1 << 0)
206
+
#define PPICLCR_TXREQHS BIT_U32(8)
207
+
#define PPICLCR_TXULPSEXT BIT_U32(1)
208
+
#define PPICLCR_TXULPSCLK BIT_U32(0)
209
209
210
210
#define PPICLSR 0x720
211
-
#define PPICLSR_HSTOLP (1 << 27)
212
-
#define PPICLSR_TOHS (1 << 26)
213
-
#define PPICLSR_STPST (1 << 0)
211
+
#define PPICLSR_HSTOLP BIT_U32(27)
212
+
#define PPICLSR_TOHS BIT_U32(26)
213
+
#define PPICLSR_STPST BIT_U32(0)
214
214
215
215
#define PPICLSCR 0x724
216
-
#define PPICLSCR_HSTOLP (1 << 27)
217
-
#define PPICLSCR_TOHS (1 << 26)
216
+
#define PPICLSCR_HSTOLP BIT_U32(27)
217
+
#define PPICLSCR_TOHS BIT_U32(26)
218
218
219
219
#define PPIDL0SR 0x740
220
-
#define PPIDL0SR_DIR (1 << 10)
221
-
#define PPIDL0SR_STPST (1 << 6)
220
+
#define PPIDL0SR_DIR BIT_U32(10)
221
+
#define PPIDL0SR_STPST BIT_U32(6)
222
222
223
223
#define PPIDLSR 0x760
224
-
#define PPIDLSR_STPST (0xf << 0)
224
+
#define PPIDLSR_STPST GENMASK(3, 0)
225
225
226
226
/*
227
227
* Clocks registers
228
228
*/
229
229
#define LPCLKSET 0x1000
230
-
#define LPCLKSET_CKEN (1 << 8)
230
+
#define LPCLKSET_CKEN BIT_U32(8)
231
231
#define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0)
232
232
233
233
#define CFGCLKSET 0x1004
234
-
#define CFGCLKSET_CKEN (1 << 8)
234
+
#define CFGCLKSET_CKEN BIT_U32(8)
235
235
#define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0)
236
236
237
237
#define DOTCLKDIV 0x1008
238
-
#define DOTCLKDIV_CKEN (1 << 8)
238
+
#define DOTCLKDIV_CKEN BIT_U32(8)
239
239
#define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0)
240
240
241
241
#define VCLKSET 0x100c
242
-
#define VCLKSET_CKEN (1 << 16)
243
-
#define VCLKSET_COLOR_YCC (1 << 8) /* 0:RGB 1:YCbCr */
242
+
#define VCLKSET_CKEN BIT_U32(16)
243
+
#define VCLKSET_COLOR_YCC BIT_U32(8) /* 0:RGB 1:YCbCr */
244
244
#define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4)
245
245
#define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4)
246
-
#define VCLKSET_BPP_MASK (3 << 2)
246
+
#define VCLKSET_BPP_MASK GENMASK(3, 2)
247
247
#define VCLKSET_BPP_16 FIELD_PREP(VCLKSET_BPP_MASK, 0)
248
248
#define VCLKSET_BPP_18 FIELD_PREP(VCLKSET_BPP_MASK, 1)
249
249
#define VCLKSET_BPP_18L FIELD_PREP(VCLKSET_BPP_MASK, 2)
···
251
251
#define VCLKSET_LANE(x) (((x) & 0x3) << 0)
252
252
253
253
#define VCLKEN 0x1010
254
-
#define VCLKEN_CKEN (1 << 0)
254
+
#define VCLKEN_CKEN BIT_U32(0)
255
255
256
256
#define PHYSETUP 0x1014
257
257
#define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16)
258
-
#define PHYSETUP_HSFREQRANGE_MASK (0x7f << 16)
258
+
#define PHYSETUP_HSFREQRANGE_MASK GENMASK(22, 16)
259
259
#define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8)
260
-
#define PHYSETUP_SHUTDOWNZ (1 << 1)
261
-
#define PHYSETUP_RSTZ (1 << 0)
260
+
#define PHYSETUP_SHUTDOWNZ BIT_U32(1)
261
+
#define PHYSETUP_RSTZ BIT_U32(0)
262
262
263
263
#define CLOCKSET1 0x101c
264
-
#define CLOCKSET1_LOCK_PHY (1 << 17)
265
-
#define CLOCKSET1_CLKSEL (1 << 8)
266
-
#define CLOCKSET1_CLKINSEL_MASK (3 << 2)
264
+
#define CLOCKSET1_LOCK_PHY BIT_U32(17)
265
+
#define CLOCKSET1_CLKSEL BIT_U32(8)
266
+
#define CLOCKSET1_CLKINSEL_MASK GENMASK(3, 2)
267
267
#define CLOCKSET1_CLKINSEL_EXTAL FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 0)
268
268
#define CLOCKSET1_CLKINSEL_DIG FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 1)
269
269
#define CLOCKSET1_CLKINSEL_DU FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 2)
270
-
#define CLOCKSET1_SHADOW_CLEAR (1 << 1)
271
-
#define CLOCKSET1_UPDATEPLL (1 << 0)
270
+
#define CLOCKSET1_SHADOW_CLEAR BIT_U32(1)
271
+
#define CLOCKSET1_UPDATEPLL BIT_U32(0)
272
272
273
273
#define CLOCKSET2 0x1020
274
274
#define CLOCKSET2_M(x) (((x) & 0xfff) << 16)
···
282
282
#define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0)
283
283
284
284
#define PHTW 0x1034
285
-
#define PHTW_DWEN (1 << 24)
285
+
#define PHTW_DWEN BIT_U32(24)
286
286
#define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16)
287
-
#define PHTW_CWEN (1 << 8)
287
+
#define PHTW_CWEN BIT_U32(8)
288
288
#define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0)
289
289
290
290
#define PHTR 0x1038
291
-
#define PHTR_TESTDOUT (0xff << 16)
292
-
#define PHTR_TESTDOUT_TEST (1 << 16)
291
+
#define PHTR_TESTDOUT GENMASK(23, 16)
292
+
#define PHTR_TESTDOUT_TEST BIT_U32(16)
293
293
294
294
#define PHTC 0x103c
295
-
#define PHTC_TESTCLR (1 << 0)
295
+
#define PHTC_TESTCLR BIT_U32(0)
296
296
297
297
#endif /* __RCAR_MIPI_DSI_REGS_H__ */