Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/xe/pat: Use table-based programming of PAT settings
Provide per-platform tables of PAT values rather than per-platform
functions. This will simplify the handling of unicast vs MCR registers
in the upcoming patches.
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-3-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
authored by
Matt Roper
and committed by
Rodrigo Vivi
4f843703
576c6380
+35
-42
+35
-42
drivers/gpu/drm/xe/xe_pat.c
+35
-42
drivers/gpu/drm/xe/xe_pat.c
···
17
17
#define GEN8_PPAT_UC (0<<0)
18
18
#define GEN12_PPAT_CLOS(x) ((x)<<2)
19
19
20
-
static void tgl_setup_private_ppat(struct xe_gt *gt)
21
-
{
22
-
/* TGL doesn't support LLC or AGE settings */
23
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_WB);
24
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
25
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
26
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_UC);
27
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg, GEN8_PPAT_WB);
28
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg, GEN8_PPAT_WB);
29
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg, GEN8_PPAT_WB);
30
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg, GEN8_PPAT_WB);
31
-
}
20
+
const u32 tgl_pat_table[] = {
21
+
[0] = GEN8_PPAT_WB,
22
+
[1] = GEN8_PPAT_WC,
23
+
[2] = GEN8_PPAT_WT,
24
+
[3] = GEN8_PPAT_UC,
25
+
[4] = GEN8_PPAT_WB,
26
+
[5] = GEN8_PPAT_WB,
27
+
[6] = GEN8_PPAT_WB,
28
+
[7] = GEN8_PPAT_WB,
29
+
};
32
30
33
-
static void pvc_setup_private_ppat(struct xe_gt *gt)
34
-
{
35
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_UC);
36
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
37
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
38
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_WB);
39
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
40
-
GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT);
41
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg,
42
-
GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB);
43
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg,
44
-
GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT);
45
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg,
46
-
GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB);
47
-
}
31
+
const u32 pvc_pat_table[] = {
32
+
[0] = GEN8_PPAT_UC,
33
+
[1] = GEN8_PPAT_WC,
34
+
[2] = GEN8_PPAT_WT,
35
+
[3] = GEN8_PPAT_WB,
36
+
[4] = GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT,
37
+
[5] = GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB,
38
+
[6] = GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT,
39
+
[7] = GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB,
40
+
};
48
41
49
42
#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
50
43
#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
···
48
55
#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
49
56
#define MTL_0_COH_NON REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 0)
50
57
51
-
static void mtl_setup_private_ppat(struct xe_gt *gt)
52
-
{
53
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, MTL_PPAT_0_WB);
54
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg,
55
-
MTL_PPAT_1_WT | MTL_2_COH_1W);
56
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg,
57
-
MTL_PPAT_3_UC | MTL_2_COH_1W);
58
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg,
59
-
MTL_PPAT_0_WB | MTL_2_COH_1W);
60
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
61
-
MTL_PPAT_0_WB | MTL_3_COH_2W);
62
-
}
58
+
const u32 mtl_pat_table[] = {
59
+
[0] = MTL_PPAT_0_WB,
60
+
[1] = MTL_PPAT_1_WT | MTL_2_COH_1W,
61
+
[2] = MTL_PPAT_3_UC | MTL_2_COH_1W,
62
+
[3] = MTL_PPAT_0_WB | MTL_2_COH_1W,
63
+
[4] = MTL_PPAT_0_WB | MTL_3_COH_2W,
64
+
};
65
+
66
+
#define PROGRAM_PAT_UNICAST(gt, table) do { \
67
+
for (int i = 0; i < ARRAY_SIZE(table); i++) \
68
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(i).reg, table[i]); \
69
+
} while (0)
63
70
64
71
void xe_pat_init(struct xe_gt *gt)
65
72
{
66
73
struct xe_device *xe = gt_to_xe(gt);
67
74
68
75
if (xe->info.platform == XE_METEORLAKE)
69
-
mtl_setup_private_ppat(gt);
76
+
PROGRAM_PAT_UNICAST(gt, mtl_pat_table);
70
77
else if (xe->info.platform == XE_PVC)
71
-
pvc_setup_private_ppat(gt);
78
+
PROGRAM_PAT_UNICAST(gt, pvc_pat_table);
72
79
else
73
-
tgl_setup_private_ppat(gt);
80
+
PROGRAM_PAT_UNICAST(gt, tgl_pat_table);
74
81
}