Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Use posamble to reset counters on preemption
Use the postamble to reset perf counters when switching between rings,
except when sysprof is enabled, analogously to how they are reset
between submissions when switching pagetables.
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK
Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/618024/
Signed-off-by: Rob Clark <robdclark@chromium.org>
authored by
Antonino Maniscalco
and committed by
Rob Clark
50117cad
3044f928
+81
-2
+12
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+12
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
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static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring,
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struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue)
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{
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+
u64 preempt_postamble;
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+
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OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12);
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OUT_RING(ring, SMMU_INFO);
···
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/* seems OK to set to 0 to disable it */
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OUT_RING(ring, 0);
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OUT_RING(ring, 0);
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+
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/* Emit postamble to clear perfcounters */
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preempt_postamble = a6xx_gpu->preempt_postamble_iova;
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+
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+
OUT_PKT7(ring, CP_SET_AMBLE, 3);
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OUT_RING(ring, lower_32_bits(preempt_postamble));
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OUT_RING(ring, upper_32_bits(preempt_postamble));
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OUT_RING(ring, CP_SET_AMBLE_2_DWORDS(
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a6xx_gpu->preempt_postamble_len) |
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CP_SET_AMBLE_2_TYPE(KMD_AMBLE_TYPE));
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}
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static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
+6
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+6
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
···
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bool uses_gmem;
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bool skip_save_restore;
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+
struct drm_gem_object *preempt_postamble_bo;
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+
void *preempt_postamble_ptr;
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+
uint64_t preempt_postamble_iova;
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uint64_t preempt_postamble_len;
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bool postamble_enabled;
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+
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struct a6xx_gmu gmu;
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struct drm_gem_object *shadow_bo;
+58
drivers/gpu/drm/msm/adreno/a6xx_preempt.c
+58
drivers/gpu/drm/msm/adreno/a6xx_preempt.c
···
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kthread_queue_work(gpu->worker, &gpu->recover_work);
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}
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+
static void preempt_prepare_postamble(struct a6xx_gpu *a6xx_gpu)
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{
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+
u32 *postamble = a6xx_gpu->preempt_postamble_ptr;
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u32 count = 0;
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+
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postamble[count++] = PKT7(CP_REG_RMW, 3);
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postamble[count++] = REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD;
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postamble[count++] = 0;
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postamble[count++] = 1;
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+
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postamble[count++] = PKT7(CP_WAIT_REG_MEM, 6);
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postamble[count++] = CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ);
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postamble[count++] = CP_WAIT_REG_MEM_1_POLL_ADDR_LO(
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REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS);
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postamble[count++] = CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0);
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+
postamble[count++] = CP_WAIT_REG_MEM_3_REF(0x1);
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postamble[count++] = CP_WAIT_REG_MEM_4_MASK(0x1);
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postamble[count++] = CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0);
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+
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a6xx_gpu->preempt_postamble_len = count;
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+
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a6xx_gpu->postamble_enabled = true;
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}
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+
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static void preempt_disable_postamble(struct a6xx_gpu *a6xx_gpu)
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{
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u32 *postamble = a6xx_gpu->preempt_postamble_ptr;
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+
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/*
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* Disable the postamble by replacing the first packet header with a NOP
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* that covers the whole buffer.
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*/
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*postamble = PKT7(CP_NOP, (a6xx_gpu->preempt_postamble_len - 1));
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a6xx_gpu->postamble_enabled = false;
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}
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+
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void a6xx_preempt_irq(struct msm_gpu *gpu)
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{
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uint32_t status;
···
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unsigned long flags;
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struct msm_ringbuffer *ring;
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unsigned int cntl;
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bool sysprof;
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if (gpu->nr_rings == 1)
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return;
···
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/* Start a timer to catch a stuck preemption */
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mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000));
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+
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/* Enable or disable postamble as needed */
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sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;
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+
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if (!sysprof && !a6xx_gpu->postamble_enabled)
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preempt_prepare_postamble(a6xx_gpu);
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+
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if (sysprof && a6xx_gpu->postamble_enabled)
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preempt_disable_postamble(a6xx_gpu);
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/* Set the preemption state to triggered */
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set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED);
···
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a6xx_gpu->preempt_level = 1;
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a6xx_gpu->uses_gmem = 1;
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a6xx_gpu->skip_save_restore = 1;
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+
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a6xx_gpu->preempt_postamble_ptr = msm_gem_kernel_new(gpu->dev,
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PAGE_SIZE,
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MSM_BO_WC | MSM_BO_MAP_PRIV | MSM_BO_GPU_READONLY,
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gpu->aspace, &a6xx_gpu->preempt_postamble_bo,
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&a6xx_gpu->preempt_postamble_iova);
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+
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preempt_prepare_postamble(a6xx_gpu);
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+
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if (IS_ERR(a6xx_gpu->preempt_postamble_ptr))
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goto fail;
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timer_setup(&a6xx_gpu->preempt_timer, a6xx_preempt_timer, 0);
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+5
-2
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+5
-2
drivers/gpu/drm/msm/adreno/adreno_gpu.h
···
670
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OUT_RING(ring, PKT4(regindx, cnt));
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}
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+
#define PKT7(opcode, cnt) \
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(CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | \
675
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((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23))
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+
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static inline void
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OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
675
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{
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adreno_wait_ring(ring, cnt + 1);
677
-
OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
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-
((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
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OUT_RING(ring, PKT7(opcode, cnt));
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}
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struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);