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phy: qcom-qmp-usb: move PCS v6 register to the proper header
The commit 39bbf82d8c2b ("phy: qcom-qmp: pcs-usb: Add v6 register
offsets") incorrectly added plain PCS registers to the PCS_USB header.
Move them to a proper location.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
5077b136
579483ec
+14
-18
-16
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
-16
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
···
7
7
#define QCOM_PHY_QMP_PCS_USB_V6_H_
8
8
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9
/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
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-
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1 0xc4
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-
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2 0xc8
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-
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0xcc
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-
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0xd8
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-
#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
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-
#define QPHY_V6_PCS_POWER_STATE_CONFIG1 0x90
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-
#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188
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-
#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
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-
#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
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-
#define QPHY_V6_PCS_CDR_RESET_TIME 0x1b0
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-
#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0
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-
#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4
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-
#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
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-
#define QPHY_V6_PCS_EQ_CONFIG1 0x1dc
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-
#define QPHY_V6_PCS_EQ_CONFIG5 0x1ec
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-
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10
#define QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1 0x00
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11
#define QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
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12
#define QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
+14
-2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
+14
-2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
···
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#define QCOM_PHY_QMP_PCS_V6_H_
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/* Only for QMP V6 PHY - USB/PCIe PCS registers */
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-
#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
10
+
#define QPHY_V6_PCS_POWER_STATE_CONFIG1 0x090
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+
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1 0x0c4
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+
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2 0x0c8
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+
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0x0cc
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+
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0x0d8
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+
#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0x0dc
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#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188
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+
#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
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+
#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
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19
#define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198
13
-
#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0
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+
#define QPHY_V6_PCS_CDR_RESET_TIME 0x1b0
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+
#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0
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+
#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4
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#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
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+
#define QPHY_V6_PCS_EQ_CONFIG1 0x1dc
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+
#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0
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+
#define QPHY_V6_PCS_EQ_CONFIG5 0x1ec
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#endif