tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'ras_core_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull RAS updates from Borislav Petkov:

- Add new AMD MCA bank names and types to the MCA code, preceded by a
clean up of the relevant places to have them more developer-friendly
(read: sort them alphanumerically and clean up comments) such that
adding new banks is easy

* tag 'ras_core_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/mce, EDAC/mce_amd: Add new SMCA bank types
x86/mce, EDAC/mce_amd: Update CS bank type naming
x86/mce, EDAC/mce_amd: Reorder SMCA bank type enums

Linus Torvalds 508fed67 1834703b

+138 -110
+39 -23
arch/x86/include/asm/mce.h
··· 343 343 */ 344 344 #ifdef CONFIG_X86_MCE_AMD 345 345 346 - /* These may be used by multiple smca_hwid_mcatypes */ 346 + /* 347 + * These may be used by multiple smca_hwid_mcatypes. 348 + * 349 + * Keep in alphanumeric order, numerals before letters. 350 + * Exception: Keep "V2, etc." with their originals. 351 + */ 347 352 enum smca_bank_types { 348 - SMCA_LS = 0, /* Load Store */ 349 - SMCA_LS_V2, 350 - SMCA_IF, /* Instruction Fetch */ 351 - SMCA_L2_CACHE, /* L2 Cache */ 353 + SMCA_CS, /* Coherent Station */ 354 + SMCA_CS_V2, 355 + SMCA_DACC_BE, /* Data Acceleration Back-end */ 356 + SMCA_DACC_FE, /* Data Acceleration Front-end */ 352 357 SMCA_DE, /* Decoder Unit */ 353 - SMCA_RESERVED, /* Reserved */ 358 + SMCA_EDDR5CMN, /* eDDR5 CMN */ 354 359 SMCA_EX, /* Execution Unit */ 355 360 SMCA_FP, /* Floating Point */ 361 + SMCA_GMI_PCS, /* GMI PCS Unit */ 362 + SMCA_GMI_PHY, /* GMI PHY Unit */ 363 + SMCA_IF, /* Instruction Fetch */ 364 + SMCA_L2_CACHE, /* L2 Cache */ 356 365 SMCA_L3_CACHE, /* L3 Cache */ 357 - SMCA_CS, /* Coherent Slave */ 358 - SMCA_CS_V2, 359 - SMCA_PIE, /* Power, Interrupts, etc. */ 360 - SMCA_UMC, /* Unified Memory Controller */ 361 - SMCA_UMC_V2, 366 + SMCA_LS, /* Load Store */ 367 + SMCA_LS_V2, 362 368 SMCA_MA_LLC, /* Memory Attached Last Level Cache */ 363 - SMCA_PB, /* Parameter Block */ 364 - SMCA_PSP, /* Platform Security Processor */ 365 - SMCA_PSP_V2, 366 - SMCA_SMU, /* System Management Unit */ 367 - SMCA_SMU_V2, 368 369 SMCA_MP5, /* Microprocessor 5 Unit */ 370 + SMCA_MPART, /* AMD Root of Trust Microprocessor */ 371 + SMCA_MPASP, /* AMD Secure Processor */ 372 + SMCA_MPASP_V2, 373 + SMCA_MPDACC, /* MP for Data Acceleration */ 369 374 SMCA_MPDMA, /* MPDMA Unit */ 375 + SMCA_MPM, /* Microprocessor Manageability Core */ 376 + SMCA_MPRAS, /* MP for RAS */ 377 + SMCA_NBIF, /* NBIF Unit */ 370 378 SMCA_NBIO, /* Northbridge IO Unit */ 379 + SMCA_PB, /* Parameter Block */ 371 380 SMCA_PCIE, /* PCI Express Unit */ 372 381 SMCA_PCIE_V2, 373 - SMCA_XGMI_PCS, /* xGMI PCS Unit */ 374 - SMCA_NBIF, /* NBIF Unit */ 375 - SMCA_SHUB, /* System HUB Unit */ 382 + SMCA_PCIE_PL, /* PCIe Link */ 383 + SMCA_PIE, /* Power, Interrupts, etc. */ 384 + SMCA_PSP, /* Platform Security Processor */ 385 + SMCA_PSP_V2, 386 + SMCA_RESERVED, /* Reserved */ 376 387 SMCA_SATA, /* SATA Unit */ 388 + SMCA_SHUB, /* System HUB Unit */ 389 + SMCA_SMU, /* System Management Unit */ 390 + SMCA_SMU_V2, 391 + SMCA_SSBDCI, /* Die to Die Interconnect */ 392 + SMCA_UMC, /* Unified Memory Controller */ 393 + SMCA_UMC_V2, 377 394 SMCA_USB, /* USB Unit */ 378 - SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */ 379 395 SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */ 380 - SMCA_GMI_PCS, /* GMI PCS Unit */ 381 - SMCA_XGMI_PHY, /* xGMI PHY Unit */ 396 + SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */ 382 397 SMCA_WAFL_PHY, /* WAFL PHY Unit */ 383 - SMCA_GMI_PHY, /* GMI PHY Unit */ 398 + SMCA_XGMI_PCS, /* xGMI PCS Unit */ 399 + SMCA_XGMI_PHY, /* xGMI PHY Unit */ 384 400 N_SMCA_BANK_TYPES 385 401 }; 386 402
+70 -68
arch/x86/kernel/cpu/mce/amd.c
··· 95 95 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); 96 96 97 97 static const char * const smca_names[] = { 98 - [SMCA_LS ... SMCA_LS_V2] = "load_store", 99 - [SMCA_IF] = "insn_fetch", 100 - [SMCA_L2_CACHE] = "l2_cache", 98 + [SMCA_CS ... SMCA_CS_V2] = "coherent_station", 99 + [SMCA_DACC_BE] = "dacc_be", 100 + [SMCA_DACC_FE] = "dacc_fe", 101 101 [SMCA_DE] = "decode_unit", 102 - [SMCA_RESERVED] = "reserved", 102 + [SMCA_EDDR5CMN] = "eddr5_cmn", 103 103 [SMCA_EX] = "execution_unit", 104 104 [SMCA_FP] = "floating_point", 105 + [SMCA_GMI_PCS] = "gmi_pcs", 106 + [SMCA_GMI_PHY] = "gmi_phy", 107 + [SMCA_IF] = "insn_fetch", 108 + [SMCA_L2_CACHE] = "l2_cache", 105 109 [SMCA_L3_CACHE] = "l3_cache", 106 - [SMCA_CS ... SMCA_CS_V2] = "coherent_slave", 110 + [SMCA_LS ... SMCA_LS_V2] = "load_store", 111 + [SMCA_MA_LLC] = "ma_llc", 112 + [SMCA_MP5] = "mp5", 113 + [SMCA_MPART] = "mpart", 114 + [SMCA_MPASP ... SMCA_MPASP_V2] = "mpasp", 115 + [SMCA_MPDACC] = "mpdacc", 116 + [SMCA_MPDMA] = "mpdma", 117 + [SMCA_MPM] = "mpm", 118 + [SMCA_MPRAS] = "mpras", 119 + [SMCA_NBIF] = "nbif", 120 + [SMCA_NBIO] = "nbio", 121 + [SMCA_PB] = "param_block", 122 + [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie", 123 + [SMCA_PCIE_PL] = "pcie_pl", 107 124 [SMCA_PIE] = "pie", 125 + [SMCA_PSP ... SMCA_PSP_V2] = "psp", 126 + [SMCA_RESERVED] = "reserved", 127 + [SMCA_SATA] = "sata", 128 + [SMCA_SHUB] = "shub", 129 + [SMCA_SMU ... SMCA_SMU_V2] = "smu", 130 + [SMCA_SSBDCI] = "ssbdci", 108 131 109 132 /* UMC v2 is separate because both of them can exist in a single system. */ 110 133 [SMCA_UMC] = "umc", 111 134 [SMCA_UMC_V2] = "umc_v2", 112 - [SMCA_MA_LLC] = "ma_llc", 113 - [SMCA_PB] = "param_block", 114 - [SMCA_PSP ... SMCA_PSP_V2] = "psp", 115 - [SMCA_SMU ... SMCA_SMU_V2] = "smu", 116 - [SMCA_MP5] = "mp5", 117 - [SMCA_MPDMA] = "mpdma", 118 - [SMCA_NBIO] = "nbio", 119 - [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie", 120 - [SMCA_XGMI_PCS] = "xgmi_pcs", 121 - [SMCA_NBIF] = "nbif", 122 - [SMCA_SHUB] = "shub", 123 - [SMCA_SATA] = "sata", 124 135 [SMCA_USB] = "usb", 125 - [SMCA_USR_DP] = "usr_dp", 126 136 [SMCA_USR_CP] = "usr_cp", 127 - [SMCA_GMI_PCS] = "gmi_pcs", 128 - [SMCA_XGMI_PHY] = "xgmi_phy", 137 + [SMCA_USR_DP] = "usr_dp", 129 138 [SMCA_WAFL_PHY] = "wafl_phy", 130 - [SMCA_GMI_PHY] = "gmi_phy", 139 + [SMCA_XGMI_PCS] = "xgmi_pcs", 140 + [SMCA_XGMI_PHY] = "xgmi_phy", 131 141 }; 132 142 133 143 static const char *smca_get_name(enum smca_bank_types t) ··· 163 153 } 164 154 EXPORT_SYMBOL_GPL(smca_get_bank_type); 165 155 156 + /* 157 + * Format: 158 + * { bank_type, hwid_mcatype } 159 + * 160 + * alphanumerically sorted by bank type. 161 + */ 166 162 static const struct smca_hwid smca_hwid_mcatypes[] = { 167 - /* { bank_type, hwid_mcatype } */ 168 - 169 - /* Reserved type */ 170 - { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 171 - 172 - /* ZN Core (HWID=0xB0) MCA types */ 173 - { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 174 - { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 175 - { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 176 - { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 163 + { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 164 + { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 165 + { SMCA_DACC_BE, HWID_MCATYPE(0x164, 0x0) }, 166 + { SMCA_DACC_FE, HWID_MCATYPE(0x157, 0x0) }, 177 167 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 178 - /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 168 + { SMCA_EDDR5CMN, HWID_MCATYPE(0x1E0, 0x0) }, 179 169 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 180 170 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 171 + { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, 172 + { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, 173 + { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 174 + { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 181 175 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 182 - 183 - /* Data Fabric MCA types */ 184 - { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 185 - { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 186 - { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 176 + { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 177 + { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 187 178 { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, 188 - 189 - /* Unified Memory Controller MCA type */ 190 - { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 191 - { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 192 - 193 - /* Parameter Block MCA type */ 194 - { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 195 - 196 - /* Platform Security Processor MCA type */ 197 - { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 198 - { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 199 - 200 - /* System Management Unit MCA type */ 201 - { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 202 - { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 203 - 204 - /* Microprocessor 5 Unit MCA type */ 205 179 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 206 - 207 - /* MPDMA MCA type */ 180 + { SMCA_MPART, HWID_MCATYPE(0xFF, 0x2) }, 181 + { SMCA_MPASP, HWID_MCATYPE(0xFD, 0x0) }, 182 + { SMCA_MPASP_V2, HWID_MCATYPE(0xFD, 0x1) }, 183 + { SMCA_MPDACC, HWID_MCATYPE(0xBE, 0x0) }, 208 184 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, 209 - 210 - /* Northbridge IO Unit MCA type */ 185 + { SMCA_MPM, HWID_MCATYPE(0xF9, 0x0) }, 186 + { SMCA_MPRAS, HWID_MCATYPE(0x12, 0x0) }, 187 + { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, 211 188 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 212 - 213 - /* PCI Express Unit MCA type */ 189 + { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 214 190 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 215 191 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 216 - 217 - { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 218 - { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, 219 - { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, 192 + { SMCA_PCIE_PL, HWID_MCATYPE(0x1E1, 0x0) }, 193 + { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 194 + { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 195 + { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 196 + { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 220 197 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, 198 + { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, 199 + { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 200 + { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 201 + { SMCA_SSBDCI, HWID_MCATYPE(0x5C, 0x0) }, 202 + { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 203 + { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 221 204 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, 222 - { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, 223 205 { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) }, 224 - { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, 225 - { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 206 + { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, 226 207 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 227 - { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, 208 + { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 209 + { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 228 210 }; 229 211 230 212 /*
+29 -19
drivers/edac/mce_amd.c
··· 689 689 } 690 690 691 691 static const char * const smca_long_names[] = { 692 - [SMCA_LS ... SMCA_LS_V2] = "Load Store Unit", 693 - [SMCA_IF] = "Instruction Fetch Unit", 694 - [SMCA_L2_CACHE] = "L2 Cache", 692 + [SMCA_CS ... SMCA_CS_V2] = "Coherent Station", 693 + [SMCA_DACC_BE] = "DACC Back-end Unit", 694 + [SMCA_DACC_FE] = "DACC Front-end Unit", 695 695 [SMCA_DE] = "Decode Unit", 696 - [SMCA_RESERVED] = "Reserved", 696 + [SMCA_EDDR5CMN] = "eDDR5 CMN Unit", 697 697 [SMCA_EX] = "Execution Unit", 698 698 [SMCA_FP] = "Floating Point Unit", 699 + [SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit", 700 + [SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit", 701 + [SMCA_IF] = "Instruction Fetch Unit", 702 + [SMCA_L2_CACHE] = "L2 Cache", 699 703 [SMCA_L3_CACHE] = "L3 Cache", 700 - [SMCA_CS ... SMCA_CS_V2] = "Coherent Slave", 704 + [SMCA_LS ... SMCA_LS_V2] = "Load Store Unit", 705 + [SMCA_MP5] = "Microprocessor 5 Unit", 706 + [SMCA_MPART] = "MPART Unit", 707 + [SMCA_MPASP ... SMCA_MPASP_V2] = "MPASP Unit", 708 + [SMCA_MPDACC] = "MPDACC Unit", 709 + [SMCA_MPDMA] = "MPDMA Unit", 710 + [SMCA_MPM] = "MPM Unit", 711 + [SMCA_MPRAS] = "MPRAS Unit", 712 + [SMCA_NBIF] = "NBIF Unit", 713 + [SMCA_NBIO] = "Northbridge IO Unit", 714 + [SMCA_PB] = "Parameter Block", 715 + [SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit", 716 + [SMCA_PCIE_PL] = "PCIe Link Unit", 701 717 [SMCA_PIE] = "Power, Interrupts, etc.", 718 + [SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor", 719 + [SMCA_RESERVED] = "Reserved", 720 + [SMCA_SATA] = "SATA Unit", 721 + [SMCA_SHUB] = "System Hub Unit", 722 + [SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit", 723 + [SMCA_SSBDCI] = "Die to Die Interconnect Unit", 702 724 703 725 /* UMC v2 is separate because both of them can exist in a single system. */ 704 726 [SMCA_UMC] = "Unified Memory Controller", 705 727 [SMCA_UMC_V2] = "Unified Memory Controller v2", 706 - [SMCA_PB] = "Parameter Block", 707 - [SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor", 708 - [SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit", 709 - [SMCA_MP5] = "Microprocessor 5 Unit", 710 - [SMCA_MPDMA] = "MPDMA Unit", 711 - [SMCA_NBIO] = "Northbridge IO Unit", 712 - [SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit", 713 - [SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit", 714 - [SMCA_NBIF] = "NBIF Unit", 715 - [SMCA_SHUB] = "System Hub Unit", 716 - [SMCA_SATA] = "SATA Unit", 717 728 [SMCA_USB] = "USB Unit", 718 - [SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit", 719 - [SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit", 720 729 [SMCA_WAFL_PHY] = "WAFL PHY Unit", 721 - [SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit", 730 + [SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit", 731 + [SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit", 722 732 }; 723 733 724 734 static const char *smca_get_long_name(enum smca_bank_types t)