drm/msm/a8xx: Add support for A8x GMU · tjh.dev/kernel@50e8a55

+58 -19

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

··· 224 224 225 225 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 226 226 { 227 - u32 val; 227 + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 228 + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 228 229 int local = gmu->idle_level; 230 + u32 val; 229 231 230 232 /* SPTP and IFPC both report as IFPC */ 231 233 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 232 234 local = GMU_IDLE_STATE_IFPC; 233 235 234 - val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 236 + if (adreno_is_a8xx(adreno_gpu)) 237 + val = gmu_read(gmu, REG_A8XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 238 + else 239 + val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 235 240 236 241 if (val == local) { 237 242 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || ··· 274 269 /* Set the log wptr index 275 270 * note: downstream saves the value in poweroff and restores it here 276 271 */ 277 - if (adreno_is_a7xx(adreno_gpu)) 272 + if (adreno_is_a8xx(adreno_gpu)) 273 + gmu_write(gmu, REG_A8XX_GMU_GENERAL_9, 0); 274 + else if (adreno_is_a7xx(adreno_gpu)) 278 275 gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); 279 276 else 280 277 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); ··· 518 511 * in the power down sequence not being fully executed. That in turn can 519 512 * prevent CX_GDSC from collapsing. Assert Qactive to avoid this. 520 513 */ 521 - if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || 514 + if (adreno_is_a8xx(adreno_gpu)) 515 + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); 516 + else if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || 522 517 adreno_is_7c3(adreno_gpu))) 523 518 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); 524 519 } ··· 528 519 /* Let the GMU know that we are about to go into slumber */ 529 520 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 530 521 { 522 + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 523 + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 531 524 int ret; 532 525 533 526 /* Disable the power counter so the GMU isn't busy */ 534 - gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 527 + if (adreno_is_a8xx(adreno_gpu)) 528 + gmu_write(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 529 + else 530 + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 535 531 536 532 /* Disable SPTP_PC if the CPU is responsible for it */ 537 533 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) ··· 629 615 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 630 616 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 631 617 struct platform_device *pdev = to_platform_device(gmu->dev); 632 - void __iomem *pdcptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc"); 633 618 u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0; 634 619 void __iomem *seqptr = NULL; 635 620 uint32_t pdc_address_offset; 621 + void __iomem *pdcptr; 636 622 bool pdc_in_aop = false; 637 623 624 + /* On A8x and above, RPMH/PDC configurations are entirely configured in AOP */ 625 + if (adreno_is_a8xx(adreno_gpu)) 626 + return; 627 + 628 + pdcptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc"); 638 629 if (IS_ERR(pdcptr)) 639 630 return; 640 631 ··· 768 749 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 769 750 770 751 /* A7xx knows better by default! */ 771 - if (adreno_is_a7xx(adreno_gpu)) 752 + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) 772 753 return; 773 754 774 755 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); ··· 831 812 u32 itcm_base = 0x00000000; 832 813 u32 dtcm_base = 0x00040000; 833 814 834 - if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) 815 + if (adreno_is_a650_family(adreno_gpu) || 816 + adreno_is_a7xx(adreno_gpu) || 817 + adreno_is_a8xx(adreno_gpu)) 835 818 dtcm_base = 0x10004000; 836 819 837 820 if (gmu->legacy) { ··· 897 876 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { 898 877 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); 899 878 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 879 + } else if (adreno_is_a8xx(adreno_gpu)) { 880 + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); 881 + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 900 882 } 901 883 902 884 /* Turn on TCM (Tightly Coupled Memory) retention */ 903 885 if (adreno_is_a7xx(adreno_gpu)) 904 886 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); 905 - else 887 + else if (!adreno_is_a8xx(adreno_gpu)) 906 888 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 907 889 908 890 ret = a6xx_rpmh_start(gmu); ··· 930 906 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 931 907 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 932 908 933 - if (adreno_is_a7xx(adreno_gpu)) { 909 + if (adreno_is_a8xx(adreno_gpu)) { 910 + fence_range_upper = 0x32; 911 + fence_range_lower = 0x8c0; 912 + } else if (adreno_is_a7xx(adreno_gpu)) { 934 913 fence_range_upper = 0x32; 935 914 fence_range_lower = 0x8a0; 936 915 } else { ··· 967 940 chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ 968 941 } 969 942 970 - if (adreno_is_a7xx(adreno_gpu)) { 943 + if (adreno_is_a8xx(adreno_gpu)) { 944 + gmu_write(gmu, REG_A8XX_GMU_GENERAL_10, chipid); 945 + gmu_write(gmu, REG_A8XX_GMU_GENERAL_8, 946 + (gmu->log.iova & GENMASK(31, 12)) | 947 + ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0))); 948 + } else if (adreno_is_a7xx(adreno_gpu)) { 971 949 gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid); 972 950 gmu_write(gmu, REG_A7XX_GMU_GENERAL_8, 973 951 (gmu->log.iova & GENMASK(31, 12)) | ··· 1035 1003 u32 val, seqmem_off = 0; 1036 1004 1037 1005 /* The second spin of A7xx GPUs messed with some register offsets.. */ 1038 - if (adreno_is_a740_family(adreno_gpu)) 1006 + if (adreno_is_a740_family(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) 1039 1007 seqmem_off = 4; 1040 1008 1041 1009 /* Make sure there are no outstanding RPMh votes */ ··· 1048 1016 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, 1049 1017 val, (val & 1), 100, 1000); 1050 1018 1051 - if (!adreno_is_a740_family(adreno_gpu)) 1019 + if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a8xx(adreno_gpu)) 1052 1020 return; 1053 1021 1054 1022 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, ··· 1076 1044 * Turn off keep alive that might have been enabled by the hang 1077 1045 * interrupt 1078 1046 */ 1079 - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 1047 + if (adreno_is_a8xx(adreno_gpu)) 1048 + gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 1049 + else 1050 + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 1080 1051 1081 1052 /* Flush all the queues */ 1082 1053 a6xx_hfi_stop(gmu); ··· 1183 1148 enable_irq(gmu->gmu_irq); 1184 1149 1185 1150 /* Check to see if we are doing a cold or warm boot */ 1186 - if (adreno_is_a7xx(adreno_gpu)) { 1151 + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { 1187 1152 status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ? 1188 1153 GMU_WARM_BOOT : GMU_COLD_BOOT; 1189 1154 } else if (gmu->legacy) { ··· 1512 1477 vote = clamp(peak, 1, BCM_TCS_CMD_VOTE_MASK); 1513 1478 1514 1479 /* GMUs on A7xx votes on both x & y */ 1515 - if (adreno_is_a7xx(adreno_gpu)) 1480 + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) 1516 1481 data[bcm_index] = BCM_TCS_CMD(commit, true, vote, vote); 1517 1482 else 1518 1483 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, vote); ··· 2105 2070 */ 2106 2071 gmu->dummy.size = SZ_4K; 2107 2072 if (adreno_is_a660_family(adreno_gpu) || 2108 - adreno_is_a7xx(adreno_gpu)) { 2073 + adreno_is_a7xx(adreno_gpu) || 2074 + adreno_is_a8xx(adreno_gpu)) { 2109 2075 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 2110 2076 0x60400000, "debug"); 2111 2077 if (ret) 2112 2078 goto err_memory; 2113 2079 2114 - gmu->dummy.size = SZ_8K; 2080 + gmu->dummy.size = SZ_16K; 2115 2081 } 2116 2082 2117 2083 /* Allocate memory for the GMU dummy page */ ··· 2123 2087 2124 2088 /* Note that a650 family also includes a660 family: */ 2125 2089 if (adreno_is_a650_family(adreno_gpu) || 2126 - adreno_is_a7xx(adreno_gpu)) { 2090 + adreno_is_a7xx(adreno_gpu) || 2091 + adreno_is_a8xx(adreno_gpu)) { 2127 2092 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 2128 2093 SZ_16M - SZ_16K, 0x04000, "icache"); 2129 2094 if (ret) ··· 2188 2151 ret = -ENODEV; 2189 2152 goto err_mmio; 2190 2153 } 2154 + } else if (adreno_is_a8xx(adreno_gpu)) { 2155 + gmu->rscc = gmu->mmio + 0x19000; 2191 2156 } else { 2192 2157 gmu->rscc = gmu->mmio + 0x23000; 2193 2158 }

+2 -2

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

··· 19 19 u64 iova; 20 20 }; 21 21 22 - #define GMU_MAX_GX_FREQS 16 23 - #define GMU_MAX_CX_FREQS 4 22 + #define GMU_MAX_GX_FREQS 32 23 + #define GMU_MAX_CX_FREQS 6 24 24 #define GMU_MAX_BCMS 3 25 25 26 26 struct a6xx_bcm {

+7

drivers/gpu/drm/msm/adreno/adreno_gpu.h

··· 50 50 ADRENO_7XX_GEN1, /* a730 family */ 51 51 ADRENO_7XX_GEN2, /* a740 family */ 52 52 ADRENO_7XX_GEN3, /* a750 family */ 53 + ADRENO_8XX_GEN1, /* a830 family */ 54 + ADRENO_8XX_GEN2, /* a840 family */ 53 55 }; 54 56 55 57 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) ··· 565 563 /* Update with non-fake (i.e. non-A702) Gen 7 GPUs */ 566 564 return gpu->info->family == ADRENO_7XX_GEN1 || 567 565 adreno_is_a740_family(gpu); 566 + } 567 + 568 + static inline int adreno_is_a8xx(struct adreno_gpu *gpu) 569 + { 570 + return gpu->info->family >= ADRENO_8XX_GEN1; 568 571 } 569 572 570 573 /* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */

+35 -13

drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml

··· 66 66 <reg32 offset="0x1f81c" name="GMU_CM3_FW_INIT_RESULT"/> 67 67 <reg32 offset="0x1f82d" name="GMU_CM3_CFG"/> 68 68 <reg32 offset="0x1f840" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/> 69 + <reg32 offset="0x1fc10" name="GMU_CX_GMU_POWER_COUNTER_ENABLE" variants="A8XX"/> 69 70 <reg32 offset="0x1f841" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/> 70 71 <reg32 offset="0x1f842" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/> 72 + <reg32 offset="0x1fc40" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_0" variants="A8XX-"/> 73 + <reg32 offset="0x1fc41" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1" variants="A8XX-"/> 71 74 <reg32 offset="0x1f844" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/> 75 + <reg32 offset="0x1fca0" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L" variants="A8XX-"/> 72 76 <reg32 offset="0x1f845" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/> 77 + <reg32 offset="0x1fca1" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H" variants="A8XX-"/> 73 78 <reg32 offset="0x1f846" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/> 74 79 <reg32 offset="0x1f847" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/> 75 80 <reg32 offset="0x1f848" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/> ··· 94 89 </reg32> 95 90 <reg32 offset="0x1f8c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/> 96 91 <reg32 offset="0x1f8c2" name="GMU_PWR_COL_SPTPRAC_HYST"/> 97 - <reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS"> 92 + <reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A6XX"> 98 93 <bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/> 99 94 <bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/> 100 95 <bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/> ··· 104 99 <bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/> 105 100 <bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/> 106 101 </reg32> 107 - <reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX-"> 102 + <reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX"> 103 + <bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/> 104 + <bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/> 105 + </reg32> 106 + <reg32 offset="0x1f7e8" name="GMU_PWR_CLK_STATUS" variants="A8XX-"> 108 107 <bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/> 109 108 <bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/> 110 109 </reg32> ··· 129 120 <bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/> 130 121 </reg32> 131 122 <reg32 offset="0x1f8e9" name="GMU_RPMH_HYST_CTRL"/> 132 - <reg32 offset="0x1f8ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/> 133 - <reg32 offset="0x1f8f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/> 134 - <reg32 offset="0x1f8f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/> 123 + <reg32 offset="0x1f8ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A6XX"/> 124 + <reg32 offset="0x1f7e9" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A8XX-"/> 125 + <reg32 offset="0x1f8f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A6XX"/> 126 + <reg32 offset="0x1f7ec" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A8XX-"/> 127 + <reg32 offset="0x1f8f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A6XX"/> 128 + <reg32 offset="0x1f7ed" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A8XX-"/> 135 129 <reg32 offset="0x1f900" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/> 136 130 <reg32 offset="0x1f901" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/> 137 131 <reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/> ··· 142 130 <reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/> 143 131 <reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L"/> 144 132 <reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H"/> 145 - <reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/> 146 - <reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE"/> 133 + <reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A6XX-A7XX"/> 134 + <reg32 offset="0x1f7e4" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A8XX-"/> 135 + <reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A6XX-A7XX"/> 136 + <reg32 offset="0x1f7e5" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A8XX-"/> 147 137 <reg32 offset="0x1f980" name="GMU_HFI_CTRL_STATUS"/> 148 138 <reg32 offset="0x1f981" name="GMU_HFI_VERSION_INFO"/> 149 139 <reg32 offset="0x1f982" name="GMU_HFI_SFR_ADDR"/> ··· 178 164 <reg32 offset="0x1f9cd" name="GMU_GENERAL_8" variants="A7XX"/> 179 165 <reg32 offset="0x1f9ce" name="GMU_GENERAL_9" variants="A7XX"/> 180 166 <reg32 offset="0x1f9cf" name="GMU_GENERAL_10" variants="A7XX"/> 167 + <reg32 offset="0x1f9c0" name="GMU_GENERAL_0" variants="A8XX"/> 168 + <reg32 offset="0x1f9c1" name="GMU_GENERAL_1" variants="A8XX"/> 169 + <reg32 offset="0x1f9c6" name="GMU_GENERAL_6" variants="A8XX"/> 170 + <reg32 offset="0x1f9c7" name="GMU_GENERAL_7" variants="A8XX"/> 171 + <reg32 offset="0x1f9c8" name="GMU_GENERAL_8" variants="A8XX"/> 172 + <reg32 offset="0x1f9c9" name="GMU_GENERAL_9" variants="A8XX"/> 173 + <reg32 offset="0x1f9ca" name="GMU_GENERAL_10" variants="A8XX"/> 174 + <reg32 offset="0x1f9cb" name="GMU_GENERAL_11" variants="A8XX"/> 181 175 <reg32 offset="0x1f95d" name="GMU_ISENSE_CTRL"/> 182 176 <reg32 offset="0x23120" name="GPU_CS_ENABLE_REG"/> 183 177 <reg32 offset="0x1f95d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/> ··· 255 233 <reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/> 256 234 <reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/> 257 235 <reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/> 258 - <reg32 offset="0x05e6" name="RSCC_TCS4_DRV0_STATUS" variants="A7XX"/> 259 - <reg32 offset="0x068e" name="RSCC_TCS5_DRV0_STATUS" variants="A7XX"/> 260 - <reg32 offset="0x0736" name="RSCC_TCS6_DRV0_STATUS" variants="A7XX"/> 261 - <reg32 offset="0x07de" name="RSCC_TCS7_DRV0_STATUS" variants="A7XX"/> 262 - <reg32 offset="0x0886" name="RSCC_TCS8_DRV0_STATUS" variants="A7XX"/> 263 - <reg32 offset="0x092e" name="RSCC_TCS9_DRV0_STATUS" variants="A7XX"/> 236 + <reg32 offset="0x05e6" name="RSCC_TCS4_DRV0_STATUS" variants="A7XX-"/> 237 + <reg32 offset="0x068e" name="RSCC_TCS5_DRV0_STATUS" variants="A7XX-"/> 238 + <reg32 offset="0x0736" name="RSCC_TCS6_DRV0_STATUS" variants="A7XX-"/> 239 + <reg32 offset="0x07de" name="RSCC_TCS7_DRV0_STATUS" variants="A7XX-"/> 240 + <reg32 offset="0x0886" name="RSCC_TCS8_DRV0_STATUS" variants="A7XX-"/> 241 + <reg32 offset="0x092e" name="RSCC_TCS9_DRV0_STATUS" variants="A7XX-"/> 264 242 </domain> 265 243 266 244 </database>

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