drm/i915/display: Add filter lut values

Add the register bits related to filter lut values
and helper to load the casf filter lut.

These values are golden values and these value has
to be loaded one time while enabling the casf.

v2: update commit message[Ankit]
v3: Add intel_casf prefix to filter_load fn[Jani]
v4: Define the filter macros here

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-5-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

authored by

Nemesa Garg and committed by

Jani Nikula 8 months ago 515d1c89 74ad9ec9

+60

2 changed files

expand all

drivers

gpu

drm

i915

display

intel_casf.c

intel_casf_regs.h

+49

drivers/gpu/drm/i915/display/intel_casf.c

··· 13 13 #define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080) 14 14 #define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160) 15 15 16 + #define FILTER_COEFF_0_125 125 17 + #define FILTER_COEFF_0_25 250 18 + #define FILTER_COEFF_0_5 500 19 + #define FILTER_COEFF_1_0 1000 20 + #define FILTER_COEFF_0_0 0 21 + #define SET_POSITIVE_SIGN(x) ((x) & (~SIGN)) 22 + 16 23 /** 17 24 * DOC: Content Adaptive Sharpness Filter (CASF) 18 25 * ··· 34 27 * an alpha value which blends the sharpened image to 35 28 * original image. 36 29 */ 30 + 31 + /* Default LUT values to be loaded one time. */ 32 + static const u16 sharpness_lut[] = { 33 + 4095, 2047, 1364, 1022, 816, 678, 579, 34 + 504, 444, 397, 357, 323, 293, 268, 244, 224, 35 + 204, 187, 170, 154, 139, 125, 111, 98, 85, 36 + 73, 60, 48, 36, 24, 12, 0 37 + }; 38 + 39 + const u16 filtercoeff_1[] = { 40 + FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5, 41 + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0, 42 + FILTER_COEFF_0_0, 43 + }; 44 + 45 + const u16 filtercoeff_2[] = { 46 + FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5, 47 + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, 48 + FILTER_COEFF_0_0, 49 + }; 50 + 51 + const u16 filtercoeff_3[] = { 52 + FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5, 53 + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, 54 + FILTER_COEFF_0_125, 55 + }; 56 + 57 + static void intel_casf_filter_lut_load(struct intel_crtc *crtc, 58 + const struct intel_crtc_state *crtc_state) 59 + { 60 + struct intel_display *display = to_intel_display(crtc_state); 61 + int i; 62 + 63 + intel_de_write(display, SHRPLUT_INDEX(crtc->pipe), 64 + INDEX_AUTO_INCR | INDEX_VALUE(0)); 65 + 66 + for (i = 0; i < ARRAY_SIZE(sharpness_lut); i++) 67 + intel_de_write(display, SHRPLUT_DATA(crtc->pipe), 68 + sharpness_lut[i]); 69 + } 37 70 38 71 void intel_casf_update_strength(struct intel_crtc_state *crtc_state) 39 72 { ··· 158 111 struct intel_display *display = to_intel_display(crtc_state); 159 112 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 160 113 u32 sharpness_ctl; 114 + 115 + intel_casf_filter_lut_load(crtc, crtc_state); 161 116 162 117 sharpness_ctl = FILTER_EN | FILTER_STRENGTH(crtc_state->hw.casf_params.strength); 163 118

+11

drivers/gpu/drm/i915/display/intel_casf_regs.h

··· 19 19 #define SHARPNESS_FILTER_SIZE_5X5 REG_FIELD_PREP(FILTER_SIZE_MASK, 1) 20 20 #define SHARPNESS_FILTER_SIZE_7X7 REG_FIELD_PREP(FILTER_SIZE_MASK, 2) 21 21 22 + #define _SHRPLUT_DATA_A 0x682B8 23 + #define _SHRPLUT_DATA_B 0x68AB8 24 + #define SHRPLUT_DATA(pipe) _MMIO_PIPE(pipe, _SHRPLUT_DATA_A, _SHRPLUT_DATA_B) 25 + 26 + #define _SHRPLUT_INDEX_A 0x682B4 27 + #define _SHRPLUT_INDEX_B 0x68AB4 28 + #define SHRPLUT_INDEX(pipe) _MMIO_PIPE(pipe, _SHRPLUT_INDEX_A, _SHRPLUT_INDEX_B) 29 + #define INDEX_AUTO_INCR REG_BIT(10) 30 + #define INDEX_VALUE_MASK REG_GENMASK(4, 0) 31 + #define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x)) 32 + 22 33 #endif /* __INTEL_CASF_REGS__ */

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