tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/msm/a6xx: Store correct gmu_cgc_mode in struct a6xx_info

Store the correct values that we happen to have for some A7xx SKUs in
the GPU info struct and fill out the missing information for A6xx GPUs
based on downstream kernel information.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611094/
[add missing entry to a615 catalog to resolve conflict]
Signed-off-by: Rob Clark <robdclark@chromium.org>

authored by

Konrad Dybcio and committed by
Rob Clark d50a8363 2bbb5fe3

+20
+19
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
··· 636 636 .a6xx = &(const struct a6xx_info) { 637 637 .hwcg = a612_hwcg, 638 638 .protect = &a630_protect, 639 + .gmu_cgc_mode = 0x00020202, 639 640 .prim_fifo_threshold = 0x00080000, 640 641 }, 641 642 /* ··· 668 667 .a6xx = &(const struct a6xx_info) { 669 668 .hwcg = a615_hwcg, 670 669 .protect = &a630_protect, 670 + .gmu_cgc_mode = 0x00000222, 671 671 .prim_fifo_threshold = 0x0018000, 672 672 }, 673 673 .speedbins = ADRENO_SPEEDBINS( ··· 698 696 .a6xx = &(const struct a6xx_info) { 699 697 .hwcg = a615_hwcg, 700 698 .protect = &a630_protect, 699 + .gmu_cgc_mode = 0x00000222, 701 700 .prim_fifo_threshold = 0x00180000, 702 701 }, 703 702 .speedbins = ADRENO_SPEEDBINS( ··· 722 719 .init = a6xx_gpu_init, 723 720 .a6xx = &(const struct a6xx_info) { 724 721 .protect = &a630_protect, 722 + .gmu_cgc_mode = 0x00000222, 725 723 .prim_fifo_threshold = 0x00180000, 726 724 }, 727 725 .speedbins = ADRENO_SPEEDBINS( ··· 746 742 .a6xx = &(const struct a6xx_info) { 747 743 .hwcg = a615_hwcg, 748 744 .protect = &a630_protect, 745 + .gmu_cgc_mode = 0x00000222, 749 746 .prim_fifo_threshold = 0x00018000, 750 747 }, 751 748 .speedbins = ADRENO_SPEEDBINS( ··· 770 765 .a6xx = &(const struct a6xx_info) { 771 766 .hwcg = a615_hwcg, 772 767 .protect = &a630_protect, 768 + .gmu_cgc_mode = 0x00000222, 773 769 .prim_fifo_threshold = 0x00018000, 774 770 }, 775 771 .speedbins = ADRENO_SPEEDBINS( ··· 794 788 .a6xx = &(const struct a6xx_info) { 795 789 .hwcg = a615_hwcg, 796 790 .protect = &a630_protect, 791 + .gmu_cgc_mode = 0x00000222, 797 792 .prim_fifo_threshold = 0x00018000, 798 793 }, 799 794 .speedbins = ADRENO_SPEEDBINS( ··· 823 816 .a6xx = &(const struct a6xx_info) { 824 817 .hwcg = a630_hwcg, 825 818 .protect = &a630_protect, 819 + .gmu_cgc_mode = 0x00020202, 826 820 .prim_fifo_threshold = 0x00180000, 827 821 }, 828 822 }, { ··· 842 834 .a6xx = &(const struct a6xx_info) { 843 835 .hwcg = a640_hwcg, 844 836 .protect = &a630_protect, 837 + .gmu_cgc_mode = 0x00020202, 845 838 .prim_fifo_threshold = 0x00180000, 846 839 }, 847 840 .speedbins = ADRENO_SPEEDBINS( ··· 866 857 .a6xx = &(const struct a6xx_info) { 867 858 .hwcg = a650_hwcg, 868 859 .protect = &a650_protect, 860 + .gmu_cgc_mode = 0x00020202, 869 861 .prim_fifo_threshold = 0x00300200, 870 862 }, 871 863 .address_space_size = SZ_16G, ··· 893 883 .a6xx = &(const struct a6xx_info) { 894 884 .hwcg = a660_hwcg, 895 885 .protect = &a660_protect, 886 + .gmu_cgc_mode = 0x00020000, 896 887 .prim_fifo_threshold = 0x00300200, 897 888 }, 898 889 .address_space_size = SZ_16G, ··· 913 902 .a6xx = &(const struct a6xx_info) { 914 903 .hwcg = a660_hwcg, 915 904 .protect = &a660_protect, 905 + .gmu_cgc_mode = 0x00020202, 916 906 .prim_fifo_threshold = 0x00200200, 917 907 }, 918 908 .address_space_size = SZ_16G, ··· 940 928 .a6xx = &(const struct a6xx_info) { 941 929 .hwcg = a640_hwcg, 942 930 .protect = &a630_protect, 931 + .gmu_cgc_mode = 0x00020202, 943 932 .prim_fifo_threshold = 0x00200200, 944 933 }, 945 934 }, { ··· 959 946 .a6xx = &(const struct a6xx_info) { 960 947 .hwcg = a690_hwcg, 961 948 .protect = &a690_protect, 949 + .gmu_cgc_mode = 0x00020200, 962 950 .prim_fifo_threshold = 0x00800200, 963 951 }, 964 952 .address_space_size = SZ_16G, ··· 1221 1207 .a6xx = &(const struct a6xx_info) { 1222 1208 .hwcg = a702_hwcg, 1223 1209 .protect = &a650_protect, 1210 + .gmu_cgc_mode = 0x00020202, 1224 1211 .prim_fifo_threshold = 0x0000c000, 1225 1212 }, 1226 1213 .speedbins = ADRENO_SPEEDBINS( ··· 1246 1231 .a6xx = &(const struct a6xx_info) { 1247 1232 .hwcg = a730_hwcg, 1248 1233 .protect = &a730_protect, 1234 + .gmu_cgc_mode = 0x00020000, 1249 1235 }, 1250 1236 .address_space_size = SZ_16G, 1251 1237 }, { ··· 1266 1250 .hwcg = a740_hwcg, 1267 1251 .protect = &a730_protect, 1268 1252 .gmu_chipid = 0x7020100, 1253 + .gmu_cgc_mode = 0x00020202, 1269 1254 }, 1270 1255 .address_space_size = SZ_16G, 1271 1256 }, { ··· 1285 1268 .hwcg = a740_hwcg, 1286 1269 .protect = &a730_protect, 1287 1270 .gmu_chipid = 0x7050001, 1271 + .gmu_cgc_mode = 0x00020202, 1288 1272 }, 1289 1273 .address_space_size = SZ_256G, 1290 1274 }, { ··· 1304 1286 .a6xx = &(const struct a6xx_info) { 1305 1287 .protect = &a730_protect, 1306 1288 .gmu_chipid = 0x7090100, 1289 + .gmu_cgc_mode = 0x00020202, 1307 1290 }, 1308 1291 .address_space_size = SZ_16G, 1309 1292 }
+1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
··· 22 22 const struct adreno_reglist *hwcg; 23 23 const struct adreno_protect *protect; 24 24 u32 gmu_chipid; 25 + u32 gmu_cgc_mode; 25 26 u32 prim_fifo_threshold; 26 27 }; 27 28