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Merge branch 'net-mlx5-add-balance-id-support-for-lag-multiplane-groups'

Tariq Toukan says:

====================
net/mlx5: Add balance ID support for LAG multiplane groups

This series adds balance ID support for MLX5 LAG in multiplane
configurations.

See detailed description by Mark below [1].

[1]
The problem: In complex multiplane LAG setups, we need finer control over LAG
groups. Currently, devices with the same system image GUID are treated
identically, but hardware now supports per-multiplane-group balance IDs that
let us differentiate between them. On such systems image system guid
isn't enough to decide which devices should be part of which LAG.

The solution: Extend the system image GUID with a balance ID byte when the
hardware supports it. This gives us the granularity we need without breaking
existing deployments.

What this series does:

1. Clean up some duplicate code while we're here
2. Rework the system image GUID infrastructure to handle variable lengths
3. Update PTP clock pairing to use the new approach
4. Restructure capability setting to make room for the new feature
5. Actually implement the balance ID support

The key insight is in patch 5: we only append the balance ID when both
capabilities are present, so older hardware and software continue to work
exactly as before. For newer setups, you get the extra byte that enables
per-multiplane-group load balancing.

This has been tested with both old and new hardware configurations.
====================

Link: https://patch.msgid.link/1761211020-925651-1-git-send-email-tariqt@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

Paolo Abeni 51f32255 0bc4059c

+112 -66
+8 -4
drivers/net/ethernet/mellanox/mlx5/core/dev.c
··· 564 564 565 565 bool mlx5_same_hw_devs(struct mlx5_core_dev *dev, struct mlx5_core_dev *peer_dev) 566 566 { 567 - u64 fsystem_guid, psystem_guid; 567 + u8 fsystem_guid[MLX5_SW_IMAGE_GUID_MAX_BYTES]; 568 + u8 psystem_guid[MLX5_SW_IMAGE_GUID_MAX_BYTES]; 569 + u8 flen; 570 + u8 plen; 568 571 569 - fsystem_guid = mlx5_query_nic_system_image_guid(dev); 570 - psystem_guid = mlx5_query_nic_system_image_guid(peer_dev); 572 + mlx5_query_nic_sw_system_image_guid(dev, fsystem_guid, &flen); 573 + mlx5_query_nic_sw_system_image_guid(peer_dev, psystem_guid, &plen); 571 574 572 - return (fsystem_guid && psystem_guid && fsystem_guid == psystem_guid); 575 + return plen && flen && flen == plen && 576 + !memcmp(fsystem_guid, psystem_guid, flen); 573 577 }
+2 -5
drivers/net/ethernet/mellanox/mlx5/core/en/devlink.c
··· 40 40 static void 41 41 mlx5e_devlink_get_port_parent_id(struct mlx5_core_dev *dev, struct netdev_phys_item_id *ppid) 42 42 { 43 - u64 parent_id; 44 - 45 - parent_id = mlx5_query_nic_system_image_guid(dev); 46 - ppid->id_len = sizeof(parent_id); 47 - memcpy(ppid->id, &parent_id, sizeof(parent_id)); 43 + BUILD_BUG_ON(MLX5_SW_IMAGE_GUID_MAX_BYTES > MAX_PHYS_ITEM_ID_LEN); 44 + mlx5_query_nic_sw_system_image_guid(dev, ppid->id, &ppid->id_len); 48 45 } 49 46 50 47 int mlx5e_devlink_port_register(struct mlx5e_dev *mlx5e_dev,
+9 -4
drivers/net/ethernet/mellanox/mlx5/core/en/mapping.c
··· 6 6 #include <linux/xarray.h> 7 7 #include <linux/hashtable.h> 8 8 #include <linux/refcount.h> 9 + #include <linux/mlx5/driver.h> 9 10 10 11 #include "mapping.h" 11 12 ··· 25 24 struct delayed_work dwork; 26 25 struct list_head pending_list; 27 26 spinlock_t pending_list_lock; /* Guards pending list */ 28 - u64 id; 27 + u8 id[MLX5_SW_IMAGE_GUID_MAX_BYTES]; 28 + u8 id_len; 29 29 u8 type; 30 30 struct list_head list; 31 31 refcount_t refcount; ··· 222 220 } 223 221 224 222 struct mapping_ctx * 225 - mapping_create_for_id(u64 id, u8 type, size_t data_size, u32 max_id, bool delayed_removal) 223 + mapping_create_for_id(u8 *id, u8 id_len, u8 type, size_t data_size, u32 max_id, 224 + bool delayed_removal) 226 225 { 227 226 struct mapping_ctx *ctx; 228 227 229 228 mutex_lock(&shared_ctx_lock); 230 229 list_for_each_entry(ctx, &shared_ctx_list, list) { 231 - if (ctx->id == id && ctx->type == type) { 230 + if (ctx->type == type && ctx->id_len == id_len && 231 + !memcmp(id, ctx->id, id_len)) { 232 232 if (refcount_inc_not_zero(&ctx->refcount)) 233 233 goto unlock; 234 234 break; ··· 241 237 if (IS_ERR(ctx)) 242 238 goto unlock; 243 239 244 - ctx->id = id; 240 + memcpy(ctx->id, id, id_len); 241 + ctx->id_len = id_len; 245 242 ctx->type = type; 246 243 list_add(&ctx->list, &shared_ctx_list); 247 244
+2 -1
drivers/net/ethernet/mellanox/mlx5/core/en/mapping.h
··· 27 27 /* adds mapping with an id or get an existing mapping with the same id 28 28 */ 29 29 struct mapping_ctx * 30 - mapping_create_for_id(u64 id, u8 type, size_t data_size, u32 max_id, bool delayed_removal); 30 + mapping_create_for_id(u8 *id, u8 id_len, u8 type, size_t data_size, u32 max_id, 31 + bool delayed_removal); 31 32 32 33 #endif /* __MLX5_MAPPING_H__ */
+1 -5
drivers/net/ethernet/mellanox/mlx5/core/en/rep/bridge.c
··· 30 30 { 31 31 struct mlx5e_priv *priv = netdev_priv(dev); 32 32 struct mlx5_core_dev *mdev, *esw_mdev; 33 - u64 system_guid, esw_system_guid; 34 33 35 34 mdev = priv->mdev; 36 35 esw_mdev = esw->dev; 37 36 38 - system_guid = mlx5_query_nic_system_image_guid(mdev); 39 - esw_system_guid = mlx5_query_nic_system_image_guid(esw_mdev); 40 - 41 - return system_guid == esw_system_guid; 37 + return mlx5_same_hw_devs(mdev, esw_mdev); 42 38 } 43 39 44 40 static struct net_device *
+5 -3
drivers/net/ethernet/mellanox/mlx5/core/en/tc/int_port.c
··· 307 307 { 308 308 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 309 309 struct mlx5e_tc_int_port_priv *int_port_priv; 310 - u64 mapping_id; 310 + u8 mapping_id[MLX5_SW_IMAGE_GUID_MAX_BYTES]; 311 + u8 id_len; 311 312 312 313 if (!mlx5e_tc_int_port_supported(esw)) 313 314 return NULL; ··· 317 316 if (!int_port_priv) 318 317 return NULL; 319 318 320 - mapping_id = mlx5_query_nic_system_image_guid(priv->mdev); 319 + mlx5_query_nic_sw_system_image_guid(priv->mdev, mapping_id, &id_len); 321 320 322 - int_port_priv->metadata_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_INT_PORT, 321 + int_port_priv->metadata_mapping = mapping_create_for_id(mapping_id, id_len, 322 + MAPPING_TYPE_INT_PORT, 323 323 sizeof(u32) * 2, 324 324 (1 << ESW_VPORT_BITS) - 1, true); 325 325 if (IS_ERR(int_port_priv->metadata_mapping)) {
+7 -4
drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c
··· 2287 2287 enum mlx5_flow_namespace_type ns_type, 2288 2288 struct mlx5e_post_act *post_act) 2289 2289 { 2290 + u8 mapping_id[MLX5_SW_IMAGE_GUID_MAX_BYTES]; 2290 2291 struct mlx5_tc_ct_priv *ct_priv; 2291 2292 struct mlx5_core_dev *dev; 2292 - u64 mapping_id; 2293 + u8 id_len; 2293 2294 int err; 2294 2295 2295 2296 dev = priv->mdev; ··· 2302 2301 if (!ct_priv) 2303 2302 goto err_alloc; 2304 2303 2305 - mapping_id = mlx5_query_nic_system_image_guid(dev); 2304 + mlx5_query_nic_sw_system_image_guid(dev, mapping_id, &id_len); 2306 2305 2307 - ct_priv->zone_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_ZONE, 2306 + ct_priv->zone_mapping = mapping_create_for_id(mapping_id, id_len, 2307 + MAPPING_TYPE_ZONE, 2308 2308 sizeof(u16), 0, true); 2309 2309 if (IS_ERR(ct_priv->zone_mapping)) { 2310 2310 err = PTR_ERR(ct_priv->zone_mapping); 2311 2311 goto err_mapping_zone; 2312 2312 } 2313 2313 2314 - ct_priv->labels_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_LABELS, 2314 + ct_priv->labels_mapping = mapping_create_for_id(mapping_id, id_len, 2315 + MAPPING_TYPE_LABELS, 2315 2316 sizeof(u32) * 4, 0, true); 2316 2317 if (IS_ERR(ct_priv->labels_mapping)) { 2317 2318 err = PTR_ERR(ct_priv->labels_mapping);
+17 -15
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
··· 3614 3614 bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv) 3615 3615 { 3616 3616 struct mlx5_core_dev *fmdev, *pmdev; 3617 - u64 fsystem_guid, psystem_guid; 3618 3617 3619 3618 fmdev = priv->mdev; 3620 3619 pmdev = peer_priv->mdev; 3621 3620 3622 - fsystem_guid = mlx5_query_nic_system_image_guid(fmdev); 3623 - psystem_guid = mlx5_query_nic_system_image_guid(pmdev); 3624 - 3625 - return (fsystem_guid == psystem_guid); 3621 + return mlx5_same_hw_devs(fmdev, pmdev); 3626 3622 } 3627 3623 3628 3624 static int ··· 5233 5237 int mlx5e_tc_nic_init(struct mlx5e_priv *priv) 5234 5238 { 5235 5239 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs); 5240 + u8 mapping_id[MLX5_SW_IMAGE_GUID_MAX_BYTES]; 5236 5241 struct mlx5_core_dev *dev = priv->mdev; 5237 5242 struct mapping_ctx *chains_mapping; 5238 5243 struct mlx5_chains_attr attr = {}; 5239 - u64 mapping_id; 5244 + u8 id_len; 5240 5245 int err; 5241 5246 5242 5247 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr); ··· 5253 5256 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key); 5254 5257 lockdep_init_map(&tc->ht.run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0); 5255 5258 5256 - mapping_id = mlx5_query_nic_system_image_guid(dev); 5259 + mlx5_query_nic_sw_system_image_guid(dev, mapping_id, &id_len); 5257 5260 5258 - chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN, 5261 + chains_mapping = mapping_create_for_id(mapping_id, id_len, 5262 + MAPPING_TYPE_CHAIN, 5259 5263 sizeof(struct mlx5_mapped_obj), 5260 - MLX5E_TC_TABLE_CHAIN_TAG_MASK, true); 5264 + MLX5E_TC_TABLE_CHAIN_TAG_MASK, 5265 + true); 5261 5266 5262 5267 if (IS_ERR(chains_mapping)) { 5263 5268 err = PTR_ERR(chains_mapping); ··· 5390 5391 int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv) 5391 5392 { 5392 5393 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts); 5394 + u8 mapping_id[MLX5_SW_IMAGE_GUID_MAX_BYTES]; 5393 5395 struct mlx5_devcom_match_attr attr = {}; 5394 5396 struct netdev_phys_item_id ppid; 5395 5397 struct mlx5e_rep_priv *rpriv; 5396 5398 struct mapping_ctx *mapping; 5397 5399 struct mlx5_eswitch *esw; 5398 5400 struct mlx5e_priv *priv; 5399 - u64 mapping_id; 5400 5401 int err = 0; 5402 + u8 id_len; 5401 5403 5402 5404 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv); 5403 5405 priv = netdev_priv(rpriv->netdev); ··· 5416 5416 5417 5417 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act); 5418 5418 5419 - mapping_id = mlx5_query_nic_system_image_guid(esw->dev); 5419 + mlx5_query_nic_sw_system_image_guid(esw->dev, mapping_id, &id_len); 5420 5420 5421 - mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL, 5421 + mapping = mapping_create_for_id(mapping_id, id_len, MAPPING_TYPE_TUNNEL, 5422 5422 sizeof(struct tunnel_match_key), 5423 5423 TUNNEL_INFO_BITS_MASK, true); 5424 5424 ··· 5431 5431 /* Two last values are reserved for stack devices slow path table mark 5432 5432 * and bridge ingress push mark. 5433 5433 */ 5434 - mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS, 5435 - sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true); 5434 + mapping = mapping_create_for_id(mapping_id, id_len, 5435 + MAPPING_TYPE_TUNNEL_ENC_OPTS, 5436 + sz_enc_opts, ENC_OPTS_BITS_MASK - 2, 5437 + true); 5436 5438 if (IS_ERR(mapping)) { 5437 5439 err = PTR_ERR(mapping); 5438 5440 goto err_enc_opts_mapping; ··· 5455 5453 5456 5454 err = netif_get_port_parent_id(priv->netdev, &ppid, false); 5457 5455 if (!err) { 5458 - memcpy(&attr.key.val, &ppid.id, sizeof(attr.key.val)); 5456 + memcpy(&attr.key.buf, &ppid.id, ppid.id_len); 5459 5457 attr.flags = MLX5_DEVCOM_MATCH_FLAGS_NS; 5460 5458 attr.net = mlx5_core_net(esw->dev); 5461 5459 mlx5_esw_offloads_devcom_init(esw, &attr);
+5 -3
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
··· 3557 3557 3558 3558 int esw_offloads_enable(struct mlx5_eswitch *esw) 3559 3559 { 3560 + u8 mapping_id[MLX5_SW_IMAGE_GUID_MAX_BYTES]; 3560 3561 struct mapping_ctx *reg_c0_obj_pool; 3561 3562 struct mlx5_vport *vport; 3562 3563 unsigned long i; 3563 - u64 mapping_id; 3564 + u8 id_len; 3564 3565 int err; 3565 3566 3566 3567 mutex_init(&esw->offloads.termtbl_mutex); ··· 3583 3582 if (err) 3584 3583 goto err_vport_metadata; 3585 3584 3586 - mapping_id = mlx5_query_nic_system_image_guid(esw->dev); 3585 + mlx5_query_nic_sw_system_image_guid(esw->dev, mapping_id, &id_len); 3587 3586 3588 - reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN, 3587 + reg_c0_obj_pool = mapping_create_for_id(mapping_id, id_len, 3588 + MAPPING_TYPE_CHAIN, 3589 3589 sizeof(struct mlx5_mapped_obj), 3590 3590 ESW_REG_C0_USER_DATA_METADATA_MASK, 3591 3591 true);
+3 -1
drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
··· 1418 1418 static int mlx5_lag_register_hca_devcom_comp(struct mlx5_core_dev *dev) 1419 1419 { 1420 1420 struct mlx5_devcom_match_attr attr = { 1421 - .key.val = mlx5_query_nic_system_image_guid(dev), 1422 1421 .flags = MLX5_DEVCOM_MATCH_FLAGS_NS, 1423 1422 .net = mlx5_core_net(dev), 1424 1423 }; 1424 + u8 len __always_unused; 1425 + 1426 + mlx5_query_nic_sw_system_image_guid(dev, attr.key.buf, &len); 1425 1427 1426 1428 /* This component is use to sync adding core_dev to lag_dev and to sync 1427 1429 * changes of mlx5_adev_devices between LAG layer and other layers.
+9 -10
drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
··· 1432 1432 return 0; 1433 1433 } 1434 1434 1435 - static void mlx5_shared_clock_register(struct mlx5_core_dev *mdev, u64 key) 1435 + static void mlx5_shared_clock_register(struct mlx5_core_dev *mdev, 1436 + u8 identity[MLX5_RT_CLOCK_IDENTITY_SIZE]) 1436 1437 { 1437 1438 struct mlx5_core_dev *peer_dev, *next = NULL; 1438 - struct mlx5_devcom_match_attr attr = { 1439 - .key.val = key, 1440 - }; 1439 + struct mlx5_devcom_match_attr attr = {}; 1441 1440 struct mlx5_devcom_comp_dev *compd; 1442 1441 struct mlx5_devcom_comp_dev *pos; 1442 + 1443 + BUILD_BUG_ON(MLX5_RT_CLOCK_IDENTITY_SIZE > MLX5_DEVCOM_MATCH_KEY_MAX); 1444 + memcpy(attr.key.buf, identity, MLX5_RT_CLOCK_IDENTITY_SIZE); 1443 1445 1444 1446 compd = mlx5_devcom_register_component(mdev->priv.devc, 1445 1447 MLX5_DEVCOM_SHARED_CLOCK, ··· 1596 1594 { 1597 1595 u8 identity[MLX5_RT_CLOCK_IDENTITY_SIZE]; 1598 1596 struct mlx5_clock_dev_state *clock_state; 1599 - u64 key; 1600 1597 int err; 1601 1598 1602 1599 if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) { ··· 1611 1610 mdev->clock_state = clock_state; 1612 1611 1613 1612 if (MLX5_CAP_MCAM_REG3(mdev, mrtcq) && mlx5_real_time_mode(mdev)) { 1614 - if (mlx5_clock_identity_get(mdev, identity)) { 1613 + if (mlx5_clock_identity_get(mdev, identity)) 1615 1614 mlx5_core_warn(mdev, "failed to get rt clock identity, create ptp dev per function\n"); 1616 - } else { 1617 - memcpy(&key, &identity, sizeof(key)); 1618 - mlx5_shared_clock_register(mdev, key); 1619 - } 1615 + else 1616 + mlx5_shared_clock_register(mdev, identity); 1620 1617 } 1621 1618 1622 1619 if (!mdev->clock) {
+2
drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h
··· 10 10 MLX5_DEVCOM_MATCH_FLAGS_NS = BIT(0), 11 11 }; 12 12 13 + #define MLX5_DEVCOM_MATCH_KEY_MAX 32 13 14 union mlx5_devcom_match_key { 14 15 u64 val; 16 + u8 buf[MLX5_DEVCOM_MATCH_KEY_MAX]; 15 17 }; 16 18 17 19 struct mlx5_devcom_match_attr {
+17 -6
drivers/net/ethernet/mellanox/mlx5/core/main.c
··· 553 553 554 554 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 555 555 { 556 + bool do_set = false; 556 557 void *set_hca_cap; 557 558 int err; 558 559 ··· 564 563 if (err) 565 564 return err; 566 565 567 - if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 568 - !(dev->priv.sw_vhca_id > 0)) 569 - return 0; 570 - 571 566 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 572 567 capability); 573 568 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 574 569 MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 575 - MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 576 570 577 - return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 571 + if (MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) && 572 + dev->priv.sw_vhca_id > 0) { 573 + MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 574 + do_set = true; 575 + } 576 + 577 + if (MLX5_CAP_GEN_2_MAX(dev, lag_per_mp_group)) { 578 + MLX5_SET(cmd_hca_cap_2, set_hca_cap, lag_per_mp_group, 1); 579 + do_set = true; 580 + } 581 + 582 + /* some FW versions that support querying MLX5_CAP_GENERAL_2 583 + * capabilities but don't support setting them. 584 + * Skip unnecessary update to hca_cap_2 when no changes were introduced 585 + */ 586 + return do_set ? set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2) : 0; 578 587 } 579 588 580 589 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
+2
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
··· 444 444 void mlx5_uninit_one_light(struct mlx5_core_dev *dev); 445 445 void mlx5_unload_one_light(struct mlx5_core_dev *dev); 446 446 447 + void mlx5_query_nic_sw_system_image_guid(struct mlx5_core_dev *mdev, u8 *buf, 448 + u8 *len); 447 449 int mlx5_vport_set_other_func_cap(struct mlx5_core_dev *dev, const void *hca_cap, u16 vport, 448 450 u16 opmod); 449 451 #define mlx5_vport_get_other_func_general_cap(dev, vport, out) \
+19
drivers/net/ethernet/mellanox/mlx5/core/vport.c
··· 1190 1190 } 1191 1191 EXPORT_SYMBOL_GPL(mlx5_query_nic_system_image_guid); 1192 1192 1193 + void mlx5_query_nic_sw_system_image_guid(struct mlx5_core_dev *mdev, u8 *buf, 1194 + u8 *len) 1195 + { 1196 + u64 fw_system_image_guid; 1197 + 1198 + *len = 0; 1199 + 1200 + fw_system_image_guid = mlx5_query_nic_system_image_guid(mdev); 1201 + if (!fw_system_image_guid) 1202 + return; 1203 + 1204 + memcpy(buf, &fw_system_image_guid, sizeof(fw_system_image_guid)); 1205 + *len += sizeof(fw_system_image_guid); 1206 + 1207 + if (MLX5_CAP_GEN_2(mdev, load_balance_id) && 1208 + MLX5_CAP_GEN_2(mdev, lag_per_mp_group)) 1209 + buf[(*len)++] = MLX5_CAP_GEN_2(mdev, load_balance_id); 1210 + } 1211 + 1193 1212 static bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, 1194 1213 u16 vport_num, u16 *vhca_id) 1195 1214 {
+3
include/linux/mlx5/driver.h
··· 1379 1379 { 1380 1380 return devlink_net(priv_to_devlink(dev)); 1381 1381 } 1382 + 1383 + #define MLX5_SW_IMAGE_GUID_MAX_BYTES 9 1384 + 1382 1385 #endif /* MLX5_DRIVER_H */