Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-tenstorrent', 'clk-rockchip', 'clk-imx' and 'clk-allwinner' into clk-next
* clk-tenstorrent:
clk: tenstorrent: Add Atlantis clock controller driver
reset: tenstorrent: Add reset controller for Atlantis
dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu
* clk-rockchip:
clk: rockchip: rk3568: Add PCIe pipe clock gates
clk: rockchip: Add clock controller for the RV1103B
dt-bindings: clock: rockchip: Add RV1103B CRU support
* clk-imx:
clk: imx8mq: Correct the CSI PHY sels
clk: vf610: Add support for the Ethernet switch clocks
dt-bindings: clock: vf610: Add definitions for MTIP L2 switch
dt-bindings: clock: vf610: Drop VF610_CLK_END define
clk: vf610: Move VF610_CLK_END define to clk-vf610 driver
clk: imx: imx8-acm: fix flags for acm clocks
clk: imx: imx6q: Fix device node reference leak in of_assigned_ldb_sels()
clk: imx: imx6q: Fix device node reference leak in pll6_bypassed()
clk: imx: fracn-gppll: Add 477.4MHz support
clk: imx: fracn-gppll: Add 333.333333 MHz support
clk: imx: pll14xx: Use unsigned format specifier
dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad
* clk-allwinner:
clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock
+2238
-9
+4
Documentation/devicetree/bindings/clock/imx6q-clock.yaml
+4
Documentation/devicetree/bindings/clock/imx6q-clock.yaml
···
29
29
const: 1
30
30
31
31
clocks:
32
+
minItems: 5
32
33
items:
33
34
- description: 24m osc
34
35
- description: 32k osc
35
36
- description: ckih1 clock input
36
37
- description: anaclk1 clock input
37
38
- description: anaclk2 clock input
39
+
- description: clock input from enet ref pad
38
40
39
41
clock-names:
42
+
minItems: 5
40
43
items:
41
44
- const: osc
42
45
- const: ckil
43
46
- const: ckih1
44
47
- const: anaclk1
45
48
- const: anaclk2
49
+
- const: enet_ref_pad
46
50
47
51
fsl,pmic-stby-poweroff:
48
52
$ref: /schemas/types.yaml#/definitions/flag
+4
Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
+4
Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
···
29
29
const: 1
30
30
31
31
clocks:
32
+
minItems: 4
32
33
items:
33
34
- description: 32k osc
34
35
- description: 24m osc
35
36
- description: ipp_di0 clock input
36
37
- description: ipp_di1 clock input
38
+
- description: clock input from enet1 ref pad
37
39
38
40
clock-names:
41
+
minItems: 4
39
42
items:
40
43
- const: ckil
41
44
- const: osc
42
45
- const: ipp_di0
43
46
- const: ipp_di1
47
+
- const: enet1_ref_pad
44
48
45
49
required:
46
50
- compatible
+1
Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
+1
Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
+54
Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
+54
Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/tenstorrent,atlantis-prcm-rcpu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Tenstorrent Atlantis PRCM (Power, Reset, Clock Management) Module
8
+
9
+
maintainers:
10
+
- Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
11
+
12
+
description:
13
+
Multifunctional register block found in Tenstorrent Atlantis SoC whose main
14
+
function is to control clocks and resets. This block is instantiated multiple
15
+
times in the SoC, each block controls clock and resets for a different
16
+
subsystem. RCPU prcm serves low speed IO interfaces.
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- tenstorrent,atlantis-prcm-rcpu
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
maxItems: 1
28
+
29
+
"#clock-cells":
30
+
const: 1
31
+
description:
32
+
See <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h> for valid indices.
33
+
34
+
"#reset-cells":
35
+
const: 1
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
- clocks
41
+
- "#clock-cells"
42
+
- "#reset-cells"
43
+
44
+
additionalProperties: false
45
+
46
+
examples:
47
+
- |
48
+
clock-controller@a8000000 {
49
+
compatible = "tenstorrent,atlantis-prcm-rcpu";
50
+
reg = <0xa8000000 0x10000>;
51
+
clocks = <&osc_24m>;
52
+
#clock-cells = <1>;
53
+
#reset-cells = <1>;
54
+
};
+4
MAINTAINERS
+4
MAINTAINERS
···
22812
22812
L: linux-riscv@lists.infradead.org
22813
22813
S: Maintained
22814
22814
T: git https://github.com/tenstorrent/linux.git
22815
+
F: Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
22815
22816
F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
22816
22817
F: arch/riscv/boot/dts/tenstorrent/
22818
+
F: drivers/clk/tenstorrent/
22819
+
F: drivers/reset/reset-tenstorrent-atlantis.c
22820
+
F: include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
22817
22821
22818
22822
RISC-V THEAD SoC SUPPORT
22819
22823
M: Drew Fustini <fustini@kernel.org>
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
···
532
532
source "drivers/clk/sunxi/Kconfig"
533
533
source "drivers/clk/sunxi-ng/Kconfig"
534
534
source "drivers/clk/tegra/Kconfig"
535
+
source "drivers/clk/tenstorrent/Kconfig"
535
536
source "drivers/clk/thead/Kconfig"
536
537
source "drivers/clk/stm32/Kconfig"
537
538
source "drivers/clk/ti/Kconfig"
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
+2
drivers/clk/imx/clk-fracn-gppll.c
+2
drivers/clk/imx/clk-fracn-gppll.c
···
85
85
PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
86
86
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
87
87
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
88
+
PLL_FRACN_GP(477400000U, 119, 35, 100, 0, 6),
88
89
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
89
90
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
90
91
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
92
+
PLL_FRACN_GP(333333333U, 125, 0, 1, 1, 9),
91
93
PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
92
94
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
93
95
PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20),
+11
-1
drivers/clk/imx/clk-imx6q.c
+11
-1
drivers/clk/imx/clk-imx6q.c
···
188
188
}
189
189
if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
190
190
pr_err("ccm: parent clock %d not in ccm\n", index);
191
+
of_node_put(clkspec.np);
191
192
return;
192
193
}
193
194
parent = clkspec.args[0];
195
+
of_node_put(clkspec.np);
194
196
195
197
rc = of_parse_phandle_with_args(node, "assigned-clocks",
196
198
"#clock-cells", index, &clkspec);
···
200
198
return;
201
199
if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
202
200
pr_err("ccm: child clock %d not in ccm\n", index);
201
+
of_node_put(clkspec.np);
203
202
return;
204
203
}
205
204
child = clkspec.args[0];
205
+
of_node_put(clkspec.np);
206
206
207
207
if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
208
208
child != IMX6QDL_CLK_LDB_DI1_SEL)
···
242
238
return false;
243
239
244
240
if (clkspec.np == node &&
245
-
clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
241
+
clkspec.args[0] == IMX6QDL_PLL6_BYPASS) {
242
+
of_node_put(clkspec.np);
246
243
break;
244
+
}
245
+
of_node_put(clkspec.np);
247
246
}
248
247
249
248
/* PLL6 bypass is not part of the assigned clock list */
···
255
248
256
249
ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
257
250
"#clock-cells", index, &clkspec);
251
+
252
+
if (!ret)
253
+
of_node_put(clkspec.np);
258
254
259
255
if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
260
256
return true;
+2
-1
drivers/clk/imx/clk-imx8-acm.c
+2
-1
drivers/clk/imx/clk-imx8-acm.c
···
371
371
for (i = 0; i < priv->soc_data->num_sels; i++) {
372
372
hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev,
373
373
sels[i].name, sels[i].parents,
374
-
sels[i].num_parents, 0,
374
+
sels[i].num_parents,
375
+
CLK_SET_RATE_NO_REPARENT,
375
376
base + sels[i].reg,
376
377
sels[i].shift, sels[i].width,
377
378
0, NULL, NULL);
+2
-2
drivers/clk/imx/clk-imx8mq.c
+2
-2
drivers/clk/imx/clk-imx8mq.c
···
237
237
static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
238
238
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
239
239
240
-
static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
240
+
static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
241
241
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
242
242
243
243
static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
···
246
246
static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
247
247
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
248
248
249
-
static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
249
+
static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
250
250
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
251
251
252
252
static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+3
-3
drivers/clk/imx/clk-pll14xx.c
+3
-3
drivers/clk/imx/clk-pll14xx.c
···
151
151
/* First try if we can get the desired rate from one of the static entries */
152
152
tt = imx_get_pll_settings(pll, rate);
153
153
if (tt) {
154
-
pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n",
154
+
pr_debug("%s: in=%lu, want=%lu, Using PLL setting from table\n",
155
155
clk_hw_get_name(&pll->hw), prate, rate);
156
156
t->rate = tt->rate;
157
157
t->mdiv = tt->mdiv;
···
173
173
174
174
if (rate >= rate_min && rate <= rate_max) {
175
175
kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
176
-
pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n",
176
+
pr_debug("%s: in=%lu, want=%lu Only adjust kdiv %ld -> %d\n",
177
177
clk_hw_get_name(&pll->hw), prate, rate,
178
178
FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv);
179
179
fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
···
211
211
}
212
212
}
213
213
found:
214
-
pr_debug("%s: in=%ld, want=%ld got=%d (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
214
+
pr_debug("%s: in=%lu, want=%lu got=%u (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
215
215
clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,
216
216
t->mdiv, t->kdiv);
217
217
}
+12
drivers/clk/imx/clk-vf610.c
+12
drivers/clk/imx/clk-vf610.c
···
11
11
12
12
#include "clk.h"
13
13
14
+
/*
15
+
* The VF610_CLK_END corresponds to ones defined in
16
+
* include/dt-bindings/clock/vf610-clock.h
17
+
* It shall be the value of the last defined clock +1
18
+
*/
19
+
#define VF610_CLK_END 196
20
+
14
21
#define CCM_CCR (ccm_base + 0x00)
15
22
#define CCM_CSR (ccm_base + 0x04)
16
23
#define CCM_CCSR (ccm_base + 0x08)
···
320
313
clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
321
314
clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
322
315
clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
316
+
clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8));
317
+
clk[VF610_CLK_ESW_MAC_TAB0] = imx_clk_gate2("esw_tab0", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(12));
318
+
clk[VF610_CLK_ESW_MAC_TAB1] = imx_clk_gate2("esw_tab1", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(13));
319
+
clk[VF610_CLK_ESW_MAC_TAB2] = imx_clk_gate2("esw_tab2", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(14));
320
+
clk[VF610_CLK_ESW_MAC_TAB3] = imx_clk_gate2("esw_tab3", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(15));
323
321
324
322
clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
325
323
+7
drivers/clk/rockchip/Kconfig
+7
drivers/clk/rockchip/Kconfig
···
16
16
help
17
17
Build the driver for PX30 Clock Driver.
18
18
19
+
config CLK_RV1103B
20
+
bool "Rockchip RV1103B clock controller support"
21
+
depends on ARM || COMPILE_TEST
22
+
default y
23
+
help
24
+
Build the driver for RV1103B Clock Driver.
25
+
19
26
config CLK_RV110X
20
27
bool "Rockchip RV110x clock controller support"
21
28
depends on ARM || COMPILE_TEST
+1
drivers/clk/rockchip/Makefile
+1
drivers/clk/rockchip/Makefile
···
18
18
clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
19
19
20
20
obj-$(CONFIG_CLK_PX30) += clk-px30.o
21
+
obj-$(CONFIG_CLK_RV1103B) += clk-rv1103b.o
21
22
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
22
23
obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
23
24
obj-$(CONFIG_CLK_RV1126B) += clk-rv1126b.o rst-rv1126b.o
+6
drivers/clk/rockchip/clk-rk3568.c
+6
drivers/clk/rockchip/clk-rk3568.c
···
827
827
RK3568_CLKGATE_CON(12), 3, GFLAGS),
828
828
GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
829
829
RK3568_CLKGATE_CON(12), 4, GFLAGS),
830
+
GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
831
+
RK3568_CLKGATE_CON(12), 5, GFLAGS),
830
832
GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
831
833
RK3568_CLKGATE_CON(12), 8, GFLAGS),
832
834
GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
···
839
837
RK3568_CLKGATE_CON(12), 11, GFLAGS),
840
838
GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
841
839
RK3568_CLKGATE_CON(12), 12, GFLAGS),
840
+
GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
841
+
RK3568_CLKGATE_CON(12), 13, GFLAGS),
842
842
GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
843
843
RK3568_CLKGATE_CON(13), 0, GFLAGS),
844
844
GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
···
851
847
RK3568_CLKGATE_CON(13), 3, GFLAGS),
852
848
GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
853
849
RK3568_CLKGATE_CON(13), 4, GFLAGS),
850
+
GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
851
+
RK3568_CLKGATE_CON(13), 5, GFLAGS),
854
852
GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
855
853
RK3568_CLKGATE_CON(11), 0, GFLAGS),
856
854
GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
+658
drivers/clk/rockchip/clk-rv1103b.c
+658
drivers/clk/rockchip/clk-rv1103b.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
4
+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5
+
*/
6
+
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/of.h>
9
+
#include <linux/of_address.h>
10
+
#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
11
+
#include "clk.h"
12
+
13
+
#define RV1103B_GRF_SOC_STATUS0 0x10
14
+
#define RV1103B_FRAC_MAX_PRATE 1200000000
15
+
#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16))
16
+
17
+
enum rv1103b_plls {
18
+
dpll,
19
+
gpll,
20
+
};
21
+
22
+
static struct rockchip_pll_rate_table rv1103b_pll_rates[] = {
23
+
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
24
+
RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
25
+
RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
26
+
RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
27
+
{ /* sentinel */ },
28
+
};
29
+
30
+
#define RV1103B_DIV_ACLK_CORE_MASK 0x1f
31
+
#define RV1103B_DIV_ACLK_CORE_SHIFT 0
32
+
#define RV1103B_DIV_PCLK_DBG_MASK 0x1f
33
+
#define RV1103B_DIV_PCLK_DBG_SHIFT 8
34
+
35
+
#define RV1103B_CLKSEL0(_aclk_core) \
36
+
{ \
37
+
.reg = RV1103B_CORECLKSEL_CON(2), \
38
+
.val = HIWORD_UPDATE(_aclk_core - 1, RV1103B_DIV_ACLK_CORE_MASK, \
39
+
RV1103B_DIV_ACLK_CORE_SHIFT), \
40
+
}
41
+
42
+
#define RV1103B_CLKSEL1(_pclk_dbg) \
43
+
{ \
44
+
.reg = RV1103B_CORECLKSEL_CON(2), \
45
+
.val = HIWORD_UPDATE(_pclk_dbg - 1, RV1103B_DIV_PCLK_DBG_MASK, \
46
+
RV1103B_DIV_PCLK_DBG_SHIFT), \
47
+
}
48
+
49
+
#define RV1103B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
50
+
{ \
51
+
.prate = _prate, \
52
+
.divs = { \
53
+
RV1103B_CLKSEL0(_aclk_core), \
54
+
RV1103B_CLKSEL1(_pclk_dbg), \
55
+
}, \
56
+
}
57
+
58
+
static struct rockchip_cpuclk_rate_table rv1103b_cpuclk_rates[] __initdata = {
59
+
RV1103B_CPUCLK_RATE(1608000000, 4, 10),
60
+
RV1103B_CPUCLK_RATE(1512000000, 4, 10),
61
+
RV1103B_CPUCLK_RATE(1416000000, 4, 10),
62
+
RV1103B_CPUCLK_RATE(1296000000, 3, 10),
63
+
RV1103B_CPUCLK_RATE(1200000000, 3, 10),
64
+
RV1103B_CPUCLK_RATE(1188000000, 3, 8),
65
+
RV1103B_CPUCLK_RATE(1104000000, 2, 8),
66
+
RV1103B_CPUCLK_RATE(1008000000, 2, 8),
67
+
RV1103B_CPUCLK_RATE(816000000, 2, 6),
68
+
RV1103B_CPUCLK_RATE(600000000, 2, 4),
69
+
RV1103B_CPUCLK_RATE(594000000, 2, 4),
70
+
RV1103B_CPUCLK_RATE(408000000, 1, 3),
71
+
RV1103B_CPUCLK_RATE(396000000, 1, 3),
72
+
};
73
+
74
+
PNAME(mux_pll_p) = { "xin24m" };
75
+
PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_gpll_div12" };
76
+
PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
77
+
PNAME(mux_480m_400m_300m_200m_p) = { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" };
78
+
PNAME(mux_480m_400m_300m_p) = { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4" };
79
+
PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" };
80
+
PNAME(mux_600m_480m_400m_p) = { "clk_gpll_div2", "clk_gpll_div2p5", "clk_gpll_div3" };
81
+
PNAME(mux_400m_300m_p) = { "clk_gpll_div3", "clk_gpll_div4" };
82
+
PNAME(mux_100m_24m_p) = { "clk_gpll_div12", "xin24m" };
83
+
PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" };
84
+
PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_gpll_div12", "clk_gpll_div24", "xin24m" };
85
+
PNAME(mux_300m_200m_100m_p) = { "clk_gpll_div4", "clk_gpll_div6", "clk_gpll_div12" };
86
+
PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
87
+
PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
88
+
PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
89
+
PNAME(mclk_sai_src_p) = { "clk_sai_src", "clk_sai_frac", "mclk_sai_from_io", "xin_osc0_half" };
90
+
PNAME(clk_freq_pwm0_src_p) = { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
91
+
PNAME(clk_counter_pwm0_src_p) = { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
92
+
PNAME(clk_mipi0_out2io_p) = { "clk_ref_mipi0", "xin24m" };
93
+
PNAME(clk_mipi1_out2io_p) = { "clk_ref_mipi1", "xin24m" };
94
+
PNAME(mclk_sai_out2io_p) = { "mclk_sai_src", "xin_osc0_half" };
95
+
PNAME(aclk_npu_root_p) = { "clk_npu_src", "clk_npu_pvtpll" };
96
+
PNAME(clk_core_vepu_p) = { "clk_vepu_src", "clk_vepu_pvtpll" };
97
+
PNAME(lsclk_vi_root_p) = { "clk_gpll_div6", "lsclk_vi_100m" };
98
+
PNAME(clk_core_isp_p) = { "clk_isp_src", "clk_isp_pvtpll_src" };
99
+
PNAME(lsclk_pmu_root_p) = { "xin24m", "clk_rc_osc_io" };
100
+
PNAME(xin_rc_div_p) = { "xin24m", "clk_rc_osc_io" };
101
+
PNAME(clk_32k_p) = { "xin_rc_div", "clk_32k_rtc", "clk_32k_io" };
102
+
PNAME(dbclk_pmu_gpio0_p) = { "xin24m", "clk_32k" };
103
+
PNAME(sclk_sfc_2x_pmu1_p) = { "clk_gpll_div12", "clk_rc_osc_io" };
104
+
PNAME(mux_armclk_p) = { "armclk_gpll", "clk_core_pvtpll" };
105
+
106
+
static struct rockchip_pll_clock rv1103b_pll_clks[] __initdata = {
107
+
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
108
+
CLK_IS_CRITICAL, RV1103B_PLL_CON(16),
109
+
RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
110
+
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
111
+
CLK_IS_CRITICAL, RV1103B_PLL_CON(24),
112
+
RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
113
+
};
114
+
115
+
#define MFLAGS CLK_MUX_HIWORD_MASK
116
+
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
117
+
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
118
+
119
+
static struct rockchip_clk_branch rv1103b_clk_uart0_fracmux __initdata =
120
+
MUX(SCLK_UART0_SRC, "sclk_uart0_src", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
121
+
RV1103B_CLKSEL_CON(32), 8, 2, MFLAGS);
122
+
123
+
static struct rockchip_clk_branch rv1103b_clk_uart1_fracmux __initdata =
124
+
MUX(SCLK_UART1_SRC, "sclk_uart1_src", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
125
+
RV1103B_CLKSEL_CON(32), 10, 2, MFLAGS);
126
+
127
+
static struct rockchip_clk_branch rv1103b_clk_uart2_fracmux __initdata =
128
+
MUX(SCLK_UART2_SRC, "sclk_uart2_src", sclk_uart2_src_p, CLK_SET_RATE_PARENT,
129
+
RV1103B_CLKSEL_CON(32), 12, 2, MFLAGS);
130
+
131
+
static struct rockchip_clk_branch rv1103b_rcdiv_pmu_fracmux __initdata =
132
+
MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
133
+
RK3568_PMU_CLKSEL_CON(0), 0, 2, MFLAGS);
134
+
135
+
static struct rockchip_clk_branch rv1103b_clk_branches[] __initdata = {
136
+
137
+
/* Clock Definition */
138
+
FACTOR(XIN_OSC0_HALF, "xin_osc0_half", "xin24m", 0, 1, 2),
139
+
140
+
COMPOSITE_NOGATE(0, "armclk_gpll", mux_gpll_24m_p, CLK_IS_CRITICAL,
141
+
RV1103B_CLKSEL_CON(37), 12, 1, MFLAGS, 13, 3, DFLAGS),
142
+
143
+
/* pd_top */
144
+
COMPOSITE_NOMUX(CLK_GPLL_DIV24, "clk_gpll_div24", "gpll", 0,
145
+
RV1103B_CLKSEL_CON(0), 0, 5, DFLAGS,
146
+
RV1103B_CLKGATE_CON(0), 0, GFLAGS),
147
+
COMPOSITE_NOMUX(CLK_GPLL_DIV12, "clk_gpll_div12", "gpll", 0,
148
+
RV1103B_CLKSEL_CON(0), 5, 5, DFLAGS,
149
+
RV1103B_CLKGATE_CON(0), 1, GFLAGS),
150
+
COMPOSITE_NOMUX(CLK_GPLL_DIV6, "clk_gpll_div6", "gpll", 0,
151
+
RV1103B_CLKSEL_CON(1), 0, 5, DFLAGS,
152
+
RV1103B_CLKGATE_CON(0), 3, GFLAGS),
153
+
COMPOSITE_NOMUX(CLK_GPLL_DIV4, "clk_gpll_div4", "gpll", 0,
154
+
RV1103B_CLKSEL_CON(1), 10, 5, DFLAGS,
155
+
RV1103B_CLKGATE_CON(0), 5, GFLAGS),
156
+
COMPOSITE_NOMUX(CLK_GPLL_DIV3, "clk_gpll_div3", "gpll", 0,
157
+
RV1103B_CLKSEL_CON(2), 0, 5, DFLAGS,
158
+
RV1103B_CLKGATE_CON(0), 7, GFLAGS),
159
+
COMPOSITE_NOMUX_HALFDIV(CLK_GPLL_DIV2P5, "clk_gpll_div2p5", "gpll", 0,
160
+
RV1103B_CLKSEL_CON(2), 5, 5, DFLAGS,
161
+
RV1103B_CLKGATE_CON(0), 8, GFLAGS),
162
+
COMPOSITE_NOMUX(CLK_GPLL_DIV2, "clk_gpll_div2", "gpll", 0,
163
+
RV1103B_CLKSEL_CON(2), 10, 5, DFLAGS,
164
+
RV1103B_CLKGATE_CON(0), 9, GFLAGS),
165
+
COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0,
166
+
RV1103B_CLKSEL_CON(5), 0, 5, DFLAGS,
167
+
RV1103B_CLKGATE_CON(1), 0, GFLAGS),
168
+
COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0,
169
+
RV1103B_CLKSEL_CON(5), 5, 5, DFLAGS,
170
+
RV1103B_CLKGATE_CON(1), 1, GFLAGS),
171
+
COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0,
172
+
RV1103B_CLKSEL_CON(5), 10, 5, DFLAGS,
173
+
RV1103B_CLKGATE_CON(1), 2, GFLAGS),
174
+
COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", 0,
175
+
RV1103B_CLKSEL_CON(10), 0,
176
+
RV1103B_CLKGATE_CON(1), 6, GFLAGS,
177
+
&rv1103b_clk_uart0_fracmux),
178
+
COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", 0,
179
+
RV1103B_CLKSEL_CON(11), 0,
180
+
RV1103B_CLKGATE_CON(1), 7, GFLAGS,
181
+
&rv1103b_clk_uart1_fracmux),
182
+
COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", 0,
183
+
RV1103B_CLKSEL_CON(12), 0,
184
+
RV1103B_CLKGATE_CON(1), 8, GFLAGS,
185
+
&rv1103b_clk_uart2_fracmux),
186
+
GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_src", 0,
187
+
RV1103B_CLKGATE_CON(3), 3, GFLAGS),
188
+
GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_src", 0,
189
+
RV1103B_CLKGATE_CON(3), 4, GFLAGS),
190
+
GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_src", 0,
191
+
RV1103B_CLKGATE_CON(3), 8, GFLAGS),
192
+
193
+
COMPOSITE_NOMUX(CLK_SAI_SRC, "clk_sai_src", "gpll", 0,
194
+
RV1103B_CLKSEL_CON(20), 0, 5, DFLAGS,
195
+
RV1103B_CLKGATE_CON(1), 12, GFLAGS),
196
+
MUX(MCLK_SAI_SRC, "mclk_sai_src", mclk_sai_src_p, CLK_SET_RATE_PARENT,
197
+
RV1103B_CLKSEL_CON(35), 10, 2, MFLAGS),
198
+
GATE(MCLK_SAI, "mclk_sai", "mclk_sai_src", 0,
199
+
RV1103B_CLKGATE_CON(5), 5, GFLAGS),
200
+
201
+
COMPOSITE_NODIV(LSCLK_NPU_SRC, "lsclk_npu_src", mux_200m_100m_p, CLK_IS_CRITICAL,
202
+
RV1103B_CLKSEL_CON(30), 0, 1, MFLAGS,
203
+
RV1103B_CLKGATE_CON(2), 0, GFLAGS),
204
+
COMPOSITE(CLK_NPU_SRC, "clk_npu_src", mux_gpll_24m_p, 0,
205
+
RV1103B_CLKSEL_CON(37), 0, 1, MFLAGS, 1, 2, DFLAGS,
206
+
RV1103B_CLKGATE_CON(5), 12, GFLAGS),
207
+
COMPOSITE_NODIV(ACLK_VEPU_SRC, "aclk_vepu_src", mux_480m_400m_300m_200m_p, 0,
208
+
RV1103B_CLKSEL_CON(30), 8, 2, MFLAGS,
209
+
RV1103B_CLKGATE_CON(2), 4, GFLAGS),
210
+
COMPOSITE(CLK_VEPU_SRC, "clk_vepu_src", mux_gpll_24m_p, 0,
211
+
RV1103B_CLKSEL_CON(37), 4, 1, MFLAGS, 5, 2, DFLAGS,
212
+
RV1103B_CLKGATE_CON(5), 13, GFLAGS),
213
+
COMPOSITE_NODIV(ACLK_VI_SRC, "aclk_vi_src", mux_480m_400m_300m_p, CLK_IS_CRITICAL,
214
+
RV1103B_CLKSEL_CON(30), 12, 2, MFLAGS,
215
+
RV1103B_CLKGATE_CON(2), 8, GFLAGS),
216
+
COMPOSITE(CLK_ISP_SRC, "clk_isp_src", mux_gpll_24m_p, 0,
217
+
RV1103B_CLKSEL_CON(37), 8, 1, MFLAGS, 9, 2, DFLAGS,
218
+
RV1103B_CLKGATE_CON(5), 14, GFLAGS),
219
+
COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_300m_200m_p, 0,
220
+
RV1103B_CLKSEL_CON(30), 14, 1, MFLAGS,
221
+
RV1103B_CLKGATE_CON(2), 9, GFLAGS),
222
+
COMPOSITE(CCLK_EMMC, "cclk_emmc", mux_gpll_24m_p, 0,
223
+
RV1103B_CLKSEL_CON(31), 15, 1, MFLAGS, 0, 8, DFLAGS,
224
+
RV1103B_CLKGATE_CON(2), 10, GFLAGS),
225
+
COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", mux_gpll_24m_p, 0,
226
+
RV1103B_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 8, DFLAGS,
227
+
RV1103B_CLKGATE_CON(2), 11, GFLAGS),
228
+
COMPOSITE(SCLK_SFC_2X, "sclk_sfc_2x", mux_gpll_24m_p, 0,
229
+
RV1103B_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 8, DFLAGS,
230
+
RV1103B_CLKGATE_CON(2), 12, GFLAGS),
231
+
COMPOSITE_NODIV(LSCLK_PERI_SRC, "lsclk_peri_src", mux_300m_200m_p, CLK_IS_CRITICAL,
232
+
RV1103B_CLKSEL_CON(31), 9, 1, MFLAGS,
233
+
RV1103B_CLKGATE_CON(3), 0, GFLAGS),
234
+
COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_600m_480m_400m_p, CLK_IS_CRITICAL,
235
+
RV1103B_CLKSEL_CON(31), 10, 2, MFLAGS,
236
+
RV1103B_CLKGATE_CON(3), 1, GFLAGS),
237
+
COMPOSITE_NODIV(HCLK_HPMCU, "hclk_hpmcu", mux_400m_300m_p, 0,
238
+
RV1103B_CLKSEL_CON(31), 12, 1, MFLAGS,
239
+
RV1103B_CLKGATE_CON(3), 2, GFLAGS),
240
+
COMPOSITE_NODIV(CLK_I2C_PMU, "clk_i2c_pmu", mux_100m_24m_p, 0,
241
+
RV1103B_CLKSEL_CON(34), 0, 1, MFLAGS,
242
+
RV1103B_CLKGATE_CON(4), 0, GFLAGS),
243
+
COMPOSITE_NODIV(CLK_I2C_PERI, "clk_i2c_peri", mux_200m_24m_p, 0,
244
+
RV1103B_CLKSEL_CON(34), 1, 1, MFLAGS,
245
+
RV1103B_CLKGATE_CON(4), 4, GFLAGS),
246
+
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
247
+
RV1103B_CLKSEL_CON(34), 2, 2, MFLAGS,
248
+
RV1103B_CLKGATE_CON(4), 5, GFLAGS),
249
+
COMPOSITE_NODIV(CLK_PWM0_SRC, "clk_pwm0_src", mux_100m_24m_p, 0,
250
+
RV1103B_CLKSEL_CON(34), 12, 1, MFLAGS,
251
+
RV1103B_CLKGATE_CON(4), 10, GFLAGS),
252
+
COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_24m_p, 0,
253
+
RV1103B_CLKSEL_CON(34), 13, 1, MFLAGS,
254
+
RV1103B_CLKGATE_CON(4), 11, GFLAGS),
255
+
COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_24m_p, 0,
256
+
RV1103B_CLKSEL_CON(34), 14, 1, MFLAGS,
257
+
RV1103B_CLKGATE_CON(4), 12, GFLAGS),
258
+
COMPOSITE_NODIV(DCLK_DECOM_SRC, "dclk_decom_src", mux_480m_400m_300m_p, 0,
259
+
RV1103B_CLKSEL_CON(35), 0, 2, MFLAGS,
260
+
RV1103B_CLKGATE_CON(5), 0, GFLAGS),
261
+
COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", mux_gpll_24m_p, 0,
262
+
RV1103B_CLKSEL_CON(36), 15, 1, MFLAGS, 0, 8, DFLAGS,
263
+
RV1103B_CLKGATE_CON(5), 1, GFLAGS),
264
+
COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_p, 0,
265
+
RV1103B_CLKSEL_CON(35), 2, 2, MFLAGS,
266
+
RV1103B_CLKGATE_CON(5), 2, GFLAGS),
267
+
COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_p, 0,
268
+
RV1103B_CLKSEL_CON(35), 4, 2, MFLAGS,
269
+
RV1103B_CLKGATE_CON(5), 3, GFLAGS),
270
+
COMPOSITE_NODIV(CLK_CORE_RGA, "clk_core_rga", mux_400m_300m_p, 0,
271
+
RV1103B_CLKSEL_CON(35), 8, 1, MFLAGS,
272
+
RV1103B_CLKGATE_CON(5), 4, GFLAGS),
273
+
274
+
GATE(PCLK_TOP_ROOT, "pclk_top_root", "clk_gpll_div12", CLK_IS_CRITICAL,
275
+
RV1103B_CLKGATE_CON(6), 0, GFLAGS),
276
+
COMPOSITE_NOMUX(CLK_REF_MIPI0, "clk_ref_mipi0", "clk_gpll_div2", 0,
277
+
RV1103B_CLKSEL_CON(40), 0, 5, DFLAGS,
278
+
RV1103B_CLKGATE_CON(6), 3, GFLAGS),
279
+
COMPOSITE_NODIV(CLK_MIPI0_OUT2IO, "clk_mipi0_out2io", clk_mipi0_out2io_p, CLK_SET_RATE_PARENT,
280
+
RV1103B_CLKSEL_CON(40), 6, 1, MFLAGS,
281
+
RV1103B_CLKGATE_CON(6), 4, GFLAGS),
282
+
COMPOSITE_NOMUX(CLK_REF_MIPI1, "clk_ref_mipi1", "clk_gpll_div2", 0,
283
+
RV1103B_CLKSEL_CON(40), 8, 5, DFLAGS,
284
+
RV1103B_CLKGATE_CON(6), 5, GFLAGS),
285
+
COMPOSITE_NODIV(CLK_MIPI1_OUT2IO, "clk_mipi1_out2io", clk_mipi1_out2io_p, CLK_SET_RATE_PARENT,
286
+
RV1103B_CLKSEL_CON(40), 14, 1, MFLAGS,
287
+
RV1103B_CLKGATE_CON(6), 6, GFLAGS),
288
+
COMPOSITE(MCLK_SAI_OUT2IO, "mclk_sai_out2io", mclk_sai_out2io_p, 0,
289
+
RV1103B_CLKSEL_CON(41), 7, 1, MFLAGS, 13, 3, DFLAGS,
290
+
RV1103B_CLKGATE_CON(6), 9, GFLAGS),
291
+
292
+
/* pd_vpu */
293
+
COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", aclk_npu_root_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
294
+
RV1103B_NPUCLKSEL_CON(0), 1, 1, MFLAGS,
295
+
RV1103B_NPUCLKGATE_CON(0), 1, GFLAGS),
296
+
GATE(HCLK_RKNN, "hclk_rknn", "lsclk_npu_src", 0,
297
+
RV1103B_NPUCLKGATE_CON(0), 4, GFLAGS),
298
+
GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
299
+
RV1103B_NPUCLKGATE_CON(0), 5, GFLAGS),
300
+
301
+
/* pd_vepu */
302
+
COMPOSITE_NOMUX(LSCLK_VEPU_ROOT, "lsclk_vepu_root", "aclk_vepu_src", CLK_IS_CRITICAL,
303
+
RV1103B_VEPUCLKSEL_CON(0), 2, 2, DFLAGS,
304
+
RV1103B_VEPUCLKGATE_CON(0), 0, GFLAGS),
305
+
GATE(HCLK_VEPU, "hclk_vepu", "lsclk_vepu_root", 0,
306
+
RV1103B_VEPUCLKGATE_CON(0), 4, GFLAGS),
307
+
GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_src", 0,
308
+
RV1103B_VEPUCLKGATE_CON(0), 5, GFLAGS),
309
+
COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", clk_core_vepu_p, 0,
310
+
RV1103B_VEPUCLKSEL_CON(0), 1, 1, MFLAGS,
311
+
RV1103B_VEPUCLKGATE_CON(0), 6, GFLAGS),
312
+
GATE(PCLK_ACODEC, "pclk_acodec", "lsclk_vepu_root", 0,
313
+
RV1103B_VEPUCLKGATE_CON(0), 13, GFLAGS),
314
+
GATE(PCLK_USBPHY, "pclk_usbphy", "lsclk_vepu_root", 0,
315
+
RV1103B_VEPUCLKGATE_CON(0), 14, GFLAGS),
316
+
317
+
/* pd_vi */
318
+
FACTOR(LSCLK_VI_100M, "lsclk_vi_100m", "clk_gpll_div6", 0, 1, 2),
319
+
COMPOSITE_NODIV(LSCLK_VI_ROOT, "lsclk_vi_root", lsclk_vi_root_p, CLK_IS_CRITICAL,
320
+
RV1103B_VICLKSEL_CON(0), 3, 1, MFLAGS,
321
+
RV1103B_VICLKGATE_CON(0), 0, GFLAGS),
322
+
GATE(HCLK_ISP, "hclk_isp", "lsclk_vi_root", 0,
323
+
RV1103B_VICLKGATE_CON(0), 4, GFLAGS),
324
+
GATE(ACLK_ISP, "aclk_isp", "aclk_vi_src", 0,
325
+
RV1103B_VICLKGATE_CON(0), 5, GFLAGS),
326
+
COMPOSITE_NODIV(CLK_CORE_ISP, "clk_core_isp", clk_core_isp_p, 0,
327
+
RV1103B_VICLKSEL_CON(0), 1, 1, MFLAGS,
328
+
RV1103B_VICLKGATE_CON(0), 6, GFLAGS),
329
+
GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_src", 0,
330
+
RV1103B_VICLKGATE_CON(1), 2, GFLAGS),
331
+
GATE(HCLK_VICAP, "hclk_vicap", "lsclk_vi_root", 0,
332
+
RV1103B_VICLKGATE_CON(1), 3, GFLAGS),
333
+
GATE(ISP0CLK_VICAP, "isp0clk_vicap", "clk_core_isp", 0,
334
+
RV1103B_VICLKGATE_CON(1), 8, GFLAGS),
335
+
GATE(PCLK_CSI2HOST0, "pclk_csi2host0", "lsclk_vi_root", 0,
336
+
RV1103B_VICLKGATE_CON(1), 9, GFLAGS),
337
+
GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "lsclk_vi_root", 0,
338
+
RV1103B_VICLKGATE_CON(1), 11, GFLAGS),
339
+
GATE(HCLK_EMMC, "hclk_emmc", "lsclk_vi_root", 0,
340
+
RV1103B_VICLKGATE_CON(1), 13, GFLAGS),
341
+
GATE(HCLK_SFC, "hclk_sfc", "lsclk_vi_root", 0,
342
+
RV1103B_VICLKGATE_CON(1), 14, GFLAGS),
343
+
GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "lsclk_vi_root", 0,
344
+
RV1103B_VICLKGATE_CON(1), 15, GFLAGS),
345
+
GATE(HCLK_SDMMC0, "hclk_sdmmc0", "lsclk_vi_root", 0,
346
+
RV1103B_VICLKGATE_CON(2), 0, GFLAGS),
347
+
GATE(PCLK_CSIPHY, "pclk_csiphy", "lsclk_vi_root", 0,
348
+
RV1103B_VICLKGATE_CON(2), 2, GFLAGS),
349
+
GATE(PCLK_GPIO1, "pclk_gpio1", "lsclk_vi_root", 0,
350
+
RV1103B_VICLKGATE_CON(2), 3, GFLAGS),
351
+
GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
352
+
RV1103B_VICLKGATE_CON(2), 4, GFLAGS),
353
+
354
+
/* pd_ddr */
355
+
GATE(LSCLK_DDR_ROOT, "lsclk_ddr_root", "clk_gpll_div12", CLK_IS_CRITICAL,
356
+
RV1103B_DDRCLKGATE_CON(0), 0, GFLAGS),
357
+
GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
358
+
RV1103B_DDRCLKGATE_CON(0), 4, GFLAGS),
359
+
FACTOR(0, "sclk_ddr", "dpll", 0, 1, 2),
360
+
361
+
/* pd_pmu */
362
+
COMPOSITE(LSCLK_PMU_ROOT, "lsclk_pmu_root", lsclk_pmu_root_p, CLK_IS_CRITICAL,
363
+
RV1103B_PMUCLKSEL_CON(2), 4, 1, MFLAGS, 0, 2, DFLAGS,
364
+
RV1103B_PMUCLKGATE_CON(0), 0, GFLAGS),
365
+
GATE(PCLK_PMU, "pclk_pmu", "lsclk_pmu_root", CLK_IS_CRITICAL,
366
+
RV1103B_PMUCLKGATE_CON(0), 2, GFLAGS),
367
+
MUX(XIN_RC_SRC, "xin_rc_src", xin_rc_div_p, 0,
368
+
RV1103B_PMUCLKSEL_CON(0), 2, 1, MFLAGS),
369
+
COMPOSITE_FRACMUX(XIN_RC_DIV, "xin_rc_div", "xin_rc_src", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
370
+
RV1103B_PMUCLKSEL_CON(1), 0,
371
+
RV1103B_PMUCLKGATE_CON(0), 3, GFLAGS,
372
+
&rv1103b_rcdiv_pmu_fracmux),
373
+
GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "lsclk_pmu_root", 0,
374
+
RV1103B_PMUCLKGATE_CON(0), 4, GFLAGS),
375
+
COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", dbclk_pmu_gpio0_p, 0,
376
+
RK3568_PMU_CLKSEL_CON(0), 3, 1, MFLAGS,
377
+
RV1103B_PMUCLKGATE_CON(0), 5, GFLAGS),
378
+
GATE(PCLK_PWM0, "pclk_pwm0", "lsclk_pmu_root", 0,
379
+
RV1103B_PMUCLKGATE_CON(2), 0, GFLAGS),
380
+
GATE(CLK_PWM0, "clk_pwm0", "clk_pwm0_src", 0,
381
+
RV1103B_PMUCLKGATE_CON(2), 1, GFLAGS),
382
+
GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
383
+
RV1103B_PMUCLKGATE_CON(2), 2, GFLAGS),
384
+
GATE(CLK_RC_PWM0, "clk_rc_pwm0", "clk_32k", 0,
385
+
RV1103B_PMUCLKGATE_CON(2), 3, GFLAGS),
386
+
GATE(PCLK_I2C0, "pclk_i2c0", "lsclk_pmu_root", 0,
387
+
RV1103B_PMUCLKGATE_CON(0), 12, GFLAGS),
388
+
GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_pmu", 0,
389
+
RV1103B_PMUCLKGATE_CON(0), 13, GFLAGS),
390
+
GATE(PCLK_UART0, "pclk_uart0", "lsclk_pmu_root", 0,
391
+
RV1103B_PMUCLKGATE_CON(0), 14, GFLAGS),
392
+
GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
393
+
RV1103B_PMUCLKGATE_CON(1), 4, GFLAGS),
394
+
GATE(CLK_PREROLL, "clk_preroll", "lsclk_pmu_root", 0,
395
+
RV1103B_PMUCLKGATE_CON(1), 6, GFLAGS),
396
+
GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0,
397
+
RV1103B_PMUCLKGATE_CON(1), 7, GFLAGS),
398
+
GATE(CLK_LPMCU_PMU, "clk_lpmcu_pmu", "lsclk_pmu_root", 0,
399
+
RV1103B_PMUCLKGATE_CON(2), 12, GFLAGS),
400
+
401
+
/* pd_pmu1 */
402
+
GATE(PCLK_SPI2AHB, "pclk_spi2ahb", "lsclk_pmu_root", 0,
403
+
RV1103B_PMU1CLKGATE_CON(0), 0, GFLAGS),
404
+
GATE(HCLK_SPI2AHB, "hclk_spi2ahb", "lsclk_pmu_root", 0,
405
+
RV1103B_PMU1CLKGATE_CON(0), 1, GFLAGS),
406
+
GATE(PCLK_WDT_LPMCU, "pclk_wdt_lpmcu", "lsclk_pmu_root", 0,
407
+
RV1103B_PMU1CLKGATE_CON(0), 9, GFLAGS),
408
+
GATE(TCLK_WDT_LPMCU, "tclk_wdt_lpmcu", "xin24m", 0,
409
+
RV1103B_PMU1CLKGATE_CON(0), 10, GFLAGS),
410
+
GATE(HCLK_SFC_PMU1, "hclk_sfc_pmu1", "lsclk_pmu_root", 0,
411
+
RV1103B_PMU1CLKGATE_CON(0), 12, GFLAGS),
412
+
GATE(HCLK_SFC_XIP_PMU1, "hclk_sfc_xip_pmu1", "lsclk_pmu_root", 0,
413
+
RV1103B_PMU1CLKGATE_CON(0), 13, GFLAGS),
414
+
COMPOSITE_NODIV(SCLK_SFC_2X_PMU1, "sclk_sfc_2x_pmu1", sclk_sfc_2x_pmu1_p, 0,
415
+
RV1103B_PMU1CLKSEL_CON(0), 8, 1, MFLAGS,
416
+
RV1103B_PMU1CLKGATE_CON(0), 14, GFLAGS),
417
+
GATE(CLK_LPMCU, "clk_lpmcu", "lsclk_pmu_root", 0,
418
+
RV1103B_PMU1CLKGATE_CON(1), 0, GFLAGS),
419
+
GATE(CLK_LPMCU_RTC, "clk_lpmcu_rtc", "xin24m", 0,
420
+
RV1103B_PMU1CLKGATE_CON(1), 4, GFLAGS),
421
+
GATE(PCLK_LPMCU_MAILBOX, "pclk_lpmcu_mailbox", "lsclk_pmu_root", 0,
422
+
RV1103B_PMU1CLKGATE_CON(1), 8, GFLAGS),
423
+
424
+
/* pd_peri */
425
+
COMPOSITE_NOMUX(PCLK_PERI_ROOT, "pclk_peri_root", "lsclk_peri_src", CLK_IS_CRITICAL,
426
+
RV1103B_PERICLKSEL_CON(0), 0, 2, DFLAGS,
427
+
RV1103B_PERICLKGATE_CON(0), 0, GFLAGS),
428
+
COMPOSITE_NOMUX(PCLK_RTC_ROOT, "pclk_rtc_root", "lsclk_peri_src", CLK_IS_CRITICAL,
429
+
RV1103B_PERICLKSEL_CON(2), 12, 4, DFLAGS,
430
+
RV1103B_PERICLKGATE_CON(0), 8, GFLAGS),
431
+
GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
432
+
RV1103B_PERICLKGATE_CON(0), 1, GFLAGS),
433
+
GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
434
+
RV1103B_PERICLKGATE_CON(1), 0, GFLAGS),
435
+
GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
436
+
RV1103B_PERICLKGATE_CON(1), 1, GFLAGS),
437
+
GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
438
+
RV1103B_PERICLKGATE_CON(1), 2, GFLAGS),
439
+
GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
440
+
RV1103B_PERICLKGATE_CON(1), 3, GFLAGS),
441
+
GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
442
+
RV1103B_PERICLKGATE_CON(1), 4, GFLAGS),
443
+
GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
444
+
RV1103B_PERICLKGATE_CON(1), 5, GFLAGS),
445
+
GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
446
+
RV1103B_PERICLKGATE_CON(1), 6, GFLAGS),
447
+
GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
448
+
RV1103B_PERICLKGATE_CON(1), 7, GFLAGS),
449
+
GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
450
+
RV1103B_PERICLKGATE_CON(1), 8, GFLAGS),
451
+
GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
452
+
RV1103B_PERICLKGATE_CON(1), 9, GFLAGS),
453
+
GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
454
+
RV1103B_PERICLKGATE_CON(2), 0, GFLAGS),
455
+
GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
456
+
RV1103B_PERICLKGATE_CON(2), 1, GFLAGS),
457
+
GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
458
+
RV1103B_PERICLKGATE_CON(2), 2, GFLAGS),
459
+
GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
460
+
RV1103B_PERICLKGATE_CON(2), 3, GFLAGS),
461
+
GATE(PCLK_WDT_HPMCU, "pclk_wdt_hpmcu", "pclk_peri_root", 0,
462
+
RV1103B_PERICLKGATE_CON(2), 4, GFLAGS),
463
+
GATE(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", "xin24m", 0,
464
+
RV1103B_PERICLKGATE_CON(2), 5, GFLAGS),
465
+
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri_root", 0,
466
+
RV1103B_PERICLKGATE_CON(2), 6, GFLAGS),
467
+
GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_peri", 0,
468
+
RV1103B_PERICLKGATE_CON(2), 7, GFLAGS),
469
+
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
470
+
RV1103B_PERICLKGATE_CON(2), 8, GFLAGS),
471
+
GATE(CLK_I2C2, "clk_i2c2", "clk_i2c_peri", 0,
472
+
RV1103B_PERICLKGATE_CON(2), 9, GFLAGS),
473
+
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
474
+
RV1103B_PERICLKGATE_CON(2), 10, GFLAGS),
475
+
GATE(CLK_I2C3, "clk_i2c3", "clk_i2c_peri", 0,
476
+
RV1103B_PERICLKGATE_CON(2), 11, GFLAGS),
477
+
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
478
+
RV1103B_PERICLKGATE_CON(2), 12, GFLAGS),
479
+
GATE(CLK_I2C4, "clk_i2c4", "clk_i2c_peri", 0,
480
+
RV1103B_PERICLKGATE_CON(2), 13, GFLAGS),
481
+
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri_root", 0,
482
+
RV1103B_PERICLKGATE_CON(3), 10, GFLAGS),
483
+
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_peri_root", 0,
484
+
RV1103B_PERICLKGATE_CON(4), 6, GFLAGS),
485
+
GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
486
+
RV1103B_PERICLKGATE_CON(4), 8, GFLAGS),
487
+
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_peri_root", 0,
488
+
RV1103B_PERICLKGATE_CON(4), 12, GFLAGS),
489
+
GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
490
+
RV1103B_PERICLKGATE_CON(4), 13, GFLAGS),
491
+
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
492
+
RV1103B_PERICLKGATE_CON(3), 0, GFLAGS),
493
+
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
494
+
RV1103B_PERICLKGATE_CON(3), 2, GFLAGS),
495
+
GATE(ACLK_RKDMA, "aclk_rkdma", "lsclk_peri_src", 0,
496
+
RV1103B_PERICLKGATE_CON(5), 8, GFLAGS),
497
+
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri_root", 0,
498
+
RV1103B_PERICLKGATE_CON(5), 9, GFLAGS),
499
+
COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
500
+
RV1103B_PERICLKSEL_CON(0), 4, 5, DFLAGS,
501
+
RV1103B_PERICLKGATE_CON(5), 10, GFLAGS),
502
+
COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
503
+
RV1103B_PERICLKSEL_CON(0), 10, 5, DFLAGS,
504
+
RV1103B_PERICLKGATE_CON(5), 11, GFLAGS),
505
+
GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
506
+
RV1103B_PERICLKGATE_CON(5), 12, GFLAGS),
507
+
COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
508
+
RV1103B_PERICLKSEL_CON(1), 0, 3, DFLAGS,
509
+
RV1103B_PERICLKGATE_CON(5), 13, GFLAGS),
510
+
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri_root", 0,
511
+
RV1103B_PERICLKGATE_CON(6), 3, GFLAGS),
512
+
GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
513
+
RV1103B_PERICLKGATE_CON(6), 4, GFLAGS),
514
+
GATE(ACLK_USBOTG, "aclk_usbotg", "lsclk_peri_src", 0,
515
+
RV1103B_PERICLKGATE_CON(6), 9, GFLAGS),
516
+
GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
517
+
RV1103B_PERICLKGATE_CON(6), 10, GFLAGS),
518
+
GATE(HCLK_SDMMC1, "hclk_sdmmc1", "lsclk_peri_src", 0,
519
+
RV1103B_PERICLKGATE_CON(7), 0, GFLAGS),
520
+
GATE(HCLK_SAI, "hclk_sai", "lsclk_peri_src", 0,
521
+
RV1103B_PERICLKGATE_CON(7), 1, GFLAGS),
522
+
GATE(ACLK_CRYPTO, "aclk_crypto", "lsclk_peri_src", 0,
523
+
RV1103B_PERICLKGATE_CON(8), 2, GFLAGS),
524
+
GATE(HCLK_CRYPTO, "hclk_crypto", "lsclk_peri_src", 0,
525
+
RV1103B_PERICLKGATE_CON(8), 3, GFLAGS),
526
+
GATE(HCLK_RK_RNG_S, "hclk_rk_rng_s", "lsclk_peri_src", 0,
527
+
RV1103B_PERICLKGATE_CON(8), 5, GFLAGS),
528
+
GATE(HCLK_RK_RNG_NS, "hclk_rk_rng_ns", "hclk_rk_rng_s", 0,
529
+
RV1103B_PERICLKGATE_CON(8), 4, GFLAGS),
530
+
GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri_root", 0,
531
+
RV1103B_PERICLKGATE_CON(8), 6, GFLAGS),
532
+
GATE(CLK_OTPC_ROOT_NS, "clk_otpc_root_ns", "xin24m", 0,
533
+
RV1103B_PERICLKGATE_CON(8), 7, GFLAGS),
534
+
GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "clk_otpc_root_ns", 0,
535
+
RV1103B_PERICLKGATE_CON(8), 8, GFLAGS),
536
+
COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_otpc_root_ns", 0,
537
+
RV1103B_PERICLKSEL_CON(1), 4, 3, DFLAGS,
538
+
RV1103B_PERICLKGATE_CON(8), 9, GFLAGS),
539
+
GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri_root", 0,
540
+
RV1103B_PERICLKGATE_CON(8), 10, GFLAGS),
541
+
GATE(CLK_OTPC_ROOT_S, "clk_otpc_root_s", "xin24m", 0,
542
+
RV1103B_PERICLKGATE_CON(8), 11, GFLAGS),
543
+
GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "clk_otpc_root_s", 0,
544
+
RV1103B_PERICLKGATE_CON(8), 12, GFLAGS),
545
+
COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "clk_otpc_root_s", 0,
546
+
RV1103B_PERICLKSEL_CON(1), 8, 3, DFLAGS,
547
+
RV1103B_PERICLKGATE_CON(8), 13, GFLAGS),
548
+
GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_peri_root", 0,
549
+
RV1103B_PERICLKGATE_CON(8), 15, GFLAGS),
550
+
GATE(HCLK_RGA, "hclk_rga", "lsclk_peri_src", 0,
551
+
RV1103B_PERICLKGATE_CON(9), 0, GFLAGS),
552
+
GATE(ACLK_RGA, "aclk_rga", "aclk_peri_src", 0,
553
+
RV1103B_PERICLKGATE_CON(9), 1, GFLAGS),
554
+
GATE(ACLK_MAC, "aclk_mac", "lsclk_peri_src", 0,
555
+
RV1103B_PERICLKGATE_CON(9), 3, GFLAGS),
556
+
GATE(PCLK_MAC, "pclk_mac", "pclk_peri_root", 0,
557
+
RV1103B_PERICLKGATE_CON(9), 4, GFLAGS),
558
+
GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
559
+
RV1103B_PERICLKGATE_CON(9), 11, GFLAGS),
560
+
GATE(ACLK_SPINLOCK, "aclk_spinlock", "lsclk_peri_src", 0,
561
+
RV1103B_PERICLKGATE_CON(10), 0, GFLAGS),
562
+
GATE(HCLK_CACHE, "hclk_cache", "hclk_hpmcu", 0,
563
+
RV1103B_PERICLKGATE_CON(10), 1, GFLAGS),
564
+
GATE(PCLK_HPMCU_MAILBOX, "pclk_hpmcu_mailbox", "pclk_peri_root", 0,
565
+
RV1103B_PERICLKGATE_CON(10), 2, GFLAGS),
566
+
GATE(PCLK_HPMCU_INTMUX, "pclk_hpmcu_intmux", "pclk_peri_root", 0,
567
+
RV1103B_PERICLKGATE_CON(10), 3, GFLAGS),
568
+
GATE(CLK_HPMCU, "clk_hpmcu", "hclk_hpmcu", 0,
569
+
RV1103B_PERICLKGATE_CON(10), 4, GFLAGS),
570
+
GATE(CLK_HPMCU_RTC, "clk_hpmcu_rtc", "xin24m", 0,
571
+
RV1103B_PERICLKGATE_CON(10), 8, GFLAGS),
572
+
GATE(DCLK_DECOM, "dclk_decom", "dclk_decom_src", 0,
573
+
RV1103B_PERICLKGATE_CON(11), 0, GFLAGS),
574
+
GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_src", 0,
575
+
RV1103B_PERICLKGATE_CON(11), 1, GFLAGS),
576
+
GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
577
+
RV1103B_PERICLKGATE_CON(11), 2, GFLAGS),
578
+
GATE(ACLK_SYS_SRAM, "aclk_sys_sram", "lsclk_peri_src", CLK_IS_CRITICAL,
579
+
RV1103B_PERICLKGATE_CON(11), 3, GFLAGS),
580
+
GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_peri_root", 0,
581
+
RV1103B_PERICLKGATE_CON(11), 4, GFLAGS),
582
+
GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_peri_src", 0,
583
+
RV1103B_PERICLKGATE_CON(11), 5, GFLAGS),
584
+
GATE(PCLK_DCF, "pclk_dcf", "pclk_peri_root", 0,
585
+
RV1103B_PERICLKGATE_CON(11), 6, GFLAGS),
586
+
GATE(ACLK_DCF, "aclk_dcf", "lsclk_peri_src", 0,
587
+
RV1103B_PERICLKGATE_CON(11), 7, GFLAGS),
588
+
COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_sai_src", 0,
589
+
RV1103B_PERICLKSEL_CON(2), 0, 3, DFLAGS,
590
+
RV1103B_PERICLKGATE_CON(11), 9, GFLAGS),
591
+
GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
592
+
RV1103B_PERICLKGATE_CON(11), 12, GFLAGS),
593
+
594
+
/* io */
595
+
COMPOSITE_NODIV(CLK_FREQ_PWM0_SRC, "clk_freq_pwm0_src", clk_freq_pwm0_src_p, 0,
596
+
RV1103B_CLKSEL_CON(35), 12, 2, MFLAGS,
597
+
RV1103B_CLKGATE_CON(5), 6, GFLAGS),
598
+
GATE(CLK_FREQ_PWM0, "clk_freq_pwm0", "clk_freq_pwm0_src", 0,
599
+
RV1103B_PMUCLKGATE_CON(2), 4, GFLAGS),
600
+
COMPOSITE_NODIV(CLK_COUNTER_PWM0_SRC, "clk_counter_pwm0_src", clk_counter_pwm0_src_p, 0,
601
+
RV1103B_CLKSEL_CON(35), 14, 2, MFLAGS,
602
+
RV1103B_CLKGATE_CON(5), 7, GFLAGS),
603
+
GATE(CLK_COUNTER_PWM0, "clk_counter_pwm0", "clk_counter_pwm0_src", 0,
604
+
RV1103B_PMUCLKGATE_CON(2), 5, GFLAGS),
605
+
GATE(SCLK_SPI2AHB, "sclk_spi2ahb", "sclk_spi2ahb_io", 0,
606
+
RV1103B_PMU1CLKGATE_CON(0), 2, GFLAGS),
607
+
GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
608
+
RV1103B_PERICRU_IP_CON, 14, GFLAGS),
609
+
};
610
+
611
+
static struct rockchip_clk_branch rv1103b_armclk __initdata =
612
+
MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
613
+
RV1103B_CORECLKSEL_CON(0), 1, 1, MFLAGS);
614
+
615
+
static void __init rv1103b_clk_init(struct device_node *np)
616
+
{
617
+
struct rockchip_clk_provider *ctx;
618
+
unsigned long clk_nr;
619
+
void __iomem *reg_base;
620
+
621
+
clk_nr = rockchip_clk_find_max_clk_id(rv1103b_clk_branches,
622
+
ARRAY_SIZE(rv1103b_clk_branches)) + 1;
623
+
reg_base = of_iomap(np, 0);
624
+
if (!reg_base) {
625
+
pr_err("%s: could not map cru region\n", __func__);
626
+
return;
627
+
}
628
+
629
+
ctx = rockchip_clk_init(np, reg_base, clk_nr);
630
+
if (IS_ERR(ctx)) {
631
+
pr_err("%s: rockchip clk init failed\n", __func__);
632
+
iounmap(reg_base);
633
+
return;
634
+
}
635
+
636
+
rockchip_clk_register_plls(ctx, rv1103b_pll_clks,
637
+
ARRAY_SIZE(rv1103b_pll_clks),
638
+
RV1103B_GRF_SOC_STATUS0);
639
+
640
+
rockchip_clk_register_branches(ctx, rv1103b_clk_branches,
641
+
ARRAY_SIZE(rv1103b_clk_branches));
642
+
643
+
rockchip_clk_register_armclk_multi_pll(ctx, &rv1103b_armclk,
644
+
rv1103b_cpuclk_rates,
645
+
ARRAY_SIZE(rv1103b_cpuclk_rates));
646
+
647
+
rockchip_register_restart_notifier(ctx, RV1103B_GLB_SRST_FST, NULL);
648
+
649
+
rockchip_clk_of_add_provider(np, ctx);
650
+
651
+
/* pvtpll src init */
652
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_CORECLKSEL_CON(0));
653
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_NPUCLKSEL_CON(0));
654
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_VICLKSEL_CON(0));
655
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_VEPUCLKSEL_CON(0));
656
+
}
657
+
658
+
CLK_OF_DECLARE(rv1103b_cru, "rockchip,rv1103b-cru", rv1103b_clk_init);
+49
drivers/clk/rockchip/clk.h
+49
drivers/clk/rockchip/clk.h
···
66
66
#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
67
67
#define PX30_PMU_MODE 0x0020
68
68
69
+
#define RV1103B_TOPCRU_BASE 0x60000
70
+
#define RV1103B_PERICRU_BASE 0x0
71
+
#define RV1103B_VICRU_BASE 0x30000
72
+
#define RV1103B_NPUCRU_BASE 0x20000
73
+
#define RV1103B_CORECRU_BASE 0x40000
74
+
#define RV1103B_VEPUCRU_BASE 0x10000
75
+
#define RV1103B_DDRCRU_BASE 0x50000
76
+
#define RV1103B_SUBDDRCRU_BASE 0x58000
77
+
#define RV1103B_PMUCRU_BASE 0x70000
78
+
#define RV1103B_PMU1CRU_BASE 0x80000
79
+
80
+
#define RV1103B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMUCRU_BASE)
81
+
#define RV1103B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMUCRU_BASE)
82
+
#define RV1103B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMUCRU_BASE)
83
+
#define RV1103B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMU1CRU_BASE)
84
+
#define RV1103B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMU1CRU_BASE)
85
+
#define RV1103B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMU1CRU_BASE)
86
+
#define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE)
87
+
#define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE)
88
+
#define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)
89
+
#define RV1103B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_TOPCRU_BASE)
90
+
#define RV1103B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_TOPCRU_BASE)
91
+
#define RV1103B_GLB_SRST_FST (0xc08 + RV1103B_TOPCRU_BASE)
92
+
#define RV1103B_GLB_SRST_SND (0xc0c + RV1103B_TOPCRU_BASE)
93
+
#define RV1103B_CLK_SAI_FRAC_DIV_HIGH (0xcc0 + RV1103B_TOPCRU_BASE)
94
+
#define RV1103B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PERICRU_BASE)
95
+
#define RV1103B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PERICRU_BASE)
96
+
#define RV1103B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PERICRU_BASE)
97
+
#define RV1103B_PERICRU_IP_CON (0xc08 + RV1103B_PERICRU_BASE)
98
+
#define RV1103B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VICRU_BASE)
99
+
#define RV1103B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VICRU_BASE)
100
+
#define RV1103B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VICRU_BASE)
101
+
#define RV1103B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_NPUCRU_BASE)
102
+
#define RV1103B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_NPUCRU_BASE)
103
+
#define RV1103B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_NPUCRU_BASE)
104
+
#define RV1103B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_CORECRU_BASE)
105
+
#define RV1103B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_CORECRU_BASE)
106
+
#define RV1103B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_CORECRU_BASE)
107
+
#define RV1103B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VEPUCRU_BASE)
108
+
#define RV1103B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VEPUCRU_BASE)
109
+
#define RV1103B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VEPUCRU_BASE)
110
+
#define RV1103B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_DDRCRU_BASE)
111
+
#define RV1103B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_DDRCRU_BASE)
112
+
#define RV1103B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_DDRCRU_BASE)
113
+
#define RV1103B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_SUBDDRCRU_BASE)
114
+
#define RV1103B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_SUBDDRCRU_BASE)
115
+
#define RV1103B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_SUBDDRCRU_BASE)
116
+
#define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE)
117
+
69
118
#define RV1108_PLL_CON(x) ((x) * 0x4)
70
119
#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
71
120
#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
+16
-1
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
+16
-1
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
···
83
83
static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
84
84
&r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
85
85
86
-
/* SPI clock is /M/N (same as new MMC?) */
86
+
static const struct clk_parent_data r_spi_parents[] = {
87
+
{ .fw_name = "hosc" },
88
+
{ .fw_name = "pll-periph" },
89
+
{ .name = "pll-periph0-300M" },
90
+
{ .name = "pll-periph1-300M" },
91
+
{ .name = "pll-audio" },
92
+
};
93
+
static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
94
+
0, 5, /* M */
95
+
8, 5, /* P */
96
+
24, 3, /* mux */
97
+
BIT(31), /* gate */
98
+
0);
87
99
static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
88
100
&r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
101
+
89
102
static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
90
103
&r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
91
104
static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",
···
151
138
&bus_r_twd_clk.common,
152
139
&r_pwmctrl_clk.common,
153
140
&bus_r_pwmctrl_clk.common,
141
+
&r_spi_clk.common,
154
142
&bus_r_spi_clk.common,
155
143
&bus_r_spinlock_clk.common,
156
144
&bus_r_msgbox_clk.common,
···
183
169
[CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
184
170
[CLK_R_PWMCTRL] = &r_pwmctrl_clk.common.hw,
185
171
[CLK_BUS_R_PWMCTRL] = &bus_r_pwmctrl_clk.common.hw,
172
+
[CLK_R_SPI] = &r_spi_clk.common.hw,
186
173
[CLK_BUS_R_SPI] = &bus_r_spi_clk.common.hw,
187
174
[CLK_BUS_R_SPINLOCK] = &bus_r_spinlock_clk.common.hw,
188
175
[CLK_BUS_R_MSGBOX] = &bus_r_msgbox_clk.common.hw,
+14
drivers/clk/tenstorrent/Kconfig
+14
drivers/clk/tenstorrent/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
config TENSTORRENT_ATLANTIS_PRCM
4
+
tristate "Support for Tenstorrent Atlantis PRCM Clock Controller"
5
+
depends on ARCH_TENSTORRENT || COMPILE_TEST
6
+
default ARCH_TENSTORRENT
7
+
select REGMAP_MMIO
8
+
select AUXILIARY_BUS
9
+
select MFD_SYSCON
10
+
help
11
+
Say yes here to support the different clock
12
+
controllers found in the Tenstorrent Atlantis SoC.
13
+
This includes the clocks from the RCPU, HSIO, MMIO
14
+
and PCIE domain.
+3
drivers/clk/tenstorrent/Makefile
+3
drivers/clk/tenstorrent/Makefile
+870
drivers/clk/tenstorrent/atlantis-prcm.c
+870
drivers/clk/tenstorrent/atlantis-prcm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Tenstorrent Atlantis PRCM Clock Driver
4
+
*
5
+
* Copyright (c) 2026 Tenstorrent
6
+
*/
7
+
8
+
#include <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h>
9
+
#include <linux/auxiliary_bus.h>
10
+
#include <linux/bitfield.h>
11
+
#include <linux/clk-provider.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/regmap.h>
14
+
#include <linux/slab.h>
15
+
16
+
/* RCPU Clock Register Offsets */
17
+
#define PLL_RCPU_CFG_REG 0x0000
18
+
#define PLL_NOCC_CFG_REG 0x0004
19
+
#define NOCC_CLK_CFG_REG 0x0008
20
+
#define RCPU_DIV_CFG_REG 0x000C
21
+
#define RCPU_BLK_CG_REG 0x0014
22
+
#define LSIO_BLK_CG_REG 0x0018
23
+
#define PLL_RCPU_EN_REG 0x011C
24
+
#define PLL_NOCC_EN_REG 0x0120
25
+
#define BUS_CG_REG 0x01FC
26
+
27
+
/* PLL Bit Definitions */
28
+
#define PLL_CFG_EN_BIT BIT(0)
29
+
#define PLL_CFG_BYPASS_BIT BIT(1)
30
+
#define PLL_CFG_REFDIV_MASK GENMASK(7, 2)
31
+
#define PLL_CFG_REFDIV_SHIFT 2
32
+
#define PLL_CFG_POSTDIV1_MASK GENMASK(10, 8)
33
+
#define PLL_CFG_POSTDIV1_SHIFT 8
34
+
#define PLL_CFG_POSTDIV2_MASK GENMASK(13, 11)
35
+
#define PLL_CFG_POSTDIV2_SHIFT 11
36
+
#define PLL_CFG_FBDIV_MASK GENMASK(25, 14)
37
+
#define PLL_CFG_FBDIV_SHIFT 14
38
+
#define PLL_CFG_LKDT_BIT BIT(30)
39
+
#define PLL_CFG_LOCK_BIT BIT(31)
40
+
#define PLL_LOCK_TIMEOUT_US 1000
41
+
#define PLL_BYPASS_WAIT_US 500
42
+
43
+
struct atlantis_clk_common {
44
+
int clkid;
45
+
struct regmap *regmap;
46
+
struct clk_hw hw;
47
+
};
48
+
49
+
static inline struct atlantis_clk_common *
50
+
hw_to_atlantis_clk_common(struct clk_hw *hw)
51
+
{
52
+
return container_of(hw, struct atlantis_clk_common, hw);
53
+
}
54
+
55
+
struct atlantis_clk_mux_config {
56
+
u8 shift;
57
+
u8 width;
58
+
u32 reg_offset;
59
+
};
60
+
61
+
struct atlantis_clk_mux {
62
+
struct atlantis_clk_common common;
63
+
struct atlantis_clk_mux_config config;
64
+
};
65
+
66
+
struct atlantis_clk_gate_config {
67
+
u32 reg_offset;
68
+
u32 enable;
69
+
};
70
+
71
+
struct atlantis_clk_gate {
72
+
struct atlantis_clk_common common;
73
+
struct atlantis_clk_gate_config config;
74
+
};
75
+
76
+
struct atlantis_clk_divider_config {
77
+
u8 shift;
78
+
u8 width;
79
+
u32 flags;
80
+
u32 reg_offset;
81
+
};
82
+
83
+
struct atlantis_clk_divider {
84
+
struct atlantis_clk_common common;
85
+
struct atlantis_clk_divider_config config;
86
+
};
87
+
88
+
struct atlantis_clk_pll_config {
89
+
u32 tbl_num;
90
+
u32 reg_offset;
91
+
u32 en_reg_offset;
92
+
u32 cg_reg_offset;
93
+
u32 cg_reg_enable;
94
+
};
95
+
96
+
/* Models a PLL with Bypass Functionality and Enable Bit + an optional Gate Clock at it's output */
97
+
struct atlantis_clk_pll {
98
+
struct atlantis_clk_common common;
99
+
struct atlantis_clk_pll_config config;
100
+
};
101
+
102
+
struct atlantis_clk_gate_shared_config {
103
+
u32 reg_offset;
104
+
u32 enable;
105
+
unsigned int *share_count;
106
+
spinlock_t *refcount_lock;
107
+
};
108
+
109
+
struct atlantis_clk_gate_shared {
110
+
struct atlantis_clk_common common;
111
+
struct atlantis_clk_gate_shared_config config;
112
+
};
113
+
114
+
struct atlantis_clk_fixed_factor_config {
115
+
unsigned int mult;
116
+
unsigned int div;
117
+
};
118
+
119
+
struct atlantis_clk_fixed_factor {
120
+
struct atlantis_clk_fixed_factor_config config;
121
+
struct atlantis_clk_common common;
122
+
};
123
+
124
+
static inline struct atlantis_clk_mux *hw_to_atlantis_clk_mux(struct clk_hw *hw)
125
+
{
126
+
struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
127
+
128
+
return container_of(common, struct atlantis_clk_mux, common);
129
+
}
130
+
131
+
static inline struct atlantis_clk_gate *
132
+
hw_to_atlantis_clk_gate(struct clk_hw *hw)
133
+
{
134
+
struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
135
+
136
+
return container_of(common, struct atlantis_clk_gate, common);
137
+
}
138
+
139
+
static inline struct atlantis_clk_divider *
140
+
hw_to_atlantis_clk_divider(struct clk_hw *hw)
141
+
{
142
+
struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
143
+
144
+
return container_of(common, struct atlantis_clk_divider, common);
145
+
}
146
+
147
+
static inline struct atlantis_clk_pll *hw_to_atlantis_pll(struct clk_hw *hw)
148
+
{
149
+
struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
150
+
151
+
return container_of(common, struct atlantis_clk_pll, common);
152
+
}
153
+
154
+
static inline struct atlantis_clk_gate_shared *
155
+
hw_to_atlantis_clk_gate_shared(struct clk_hw *hw)
156
+
{
157
+
struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
158
+
159
+
return container_of(common, struct atlantis_clk_gate_shared, common);
160
+
}
161
+
162
+
static inline struct atlantis_clk_fixed_factor *
163
+
hw_to_atlantis_clk_fixed_factor(struct clk_hw *hw)
164
+
{
165
+
struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
166
+
167
+
return container_of(common, struct atlantis_clk_fixed_factor, common);
168
+
}
169
+
170
+
static u8 atlantis_clk_mux_get_parent(struct clk_hw *hw)
171
+
{
172
+
struct atlantis_clk_mux *mux = hw_to_atlantis_clk_mux(hw);
173
+
u32 val;
174
+
175
+
regmap_read(mux->common.regmap, mux->config.reg_offset, &val);
176
+
val >>= mux->config.shift;
177
+
val &= (BIT(mux->config.width) - 1);
178
+
179
+
return val;
180
+
}
181
+
182
+
static int atlantis_clk_mux_set_parent(struct clk_hw *hw, u8 index)
183
+
{
184
+
struct atlantis_clk_mux *mux = hw_to_atlantis_clk_mux(hw);
185
+
u32 val = index;
186
+
187
+
return regmap_update_bits(mux->common.regmap, mux->config.reg_offset,
188
+
(BIT(mux->config.width) - 1) << mux->config.shift,
189
+
val << mux->config.shift);
190
+
}
191
+
192
+
static int atlantis_clk_mux_determine_rate(struct clk_hw *hw,
193
+
struct clk_rate_request *req)
194
+
{
195
+
return clk_mux_determine_rate_flags(hw, req, hw->init->flags);
196
+
}
197
+
198
+
static const struct clk_ops atlantis_clk_mux_ops = {
199
+
.get_parent = atlantis_clk_mux_get_parent,
200
+
.set_parent = atlantis_clk_mux_set_parent,
201
+
.determine_rate = atlantis_clk_mux_determine_rate,
202
+
};
203
+
204
+
static int atlantis_clk_gate_endisable(struct clk_hw *hw, int enable)
205
+
{
206
+
struct atlantis_clk_gate *gate = hw_to_atlantis_clk_gate(hw);
207
+
208
+
if (enable)
209
+
return regmap_set_bits(gate->common.regmap,
210
+
gate->config.reg_offset,
211
+
gate->config.enable);
212
+
else
213
+
return regmap_clear_bits(gate->common.regmap,
214
+
gate->config.reg_offset,
215
+
gate->config.enable);
216
+
}
217
+
218
+
static int atlantis_clk_gate_enable(struct clk_hw *hw)
219
+
{
220
+
return atlantis_clk_gate_endisable(hw, 1);
221
+
}
222
+
223
+
static void atlantis_clk_gate_disable(struct clk_hw *hw)
224
+
{
225
+
atlantis_clk_gate_endisable(hw, 0);
226
+
}
227
+
228
+
static int atlantis_clk_gate_is_enabled(struct clk_hw *hw)
229
+
{
230
+
struct atlantis_clk_gate *gate = hw_to_atlantis_clk_gate(hw);
231
+
232
+
return regmap_test_bits(gate->common.regmap, gate->config.reg_offset, gate->config.enable);
233
+
}
234
+
235
+
static const struct clk_ops atlantis_clk_gate_ops = {
236
+
.enable = atlantis_clk_gate_enable,
237
+
.disable = atlantis_clk_gate_disable,
238
+
.is_enabled = atlantis_clk_gate_is_enabled,
239
+
};
240
+
241
+
static unsigned long atlantis_clk_divider_recalc_rate(struct clk_hw *hw,
242
+
unsigned long parent_rate)
243
+
{
244
+
struct atlantis_clk_divider *divider = hw_to_atlantis_clk_divider(hw);
245
+
u32 val;
246
+
247
+
regmap_read(divider->common.regmap, divider->config.reg_offset, &val);
248
+
249
+
val >>= divider->config.shift;
250
+
val &= ((1 << (divider->config.width)) - 1);
251
+
252
+
return DIV_ROUND_UP_ULL((u64)parent_rate, val + 1);
253
+
}
254
+
255
+
static const struct clk_ops atlantis_clk_divider_ops = {
256
+
.recalc_rate = atlantis_clk_divider_recalc_rate,
257
+
};
258
+
259
+
static unsigned long
260
+
atlantis_clk_fixed_factor_recalc_rate(struct clk_hw *hw,
261
+
unsigned long parent_rate)
262
+
{
263
+
struct atlantis_clk_fixed_factor *factor =
264
+
hw_to_atlantis_clk_fixed_factor(hw);
265
+
unsigned long long rate;
266
+
267
+
rate = (unsigned long long)parent_rate * factor->config.mult;
268
+
do_div(rate, factor->config.div);
269
+
270
+
return (unsigned long)rate;
271
+
}
272
+
273
+
static const struct clk_ops atlantis_clk_fixed_factor_ops = {
274
+
.recalc_rate = atlantis_clk_fixed_factor_recalc_rate,
275
+
};
276
+
277
+
static int atlantis_clk_pll_is_enabled(struct clk_hw *hw)
278
+
{
279
+
struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
280
+
u32 val, en_val, cg_val;
281
+
282
+
regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
283
+
regmap_read(pll->common.regmap, pll->config.en_reg_offset, &en_val);
284
+
regmap_read(pll->common.regmap, pll->config.cg_reg_offset, &cg_val);
285
+
286
+
/* Check if PLL is powered on, locked, not bypassed and Gate clk is enabled */
287
+
return !!(en_val & PLL_CFG_EN_BIT) && !!(val & PLL_CFG_LOCK_BIT) &&
288
+
(!pll->config.cg_reg_enable || (cg_val & pll->config.cg_reg_enable)) &&
289
+
!(val & PLL_CFG_BYPASS_BIT);
290
+
}
291
+
292
+
static int atlantis_clk_pll_enable(struct clk_hw *hw)
293
+
{
294
+
struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
295
+
u32 val, en_val, cg_val;
296
+
int ret;
297
+
298
+
regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
299
+
regmap_read(pll->common.regmap, pll->config.en_reg_offset, &en_val);
300
+
regmap_read(pll->common.regmap, pll->config.cg_reg_offset, &cg_val);
301
+
302
+
/* Check if PLL is already enabled, locked, not bypassed and Gate clk is enabled */
303
+
if ((en_val & PLL_CFG_EN_BIT) && (val & PLL_CFG_LOCK_BIT) &&
304
+
(!pll->config.cg_reg_enable || (cg_val & pll->config.cg_reg_enable)) &&
305
+
!(val & PLL_CFG_BYPASS_BIT)) {
306
+
return 0;
307
+
}
308
+
309
+
/* Step 1: Set bypass mode first */
310
+
regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
311
+
PLL_CFG_BYPASS_BIT, PLL_CFG_BYPASS_BIT);
312
+
313
+
/* Step 2: Enable PLL (clear then set power bit) */
314
+
regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
315
+
PLL_CFG_EN_BIT, 0);
316
+
317
+
regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
318
+
PLL_CFG_EN_BIT, PLL_CFG_EN_BIT);
319
+
320
+
/* Step 3: Wait for PLL lock */
321
+
ret = regmap_read_poll_timeout(pll->common.regmap,
322
+
pll->config.reg_offset, val,
323
+
val & PLL_CFG_LOCK_BIT,
324
+
PLL_BYPASS_WAIT_US, PLL_LOCK_TIMEOUT_US);
325
+
if (ret) {
326
+
pr_err("PLL failed to lock within timeout\n");
327
+
return ret;
328
+
}
329
+
330
+
/* Step 4: Switch from bypass to PLL output */
331
+
regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
332
+
PLL_CFG_BYPASS_BIT, 0);
333
+
334
+
/* Enable Gate clk at PLL Output */
335
+
return regmap_update_bits(pll->common.regmap, pll->config.cg_reg_offset,
336
+
pll->config.cg_reg_enable,
337
+
pll->config.cg_reg_enable);
338
+
}
339
+
340
+
static void atlantis_clk_pll_disable(struct clk_hw *hw)
341
+
{
342
+
struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
343
+
344
+
/* Step 1: Switch to bypass mode before disabling */
345
+
regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
346
+
PLL_CFG_BYPASS_BIT, PLL_CFG_BYPASS_BIT);
347
+
/* Step 2: Power down PLL */
348
+
regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
349
+
PLL_CFG_EN_BIT, 0);
350
+
}
351
+
352
+
static unsigned long atlantis_clk_pll_recalc_rate(struct clk_hw *hw,
353
+
unsigned long parent_rate)
354
+
{
355
+
struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
356
+
357
+
u32 val, refdiv, fbdiv, postdiv1, postdiv2;
358
+
u64 fout;
359
+
360
+
regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
361
+
362
+
if (val & PLL_CFG_BYPASS_BIT)
363
+
return parent_rate;
364
+
365
+
refdiv = FIELD_GET(PLL_CFG_REFDIV_MASK, val);
366
+
fbdiv = FIELD_GET(PLL_CFG_FBDIV_MASK, val);
367
+
postdiv1 = FIELD_GET(PLL_CFG_POSTDIV1_MASK, val);
368
+
postdiv2 = FIELD_GET(PLL_CFG_POSTDIV2_MASK, val);
369
+
370
+
if (!refdiv)
371
+
refdiv = 1;
372
+
if (!postdiv1)
373
+
postdiv1 = 1;
374
+
if (!postdiv2)
375
+
postdiv2 = 1;
376
+
if (!fbdiv)
377
+
return 0;
378
+
379
+
fout = div64_u64((u64)parent_rate * fbdiv,
380
+
refdiv * postdiv1 * postdiv2);
381
+
382
+
return fout;
383
+
}
384
+
385
+
static const struct clk_ops atlantis_clk_pll_ops = {
386
+
.enable = atlantis_clk_pll_enable,
387
+
.disable = atlantis_clk_pll_disable,
388
+
.recalc_rate = atlantis_clk_pll_recalc_rate,
389
+
.is_enabled = atlantis_clk_pll_is_enabled,
390
+
};
391
+
392
+
static int atlantis_clk_gate_shared_enable(struct clk_hw *hw)
393
+
{
394
+
struct atlantis_clk_gate_shared *gate =
395
+
hw_to_atlantis_clk_gate_shared(hw);
396
+
bool need_enable;
397
+
398
+
scoped_guard(spinlock_irqsave, gate->config.refcount_lock)
399
+
{
400
+
need_enable = (*gate->config.share_count)++ == 0;
401
+
if (need_enable) {
402
+
regmap_set_bits(gate->common.regmap,
403
+
gate->config.reg_offset,
404
+
gate->config.enable);
405
+
}
406
+
}
407
+
408
+
if (need_enable) {
409
+
if (!regmap_test_bits(gate->common.regmap,
410
+
gate->config.reg_offset,
411
+
gate->config.enable)) {
412
+
pr_warn("%s: gate enable %d failed to enable\n",
413
+
clk_hw_get_name(hw), gate->config.enable);
414
+
return -EIO;
415
+
}
416
+
}
417
+
418
+
return 0;
419
+
}
420
+
421
+
static void atlantis_clk_gate_shared_disable(struct clk_hw *hw)
422
+
{
423
+
struct atlantis_clk_gate_shared *gate =
424
+
hw_to_atlantis_clk_gate_shared(hw);
425
+
426
+
scoped_guard(spinlock_irqsave, gate->config.refcount_lock)
427
+
{
428
+
if (WARN_ON(*gate->config.share_count == 0))
429
+
return;
430
+
if (--(*gate->config.share_count) > 0)
431
+
return;
432
+
433
+
regmap_clear_bits(gate->common.regmap,
434
+
gate->config.reg_offset,
435
+
gate->config.enable);
436
+
}
437
+
}
438
+
439
+
static int atlantis_clk_gate_shared_is_enabled(struct clk_hw *hw)
440
+
{
441
+
struct atlantis_clk_gate_shared *gate =
442
+
hw_to_atlantis_clk_gate_shared(hw);
443
+
444
+
return regmap_test_bits(gate->common.regmap, gate->config.reg_offset, gate->config.enable);
445
+
}
446
+
447
+
static void atlantis_clk_gate_shared_disable_unused(struct clk_hw *hw)
448
+
{
449
+
struct atlantis_clk_gate_shared *gate =
450
+
hw_to_atlantis_clk_gate_shared(hw);
451
+
452
+
scoped_guard(spinlock_irqsave, gate->config.refcount_lock)
453
+
{
454
+
if (*gate->config.share_count == 0)
455
+
regmap_clear_bits(gate->common.regmap,
456
+
gate->config.reg_offset,
457
+
gate->config.enable);
458
+
}
459
+
}
460
+
461
+
static const struct clk_ops atlantis_clk_gate_shared_ops = {
462
+
.enable = atlantis_clk_gate_shared_enable,
463
+
.disable = atlantis_clk_gate_shared_disable,
464
+
.disable_unused = atlantis_clk_gate_shared_disable_unused,
465
+
.is_enabled = atlantis_clk_gate_shared_is_enabled,
466
+
};
467
+
468
+
#define ATLANTIS_PLL_CONFIG(_reg_offset, _en_reg_offset, _cg_reg_offset, \
469
+
_cg_reg_enable) \
470
+
{ \
471
+
.reg_offset = (_reg_offset), \
472
+
.en_reg_offset = (_en_reg_offset), \
473
+
.cg_reg_offset = (_cg_reg_offset), \
474
+
.cg_reg_enable = (_cg_reg_enable), \
475
+
}
476
+
477
+
#define ATLANTIS_PLL_DEFINE(_clkid, _name, _parent, _reg_offset, \
478
+
_en_reg_offset, _cg_reg_offset, _cg_reg_enable, \
479
+
_flags) \
480
+
static struct atlantis_clk_pll _name = { \
481
+
.config = ATLANTIS_PLL_CONFIG(_reg_offset, _en_reg_offset, \
482
+
_cg_reg_offset, _cg_reg_enable), \
483
+
.common = { .clkid = _clkid, \
484
+
.hw.init = CLK_HW_INIT_PARENTS_DATA( \
485
+
#_name, _parent, &atlantis_clk_pll_ops, \
486
+
_flags) }, \
487
+
}
488
+
#define ATLANTIS_MUX_CONFIG(_shift, _width, _reg_offset) \
489
+
{ \
490
+
.shift = _shift, .width = _width, .reg_offset = _reg_offset \
491
+
}
492
+
493
+
#define ATLANTIS_MUX_DEFINE(_clkid, _name, _parents, _reg_offset, _shift, \
494
+
_width, _flags) \
495
+
static struct atlantis_clk_mux _name = { \
496
+
.config = ATLANTIS_MUX_CONFIG(_shift, _width, _reg_offset), \
497
+
.common = { .clkid = _clkid, \
498
+
.hw.init = CLK_HW_INIT_PARENTS_DATA( \
499
+
#_name, _parents, &atlantis_clk_mux_ops, \
500
+
_flags) } \
501
+
}
502
+
503
+
#define ATLANTIS_DIVIDER_CONFIG(_shift, _width, _flags, _reg_offset) \
504
+
{ \
505
+
.shift = _shift, .width = _width, .flags = _flags, \
506
+
.reg_offset = _reg_offset \
507
+
}
508
+
509
+
#define ATLANTIS_DIVIDER_DEFINE(_clkid, _name, _parent, _reg_offset, _shift, \
510
+
_width, _divflags, _flags) \
511
+
static struct atlantis_clk_divider _name = { \
512
+
.config = ATLANTIS_DIVIDER_CONFIG(_shift, _width, _divflags, \
513
+
_reg_offset), \
514
+
.common = { .clkid = _clkid, \
515
+
.hw.init = CLK_HW_INIT_HW( \
516
+
#_name, &_parent.common.hw, \
517
+
&atlantis_clk_divider_ops, _flags) } \
518
+
}
519
+
#define ATLANTIS_GATE_CONFIG(_enable, _reg_offset) \
520
+
{ \
521
+
.enable = _enable, .reg_offset = _reg_offset \
522
+
}
523
+
524
+
#define ATLANTIS_GATE_DEFINE(_clkid, _name, _parent, _reg_offset, _enable, \
525
+
_flags) \
526
+
static struct atlantis_clk_gate _name = { \
527
+
.config = ATLANTIS_GATE_CONFIG(_enable, _reg_offset), \
528
+
.common = { .clkid = _clkid, \
529
+
.hw.init = CLK_HW_INIT_HW( \
530
+
#_name, &_parent.common.hw, \
531
+
&atlantis_clk_gate_ops, _flags) } \
532
+
}
533
+
#define ATLANTIS_GATE_SHARED_CONFIG(_reg_offset, _enable, _share_count) \
534
+
{ \
535
+
.reg_offset = _reg_offset, .enable = _enable, \
536
+
.share_count = _share_count, .refcount_lock = &refcount_lock \
537
+
}
538
+
#define ATLANTIS_GATE_SHARED_DEFINE(_clkid, _name, _parent, _reg_offset, \
539
+
_enable, _share_count, _flags) \
540
+
static struct atlantis_clk_gate_shared _name = { \
541
+
.config = ATLANTIS_GATE_SHARED_CONFIG(_reg_offset, _enable, \
542
+
_share_count), \
543
+
.common = { .clkid = _clkid, \
544
+
.hw.init = CLK_HW_INIT_HW( \
545
+
#_name, &_parent.common.hw, \
546
+
&atlantis_clk_gate_shared_ops, _flags) } \
547
+
}
548
+
#define ATLANTIS_FIXED_FACTOR_DEFINE(_clkid, _name, _parent, _mult, _div, \
549
+
_flags) \
550
+
static struct atlantis_clk_fixed_factor _name = { \
551
+
.config = { .mult = _mult, .div = _div }, \
552
+
.common = { .clkid = _clkid, \
553
+
.hw.init = CLK_HW_INIT_HW( \
554
+
#_name, &_parent.common.hw, \
555
+
&atlantis_clk_fixed_factor_ops, _flags) } \
556
+
}
557
+
558
+
static DEFINE_SPINLOCK(refcount_lock); /* Lock for refcount value accesses */
559
+
560
+
static const struct regmap_config atlantis_prcm_regmap_config = {
561
+
.reg_bits = 32,
562
+
.reg_stride = 4,
563
+
.val_bits = 32,
564
+
.max_register = 0xFFFC,
565
+
.cache_type = REGCACHE_NONE,
566
+
};
567
+
568
+
struct atlantis_prcm_data {
569
+
struct clk_hw **hws;
570
+
size_t num;
571
+
const char *reset_name;
572
+
};
573
+
574
+
static const struct clk_parent_data osc_24m_clk[] = {
575
+
{ .index = 0 },
576
+
};
577
+
578
+
ATLANTIS_PLL_DEFINE(CLK_RCPU_PLL, rcpu_pll_clk, osc_24m_clk, PLL_RCPU_CFG_REG,
579
+
PLL_RCPU_EN_REG, BUS_CG_REG, 0, /* No Gate Clk at Output */
580
+
CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL);
581
+
582
+
static const struct clk_parent_data rcpu_root_parents[] = {
583
+
{ .index = 0 },
584
+
{ .hw = &rcpu_pll_clk.common.hw },
585
+
};
586
+
587
+
ATLANTIS_MUX_DEFINE(CLK_RCPU_ROOT, rcpu_root_clk, rcpu_root_parents,
588
+
RCPU_DIV_CFG_REG, 0, 1, CLK_SET_RATE_NO_REPARENT);
589
+
590
+
ATLANTIS_DIVIDER_DEFINE(CLK_RCPU_DIV2, rcpu_div2_clk, rcpu_root_clk,
591
+
RCPU_DIV_CFG_REG, 2, 4, 0, 0);
592
+
ATLANTIS_DIVIDER_DEFINE(CLK_RCPU_DIV4, rcpu_div4_clk, rcpu_root_clk,
593
+
RCPU_DIV_CFG_REG, 7, 4, 0, 0);
594
+
ATLANTIS_DIVIDER_DEFINE(CLK_RCPU_RTC, rcpu_rtc_clk, rcpu_div4_clk,
595
+
RCPU_DIV_CFG_REG, 12, 6, 0, 0);
596
+
597
+
ATLANTIS_GATE_DEFINE(CLK_SMNDMA0_ACLK, rcpu_dma0_clk, rcpu_div2_clk,
598
+
RCPU_BLK_CG_REG, BIT(0), 0);
599
+
ATLANTIS_GATE_DEFINE(CLK_SMNDMA1_ACLK, rcpu_dma1_clk, rcpu_div2_clk,
600
+
RCPU_BLK_CG_REG, BIT(1), 0);
601
+
ATLANTIS_GATE_DEFINE(CLK_WDT0_PCLK, sl_wdt0_pclk, rcpu_div4_clk,
602
+
RCPU_BLK_CG_REG, BIT(2), 0);
603
+
ATLANTIS_GATE_DEFINE(CLK_WDT1_PCLK, sl_wdt1_pclk, rcpu_div4_clk,
604
+
RCPU_BLK_CG_REG, BIT(3), 0);
605
+
ATLANTIS_GATE_DEFINE(CLK_TIMER_PCLK, sl_timer_pclk, rcpu_div4_clk,
606
+
RCPU_BLK_CG_REG, BIT(4), 0);
607
+
ATLANTIS_GATE_DEFINE(CLK_PVTC_PCLK, sl_pvtc_pclk, rcpu_div4_clk,
608
+
RCPU_BLK_CG_REG, BIT(12), 0);
609
+
ATLANTIS_GATE_DEFINE(CLK_PMU_PCLK, sl_pmu_pclk, rcpu_div4_clk, RCPU_BLK_CG_REG,
610
+
BIT(13), 0);
611
+
ATLANTIS_GATE_DEFINE(CLK_MAILBOX_HCLK, rcpu_ipc_clk, rcpu_div2_clk,
612
+
RCPU_BLK_CG_REG, BIT(14), 0);
613
+
ATLANTIS_GATE_DEFINE(CLK_SEC_SPACC_HCLK, sec_spacc_hclk, rcpu_div2_clk,
614
+
RCPU_BLK_CG_REG, BIT(26), 0);
615
+
ATLANTIS_GATE_DEFINE(CLK_SEC_OTP_HCLK, sec_otp_hclk, rcpu_div2_clk,
616
+
RCPU_BLK_CG_REG, BIT(28), 0);
617
+
ATLANTIS_GATE_DEFINE(CLK_TRNG_PCLK, sec_trng_pclk, rcpu_div4_clk,
618
+
RCPU_BLK_CG_REG, BIT(29), 0);
619
+
ATLANTIS_GATE_DEFINE(CLK_SEC_CRC_HCLK, sec_crc_hclk, rcpu_div2_clk,
620
+
RCPU_BLK_CG_REG, BIT(30), 0);
621
+
622
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_SMN_HCLK, rcpu_smn_hclk, rcpu_div2_clk, 1, 1,
623
+
0);
624
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_AHB0_HCLK, rcpu_ahb0_hclk, rcpu_div2_clk, 1, 1,
625
+
0);
626
+
627
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_SMN_PCLK, rcpu_smn_pclk, rcpu_div4_clk, 1, 1,
628
+
0);
629
+
630
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_SMN_CLK, rcpu_smn_clk, rcpu_root_clk, 1, 1, 0);
631
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_SCRATCHPAD_CLK, rcpu_scratchpad_aclk,
632
+
rcpu_root_clk, 1, 1, 0);
633
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_RCPU_CORE_CLK, rcpu_core_clk, rcpu_root_clk, 1,
634
+
1, 0);
635
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_RCPU_ROM_CLK, rcpu_rom_aclk, rcpu_root_clk, 1,
636
+
1, 0);
637
+
638
+
static struct atlantis_clk_fixed_factor
639
+
otp_load_clk = { .config = { .mult = 1, .div = 1 },
640
+
.common = {
641
+
.clkid = CLK_OTP_LOAD_CLK,
642
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
643
+
"otp_load_clk", osc_24m_clk,
644
+
&atlantis_clk_fixed_factor_ops,
645
+
CLK_SET_RATE_NO_REPARENT),
646
+
} };
647
+
648
+
ATLANTIS_PLL_DEFINE(CLK_NOC_PLL, nocc_pll_clk, osc_24m_clk, PLL_NOCC_CFG_REG,
649
+
PLL_NOCC_EN_REG, BUS_CG_REG, BIT(0),
650
+
CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL);
651
+
652
+
static const struct clk_parent_data nocc_mux_parents[] = {
653
+
{ .index = 0 },
654
+
{ .hw = &nocc_pll_clk.common.hw },
655
+
};
656
+
657
+
ATLANTIS_MUX_DEFINE(CLK_NOCC_CLK, nocc_clk, nocc_mux_parents, NOCC_CLK_CFG_REG,
658
+
0, 1, CLK_SET_RATE_NO_REPARENT);
659
+
660
+
ATLANTIS_DIVIDER_DEFINE(CLK_NOCC_DIV2, nocc_div2_clk, nocc_clk,
661
+
NOCC_CLK_CFG_REG, 1, 4, 0, 0);
662
+
ATLANTIS_DIVIDER_DEFINE(CLK_NOCC_DIV4, nocc_div4_clk, nocc_clk,
663
+
NOCC_CLK_CFG_REG, 5, 4, 0, 0);
664
+
ATLANTIS_DIVIDER_DEFINE(CLK_NOCC_RTC, nocc_rtc_clk, nocc_div4_clk,
665
+
NOCC_CLK_CFG_REG, 9, 6, 0, 0);
666
+
ATLANTIS_DIVIDER_DEFINE(CLK_NOCC_CAN, nocc_can_clk, nocc_clk, NOCC_CLK_CFG_REG,
667
+
15, 4, 0, 0);
668
+
669
+
static unsigned int refcnt_qspi;
670
+
ATLANTIS_GATE_SHARED_DEFINE(CLK_QSPI_SCLK, lsio_qspi_sclk, nocc_clk,
671
+
LSIO_BLK_CG_REG, BIT(0), &refcnt_qspi, 0);
672
+
ATLANTIS_GATE_SHARED_DEFINE(CLK_QSPI_HCLK, lsio_qspi_hclk, nocc_div2_clk,
673
+
LSIO_BLK_CG_REG, BIT(0), &refcnt_qspi, 0);
674
+
ATLANTIS_GATE_DEFINE(CLK_I2C0_PCLK, lsio_i2c0_pclk, nocc_div4_clk,
675
+
LSIO_BLK_CG_REG, BIT(1), 0);
676
+
ATLANTIS_GATE_DEFINE(CLK_I2C1_PCLK, lsio_i2c1_pclk, nocc_div4_clk,
677
+
LSIO_BLK_CG_REG, BIT(2), 0);
678
+
ATLANTIS_GATE_DEFINE(CLK_I2C2_PCLK, lsio_i2c2_pclk, nocc_div4_clk,
679
+
LSIO_BLK_CG_REG, BIT(3), 0);
680
+
ATLANTIS_GATE_DEFINE(CLK_I2C3_PCLK, lsio_i2c3_pclk, nocc_div4_clk,
681
+
LSIO_BLK_CG_REG, BIT(4), 0);
682
+
ATLANTIS_GATE_DEFINE(CLK_I2C4_PCLK, lsio_i2c4_pclk, nocc_div4_clk,
683
+
LSIO_BLK_CG_REG, BIT(5), 0);
684
+
685
+
ATLANTIS_GATE_DEFINE(CLK_UART0_PCLK, lsio_uart0_pclk, nocc_div4_clk,
686
+
LSIO_BLK_CG_REG, BIT(6), 0);
687
+
ATLANTIS_GATE_DEFINE(CLK_UART1_PCLK, lsio_uart1_pclk, nocc_div4_clk,
688
+
LSIO_BLK_CG_REG, BIT(7), 0);
689
+
ATLANTIS_GATE_DEFINE(CLK_UART2_PCLK, lsio_uart2_pclk, nocc_div4_clk,
690
+
LSIO_BLK_CG_REG, BIT(8), 0);
691
+
ATLANTIS_GATE_DEFINE(CLK_UART3_PCLK, lsio_uart3_pclk, nocc_div4_clk,
692
+
LSIO_BLK_CG_REG, BIT(9), 0);
693
+
ATLANTIS_GATE_DEFINE(CLK_UART4_PCLK, lsio_uart4_pclk, nocc_div4_clk,
694
+
LSIO_BLK_CG_REG, BIT(10), 0);
695
+
ATLANTIS_GATE_DEFINE(CLK_SPI0_PCLK, lsio_spi0_pclk, nocc_div4_clk,
696
+
LSIO_BLK_CG_REG, BIT(11), 0);
697
+
ATLANTIS_GATE_DEFINE(CLK_SPI1_PCLK, lsio_spi1_pclk, nocc_div4_clk,
698
+
LSIO_BLK_CG_REG, BIT(12), 0);
699
+
ATLANTIS_GATE_DEFINE(CLK_SPI2_PCLK, lsio_spi2_pclk, nocc_div4_clk,
700
+
LSIO_BLK_CG_REG, BIT(13), 0);
701
+
ATLANTIS_GATE_DEFINE(CLK_SPI3_PCLK, lsio_spi3_pclk, nocc_div4_clk,
702
+
LSIO_BLK_CG_REG, BIT(14), 0);
703
+
ATLANTIS_GATE_DEFINE(CLK_GPIO_PCLK, lsio_gpio_pclk, nocc_div4_clk,
704
+
LSIO_BLK_CG_REG, BIT(15), 0);
705
+
706
+
static unsigned int refcnt_can0;
707
+
ATLANTIS_GATE_SHARED_DEFINE(CLK_CAN0_HCLK, lsio_can0_hclk, nocc_div2_clk,
708
+
LSIO_BLK_CG_REG, BIT(17), &refcnt_can0, 0);
709
+
ATLANTIS_GATE_SHARED_DEFINE(CLK_CAN0_CLK, lsio_can0_clk, nocc_can_clk,
710
+
LSIO_BLK_CG_REG, BIT(17), &refcnt_can0, 0);
711
+
712
+
static unsigned int refcnt_can1;
713
+
ATLANTIS_GATE_SHARED_DEFINE(CLK_CAN1_HCLK, lsio_can1_hclk, nocc_div2_clk,
714
+
LSIO_BLK_CG_REG, BIT(18), &refcnt_can1, 0);
715
+
ATLANTIS_GATE_SHARED_DEFINE(CLK_CAN1_CLK, lsio_can1_clk, nocc_can_clk,
716
+
LSIO_BLK_CG_REG, BIT(18), &refcnt_can1, 0);
717
+
718
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_CAN0_TIMER_CLK, lsio_can0_timer_clk,
719
+
nocc_rtc_clk, 1, 1, 0);
720
+
ATLANTIS_FIXED_FACTOR_DEFINE(CLK_CAN1_TIMER_CLK, lsio_can1_timer_clk,
721
+
nocc_rtc_clk, 1, 1, 0);
722
+
723
+
static struct clk_hw *atlantis_rcpu_clks[] = {
724
+
[CLK_RCPU_PLL] = &rcpu_pll_clk.common.hw,
725
+
[CLK_RCPU_ROOT] = &rcpu_root_clk.common.hw,
726
+
[CLK_RCPU_DIV2] = &rcpu_div2_clk.common.hw,
727
+
[CLK_RCPU_DIV4] = &rcpu_div4_clk.common.hw,
728
+
[CLK_RCPU_RTC] = &rcpu_rtc_clk.common.hw,
729
+
[CLK_SMNDMA0_ACLK] = &rcpu_dma0_clk.common.hw,
730
+
[CLK_SMNDMA1_ACLK] = &rcpu_dma1_clk.common.hw,
731
+
[CLK_WDT0_PCLK] = &sl_wdt0_pclk.common.hw,
732
+
[CLK_WDT1_PCLK] = &sl_wdt1_pclk.common.hw,
733
+
[CLK_TIMER_PCLK] = &sl_timer_pclk.common.hw,
734
+
[CLK_PVTC_PCLK] = &sl_pvtc_pclk.common.hw,
735
+
[CLK_PMU_PCLK] = &sl_pmu_pclk.common.hw,
736
+
[CLK_MAILBOX_HCLK] = &rcpu_ipc_clk.common.hw,
737
+
[CLK_SEC_SPACC_HCLK] = &sec_spacc_hclk.common.hw,
738
+
[CLK_SEC_OTP_HCLK] = &sec_otp_hclk.common.hw,
739
+
[CLK_TRNG_PCLK] = &sec_trng_pclk.common.hw,
740
+
[CLK_SEC_CRC_HCLK] = &sec_crc_hclk.common.hw,
741
+
[CLK_SMN_HCLK] = &rcpu_smn_hclk.common.hw,
742
+
[CLK_AHB0_HCLK] = &rcpu_ahb0_hclk.common.hw,
743
+
[CLK_SMN_PCLK] = &rcpu_smn_pclk.common.hw,
744
+
[CLK_SMN_CLK] = &rcpu_smn_clk.common.hw,
745
+
[CLK_SCRATCHPAD_CLK] = &rcpu_scratchpad_aclk.common.hw,
746
+
[CLK_RCPU_CORE_CLK] = &rcpu_core_clk.common.hw,
747
+
[CLK_RCPU_ROM_CLK] = &rcpu_rom_aclk.common.hw,
748
+
[CLK_OTP_LOAD_CLK] = &otp_load_clk.common.hw,
749
+
[CLK_NOC_PLL] = &nocc_pll_clk.common.hw,
750
+
[CLK_NOCC_CLK] = &nocc_clk.common.hw,
751
+
[CLK_NOCC_DIV2] = &nocc_div2_clk.common.hw,
752
+
[CLK_NOCC_DIV4] = &nocc_div4_clk.common.hw,
753
+
[CLK_NOCC_RTC] = &nocc_rtc_clk.common.hw,
754
+
[CLK_NOCC_CAN] = &nocc_can_clk.common.hw,
755
+
[CLK_QSPI_SCLK] = &lsio_qspi_sclk.common.hw,
756
+
[CLK_QSPI_HCLK] = &lsio_qspi_hclk.common.hw,
757
+
[CLK_I2C0_PCLK] = &lsio_i2c0_pclk.common.hw,
758
+
[CLK_I2C1_PCLK] = &lsio_i2c1_pclk.common.hw,
759
+
[CLK_I2C2_PCLK] = &lsio_i2c2_pclk.common.hw,
760
+
[CLK_I2C3_PCLK] = &lsio_i2c3_pclk.common.hw,
761
+
[CLK_I2C4_PCLK] = &lsio_i2c4_pclk.common.hw,
762
+
[CLK_UART0_PCLK] = &lsio_uart0_pclk.common.hw,
763
+
[CLK_UART1_PCLK] = &lsio_uart1_pclk.common.hw,
764
+
[CLK_UART2_PCLK] = &lsio_uart2_pclk.common.hw,
765
+
[CLK_UART3_PCLK] = &lsio_uart3_pclk.common.hw,
766
+
[CLK_UART4_PCLK] = &lsio_uart4_pclk.common.hw,
767
+
[CLK_SPI0_PCLK] = &lsio_spi0_pclk.common.hw,
768
+
[CLK_SPI1_PCLK] = &lsio_spi1_pclk.common.hw,
769
+
[CLK_SPI2_PCLK] = &lsio_spi2_pclk.common.hw,
770
+
[CLK_SPI3_PCLK] = &lsio_spi3_pclk.common.hw,
771
+
[CLK_GPIO_PCLK] = &lsio_gpio_pclk.common.hw,
772
+
[CLK_CAN0_HCLK] = &lsio_can0_hclk.common.hw,
773
+
[CLK_CAN0_CLK] = &lsio_can0_clk.common.hw,
774
+
[CLK_CAN1_HCLK] = &lsio_can1_hclk.common.hw,
775
+
[CLK_CAN1_CLK] = &lsio_can1_clk.common.hw,
776
+
[CLK_CAN0_TIMER_CLK] = &lsio_can0_timer_clk.common.hw,
777
+
[CLK_CAN1_TIMER_CLK] = &lsio_can1_timer_clk.common.hw,
778
+
};
779
+
780
+
static const struct atlantis_prcm_data atlantis_prcm_rcpu_data = {
781
+
.hws = atlantis_rcpu_clks,
782
+
.num = ARRAY_SIZE(atlantis_rcpu_clks),
783
+
.reset_name = "rcpu-reset"
784
+
};
785
+
786
+
static int atlantis_prcm_clocks_register(struct device *dev,
787
+
struct regmap *regmap,
788
+
const struct atlantis_prcm_data *data)
789
+
{
790
+
struct clk_hw_onecell_data *clk_data;
791
+
int i, ret;
792
+
size_t num_clks = data->num;
793
+
794
+
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
795
+
GFP_KERNEL);
796
+
if (!clk_data)
797
+
return -ENOMEM;
798
+
799
+
for (i = 0; i < data->num; i++) {
800
+
struct clk_hw *hw = data->hws[i];
801
+
struct atlantis_clk_common *common =
802
+
hw_to_atlantis_clk_common(hw);
803
+
common->regmap = regmap;
804
+
805
+
ret = devm_clk_hw_register(dev, hw);
806
+
if (ret)
807
+
return ret;
808
+
809
+
clk_data->hws[common->clkid] = hw;
810
+
}
811
+
812
+
clk_data->num = num_clks;
813
+
814
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
815
+
}
816
+
817
+
static int atlantis_prcm_probe(struct platform_device *pdev)
818
+
{
819
+
const struct atlantis_prcm_data *data;
820
+
struct auxiliary_device *reset_adev;
821
+
struct regmap *regmap;
822
+
void __iomem *base;
823
+
struct device *dev = &pdev->dev;
824
+
int ret;
825
+
826
+
base = devm_platform_ioremap_resource(pdev, 0);
827
+
if (IS_ERR(base))
828
+
return dev_err_probe(dev, PTR_ERR(base),
829
+
"Failed to map registers\n");
830
+
831
+
regmap = devm_regmap_init_mmio(dev, base, &atlantis_prcm_regmap_config);
832
+
if (IS_ERR(regmap))
833
+
return dev_err_probe(dev, PTR_ERR(regmap),
834
+
"Failed to init regmap\n");
835
+
836
+
data = of_device_get_match_data(dev);
837
+
838
+
ret = atlantis_prcm_clocks_register(dev, regmap, data);
839
+
if (ret)
840
+
return dev_err_probe(dev, ret, "failed to register clocks\n");
841
+
842
+
reset_adev = devm_auxiliary_device_create(dev, data->reset_name, NULL);
843
+
if (!reset_adev)
844
+
return dev_err_probe(dev, -ENODEV, "failed to register resets\n");
845
+
846
+
return 0;
847
+
}
848
+
849
+
static const struct of_device_id atlantis_prcm_of_match[] = {
850
+
{
851
+
.compatible = "tenstorrent,atlantis-prcm-rcpu",
852
+
.data = &atlantis_prcm_rcpu_data,
853
+
},
854
+
{}
855
+
856
+
};
857
+
MODULE_DEVICE_TABLE(of, atlantis_prcm_of_match);
858
+
859
+
static struct platform_driver atlantis_prcm_driver = {
860
+
.probe = atlantis_prcm_probe,
861
+
.driver = {
862
+
.name = "atlantis-prcm",
863
+
.of_match_table = atlantis_prcm_of_match,
864
+
},
865
+
};
866
+
module_platform_driver(atlantis_prcm_driver);
867
+
868
+
MODULE_DESCRIPTION("Tenstorrent Atlantis PRCM Clock Controller Driver");
869
+
MODULE_AUTHOR("Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>");
870
+
MODULE_LICENSE("GPL");
+11
drivers/reset/Kconfig
+11
drivers/reset/Kconfig
···
315
315
help
316
316
This enables the reset driver for Allwinner SoCs.
317
317
318
+
config RESET_TENSTORRENT_ATLANTIS
319
+
tristate "Tenstorrent atlantis reset driver"
320
+
depends on ARCH_TENSTORRENT || COMPILE_TEST
321
+
select AUXILIARY_BUS
322
+
default ARCH_TENSTORRENT
323
+
help
324
+
This enables the driver for the reset controller
325
+
present in the Tenstorrent Atlantis SoC.
326
+
Enable this option to be able to use hardware
327
+
resets on Atalantis based systems.
328
+
318
329
config RESET_TH1520
319
330
tristate "T-HEAD TH1520 reset controller"
320
331
depends on ARCH_THEAD || COMPILE_TEST
+1
drivers/reset/Makefile
+1
drivers/reset/Makefile
···
41
41
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
42
42
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
43
43
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
44
+
obj-$(CONFIG_RESET_TENSTORRENT_ATLANTIS) += reset-tenstorrent-atlantis.o
44
45
obj-$(CONFIG_RESET_TH1520) += reset-th1520.o
45
46
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
46
47
obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
+173
drivers/reset/reset-tenstorrent-atlantis.c
+173
drivers/reset/reset-tenstorrent-atlantis.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Tenstorrent Atlantis PRCM Reset Driver
4
+
*
5
+
* Copyright (c) 2026 Tenstorrent
6
+
*/
7
+
8
+
#include <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h>
9
+
#include <linux/auxiliary_bus.h>
10
+
#include <linux/reset-controller.h>
11
+
#include <linux/regmap.h>
12
+
13
+
/* RCPU Reset Register Offsets */
14
+
#define RCPU_BLK_RST_REG 0x001c
15
+
#define LSIO_BLK_RST_REG 0x0020
16
+
#define HSIO_BLK_RST_REG 0x000c
17
+
#define PCIE_SUBS_RST_REG 0x0000
18
+
#define MM_RSTN_REG 0x0014
19
+
20
+
struct atlantis_reset_data {
21
+
u8 bit;
22
+
u16 reg;
23
+
bool active_low;
24
+
};
25
+
26
+
struct atlantis_reset_controller_data {
27
+
const struct atlantis_reset_data *reset_data;
28
+
size_t count;
29
+
};
30
+
31
+
struct atlantis_reset_controller {
32
+
struct reset_controller_dev rcdev;
33
+
const struct atlantis_reset_controller_data *data;
34
+
struct regmap *regmap;
35
+
};
36
+
37
+
static inline struct atlantis_reset_controller *
38
+
to_atlantis_reset_controller(struct reset_controller_dev *rcdev)
39
+
{
40
+
return container_of(rcdev, struct atlantis_reset_controller, rcdev);
41
+
}
42
+
43
+
#define RESET_DATA(_reg, _bit, _active_low) \
44
+
{ \
45
+
.bit = _bit, .reg = _reg, .active_low = _active_low, \
46
+
}
47
+
48
+
static const struct atlantis_reset_data atlantis_rcpu_resets[] = {
49
+
[RST_SMNDMA0] = RESET_DATA(RCPU_BLK_RST_REG, 0, true),
50
+
[RST_SMNDMA1] = RESET_DATA(RCPU_BLK_RST_REG, 1, true),
51
+
[RST_WDT0] = RESET_DATA(RCPU_BLK_RST_REG, 2, true),
52
+
[RST_WDT1] = RESET_DATA(RCPU_BLK_RST_REG, 3, true),
53
+
[RST_TMR] = RESET_DATA(RCPU_BLK_RST_REG, 4, true),
54
+
[RST_PVTC] = RESET_DATA(RCPU_BLK_RST_REG, 12, true),
55
+
[RST_PMU] = RESET_DATA(RCPU_BLK_RST_REG, 13, true),
56
+
[RST_MAILBOX] = RESET_DATA(RCPU_BLK_RST_REG, 14, true),
57
+
[RST_SPACC] = RESET_DATA(RCPU_BLK_RST_REG, 26, true),
58
+
[RST_OTP] = RESET_DATA(RCPU_BLK_RST_REG, 28, true),
59
+
[RST_TRNG] = RESET_DATA(RCPU_BLK_RST_REG, 29, true),
60
+
[RST_CRC] = RESET_DATA(RCPU_BLK_RST_REG, 30, true),
61
+
[RST_QSPI] = RESET_DATA(LSIO_BLK_RST_REG, 0, true),
62
+
[RST_I2C0] = RESET_DATA(LSIO_BLK_RST_REG, 1, true),
63
+
[RST_I2C1] = RESET_DATA(LSIO_BLK_RST_REG, 2, true),
64
+
[RST_I2C2] = RESET_DATA(LSIO_BLK_RST_REG, 3, true),
65
+
[RST_I2C3] = RESET_DATA(LSIO_BLK_RST_REG, 4, true),
66
+
[RST_I2C4] = RESET_DATA(LSIO_BLK_RST_REG, 5, true),
67
+
[RST_UART0] = RESET_DATA(LSIO_BLK_RST_REG, 6, true),
68
+
[RST_UART1] = RESET_DATA(LSIO_BLK_RST_REG, 7, true),
69
+
[RST_UART2] = RESET_DATA(LSIO_BLK_RST_REG, 8, true),
70
+
[RST_UART3] = RESET_DATA(LSIO_BLK_RST_REG, 9, true),
71
+
[RST_UART4] = RESET_DATA(LSIO_BLK_RST_REG, 10, true),
72
+
[RST_SPI0] = RESET_DATA(LSIO_BLK_RST_REG, 11, true),
73
+
[RST_SPI1] = RESET_DATA(LSIO_BLK_RST_REG, 12, true),
74
+
[RST_SPI2] = RESET_DATA(LSIO_BLK_RST_REG, 13, true),
75
+
[RST_SPI3] = RESET_DATA(LSIO_BLK_RST_REG, 14, true),
76
+
[RST_GPIO] = RESET_DATA(LSIO_BLK_RST_REG, 15, true),
77
+
[RST_CAN0] = RESET_DATA(LSIO_BLK_RST_REG, 17, true),
78
+
[RST_CAN1] = RESET_DATA(LSIO_BLK_RST_REG, 18, true),
79
+
[RST_I2S0] = RESET_DATA(LSIO_BLK_RST_REG, 19, true),
80
+
[RST_I2S1] = RESET_DATA(LSIO_BLK_RST_REG, 20, true),
81
+
82
+
};
83
+
84
+
static const struct atlantis_reset_controller_data atlantis_rcpu_reset_data = {
85
+
.reset_data = atlantis_rcpu_resets,
86
+
.count = ARRAY_SIZE(atlantis_rcpu_resets),
87
+
};
88
+
89
+
static int atlantis_reset_update(struct reset_controller_dev *rcdev,
90
+
unsigned long id, bool assert)
91
+
{
92
+
unsigned int val;
93
+
struct atlantis_reset_controller *rst =
94
+
to_atlantis_reset_controller(rcdev);
95
+
const struct atlantis_reset_data *data = &rst->data->reset_data[id];
96
+
unsigned int mask = BIT(data->bit);
97
+
struct regmap *regmap = rst->regmap;
98
+
99
+
if (data->active_low ^ assert)
100
+
val = mask;
101
+
else
102
+
val = 0;
103
+
104
+
return regmap_update_bits(regmap, data->reg, mask, val);
105
+
}
106
+
107
+
static int atlantis_reset_assert(struct reset_controller_dev *rcdev,
108
+
unsigned long id)
109
+
{
110
+
return atlantis_reset_update(rcdev, id, true);
111
+
}
112
+
113
+
static int atlantis_reset_deassert(struct reset_controller_dev *rcdev,
114
+
unsigned long id)
115
+
{
116
+
return atlantis_reset_update(rcdev, id, false);
117
+
}
118
+
119
+
static const struct reset_control_ops atlantis_reset_control_ops = {
120
+
.assert = atlantis_reset_assert,
121
+
.deassert = atlantis_reset_deassert,
122
+
};
123
+
124
+
static int
125
+
atlantis_reset_controller_register(struct device *dev,
126
+
struct atlantis_reset_controller *controller)
127
+
{
128
+
struct reset_controller_dev *rcdev = &controller->rcdev;
129
+
130
+
rcdev->ops = &atlantis_reset_control_ops;
131
+
rcdev->owner = THIS_MODULE;
132
+
rcdev->of_node = dev->of_node;
133
+
rcdev->nr_resets = controller->data->count;
134
+
135
+
return devm_reset_controller_register(dev, &controller->rcdev);
136
+
}
137
+
static int atlantis_reset_probe(struct auxiliary_device *adev,
138
+
const struct auxiliary_device_id *id)
139
+
{
140
+
struct atlantis_reset_controller *controller;
141
+
struct device *dev = &adev->dev;
142
+
struct regmap *regmap;
143
+
144
+
regmap = dev_get_regmap(dev->parent, NULL);
145
+
if (!regmap)
146
+
return -ENODEV;
147
+
148
+
controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
149
+
if (!controller)
150
+
return -ENOMEM;
151
+
controller->data =
152
+
(const struct atlantis_reset_controller_data *)id->driver_data;
153
+
controller->regmap = regmap;
154
+
155
+
return atlantis_reset_controller_register(dev, controller);
156
+
}
157
+
158
+
static const struct auxiliary_device_id atlantis_reset_ids[] = {
159
+
{ .name = "atlantis_prcm.rcpu-reset",
160
+
.driver_data = (kernel_ulong_t)&atlantis_rcpu_reset_data },
161
+
{},
162
+
};
163
+
MODULE_DEVICE_TABLE(auxiliary, atlantis_reset_ids);
164
+
165
+
static struct auxiliary_driver atlantis_reset_driver = {
166
+
.probe = atlantis_reset_probe,
167
+
.id_table = atlantis_reset_ids,
168
+
};
169
+
module_auxiliary_driver(atlantis_reset_driver);
170
+
171
+
MODULE_AUTHOR("Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>");
172
+
MODULE_DESCRIPTION("Atlantis PRCM reset controller driver");
173
+
MODULE_LICENSE("GPL");
+220
include/dt-bindings/clock/rockchip,rv1103b-cru.h
+220
include/dt-bindings/clock/rockchip,rv1103b-cru.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
+
/*
3
+
* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
4
+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
8
+
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
9
+
10
+
#define PLL_GPLL 0
11
+
#define ARMCLK 1
12
+
#define PLL_DPLL 2
13
+
#define XIN_OSC0_HALF 3
14
+
#define CLK_GPLL_DIV24 4
15
+
#define CLK_GPLL_DIV12 5
16
+
#define CLK_GPLL_DIV6 6
17
+
#define CLK_GPLL_DIV4 7
18
+
#define CLK_GPLL_DIV3 8
19
+
#define CLK_GPLL_DIV2P5 9
20
+
#define CLK_GPLL_DIV2 10
21
+
#define CLK_UART0_SRC 11
22
+
#define CLK_UART1_SRC 12
23
+
#define CLK_UART2_SRC 13
24
+
#define CLK_UART0_FRAC 14
25
+
#define CLK_UART1_FRAC 15
26
+
#define CLK_UART2_FRAC 16
27
+
#define CLK_SAI_SRC 17
28
+
#define CLK_SAI_FRAC 18
29
+
#define LSCLK_NPU_SRC 19
30
+
#define CLK_NPU_SRC 20
31
+
#define ACLK_VEPU_SRC 21
32
+
#define CLK_VEPU_SRC 22
33
+
#define ACLK_VI_SRC 23
34
+
#define CLK_ISP_SRC 24
35
+
#define DCLK_VICAP 25
36
+
#define CCLK_EMMC 26
37
+
#define CCLK_SDMMC0 27
38
+
#define SCLK_SFC_2X 28
39
+
#define LSCLK_PERI_SRC 29
40
+
#define ACLK_PERI_SRC 30
41
+
#define HCLK_HPMCU 31
42
+
#define SCLK_UART0 32
43
+
#define SCLK_UART1 33
44
+
#define SCLK_UART2 34
45
+
#define CLK_I2C_PMU 35
46
+
#define CLK_I2C_PERI 36
47
+
#define CLK_SPI0 37
48
+
#define CLK_PWM0_SRC 38
49
+
#define CLK_PWM1 39
50
+
#define CLK_PWM2 40
51
+
#define DCLK_DECOM_SRC 41
52
+
#define CCLK_SDMMC1 42
53
+
#define CLK_CORE_CRYPTO 43
54
+
#define CLK_PKA_CRYPTO 44
55
+
#define CLK_CORE_RGA 45
56
+
#define MCLK_SAI_SRC 46
57
+
#define CLK_FREQ_PWM0_SRC 47
58
+
#define CLK_COUNTER_PWM0_SRC 48
59
+
#define PCLK_TOP_ROOT 49
60
+
#define CLK_REF_MIPI0 50
61
+
#define CLK_MIPI0_OUT2IO 51
62
+
#define CLK_REF_MIPI1 52
63
+
#define CLK_MIPI1_OUT2IO 53
64
+
#define MCLK_SAI_OUT2IO 54
65
+
#define ACLK_NPU_ROOT 55
66
+
#define HCLK_RKNN 56
67
+
#define ACLK_RKNN 57
68
+
#define LSCLK_VEPU_ROOT 58
69
+
#define HCLK_VEPU 59
70
+
#define ACLK_VEPU 60
71
+
#define CLK_CORE_VEPU 61
72
+
#define PCLK_IOC_VCCIO3 62
73
+
#define PCLK_ACODEC 63
74
+
#define PCLK_USBPHY 64
75
+
#define LSCLK_VI_100M 65
76
+
#define LSCLK_VI_ROOT 66
77
+
#define HCLK_ISP 67
78
+
#define ACLK_ISP 68
79
+
#define CLK_CORE_ISP 69
80
+
#define ACLK_VICAP 70
81
+
#define HCLK_VICAP 71
82
+
#define ISP0CLK_VICAP 72
83
+
#define PCLK_CSI2HOST0 73
84
+
#define PCLK_CSI2HOST1 74
85
+
#define HCLK_EMMC 75
86
+
#define HCLK_SFC 76
87
+
#define HCLK_SFC_XIP 77
88
+
#define HCLK_SDMMC0 78
89
+
#define PCLK_CSIPHY 79
90
+
#define PCLK_GPIO1 80
91
+
#define DBCLK_GPIO1 81
92
+
#define PCLK_IOC_VCCIO47 82
93
+
#define LSCLK_DDR_ROOT 83
94
+
#define CLK_TIMER_DDRMON 84
95
+
#define LSCLK_PMU_ROOT 85
96
+
#define PCLK_PMU 86
97
+
#define XIN_RC_DIV 87
98
+
#define CLK_32K 88
99
+
#define PCLK_PMU_GPIO0 89
100
+
#define DBCLK_PMU_GPIO0 90
101
+
#define CLK_DDR_FAIL_SAFE 91
102
+
#define PCLK_PMU_HP_TIMER 92
103
+
#define CLK_PMU_32K_HP_TIMER 93
104
+
#define PCLK_PWM0 94
105
+
#define CLK_PWM0 95
106
+
#define CLK_OSC_PWM0 96
107
+
#define CLK_RC_PWM0 97
108
+
#define CLK_FREQ_PWM0 98
109
+
#define CLK_COUNTER_PWM0 99
110
+
#define PCLK_I2C0 100
111
+
#define CLK_I2C0 101
112
+
#define PCLK_UART0 102
113
+
#define PCLK_IOC_PMUIO0 103
114
+
#define CLK_REFOUT 104
115
+
#define CLK_PREROLL 105
116
+
#define CLK_PREROLL_32K 106
117
+
#define CLK_LPMCU_PMU 107
118
+
#define PCLK_SPI2AHB 108
119
+
#define HCLK_SPI2AHB 109
120
+
#define SCLK_SPI2AHB 110
121
+
#define PCLK_WDT_LPMCU 111
122
+
#define TCLK_WDT_LPMCU 112
123
+
#define HCLK_SFC_PMU1 113
124
+
#define HCLK_SFC_XIP_PMU1 114
125
+
#define SCLK_SFC_2X_PMU1 115
126
+
#define CLK_LPMCU 116
127
+
#define CLK_LPMCU_RTC 117
128
+
#define PCLK_LPMCU_MAILBOX 118
129
+
#define PCLK_IOC_PMUIO1 119
130
+
#define PCLK_CRU_PMU1 120
131
+
#define PCLK_PERI_ROOT 121
132
+
#define PCLK_RTC_ROOT 122
133
+
#define CLK_TIMER_ROOT 123
134
+
#define PCLK_TIMER 124
135
+
#define CLK_TIMER0 125
136
+
#define CLK_TIMER1 126
137
+
#define CLK_TIMER2 127
138
+
#define CLK_TIMER3 128
139
+
#define CLK_TIMER4 129
140
+
#define CLK_TIMER5 130
141
+
#define PCLK_STIMER 131
142
+
#define CLK_STIMER0 132
143
+
#define CLK_STIMER1 133
144
+
#define PCLK_WDT_NS 134
145
+
#define TCLK_WDT_NS 135
146
+
#define PCLK_WDT_S 136
147
+
#define TCLK_WDT_S 137
148
+
#define PCLK_WDT_HPMCU 138
149
+
#define TCLK_WDT_HPMCU 139
150
+
#define PCLK_I2C1 140
151
+
#define CLK_I2C1 141
152
+
#define PCLK_I2C2 142
153
+
#define CLK_I2C2 143
154
+
#define PCLK_I2C3 144
155
+
#define CLK_I2C3 145
156
+
#define PCLK_I2C4 146
157
+
#define CLK_I2C4 147
158
+
#define PCLK_SPI0 148
159
+
#define PCLK_PWM1 149
160
+
#define CLK_OSC_PWM1 150
161
+
#define PCLK_PWM2 151
162
+
#define CLK_OSC_PWM2 152
163
+
#define PCLK_UART2 153
164
+
#define PCLK_UART1 154
165
+
#define ACLK_RKDMA 155
166
+
#define PCLK_TSADC 156
167
+
#define CLK_TSADC 157
168
+
#define CLK_TSADC_TSEN 158
169
+
#define PCLK_SARADC 159
170
+
#define CLK_SARADC 160
171
+
#define PCLK_GPIO2 161
172
+
#define DBCLK_GPIO2 162
173
+
#define PCLK_IOC_VCCIO6 163
174
+
#define ACLK_USBOTG 164
175
+
#define CLK_REF_USBOTG 165
176
+
#define HCLK_SDMMC1 166
177
+
#define HCLK_SAI 167
178
+
#define MCLK_SAI 168
179
+
#define ACLK_CRYPTO 169
180
+
#define HCLK_CRYPTO 170
181
+
#define HCLK_RK_RNG_NS 171
182
+
#define HCLK_RK_RNG_S 172
183
+
#define PCLK_OTPC_NS 173
184
+
#define CLK_OTPC_ROOT_NS 174
185
+
#define CLK_SBPI_OTPC_NS 175
186
+
#define CLK_USER_OTPC_NS 176
187
+
#define PCLK_OTPC_S 177
188
+
#define CLK_OTPC_ROOT_S 178
189
+
#define CLK_SBPI_OTPC_S 179
190
+
#define CLK_USER_OTPC_S 180
191
+
#define CLK_OTPC_ARB 181
192
+
#define PCLK_OTP_MASK 182
193
+
#define HCLK_RGA 183
194
+
#define ACLK_RGA 184
195
+
#define ACLK_MAC 185
196
+
#define PCLK_MAC 186
197
+
#define CLK_MACPHY 187
198
+
#define ACLK_SPINLOCK 188
199
+
#define HCLK_CACHE 189
200
+
#define PCLK_HPMCU_MAILBOX 190
201
+
#define PCLK_HPMCU_INTMUX 191
202
+
#define CLK_HPMCU 192
203
+
#define CLK_HPMCU_RTC 193
204
+
#define DCLK_DECOM 194
205
+
#define ACLK_DECOM 195
206
+
#define PCLK_DECOM 196
207
+
#define ACLK_SYS_SRAM 197
208
+
#define PCLK_DMA2DDR 198
209
+
#define ACLK_DMA2DDR 199
210
+
#define PCLK_DCF 200
211
+
#define ACLK_DCF 201
212
+
#define MCLK_ACODEC_TX 202
213
+
#define SCLK_UART0_SRC 203
214
+
#define SCLK_UART1_SRC 204
215
+
#define SCLK_UART2_SRC 205
216
+
#define XIN_RC_SRC 206
217
+
#define CLK_UTMI_USBOTG 207
218
+
#define CLK_REF_USBPHY 208
219
+
220
+
#endif // _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
+103
include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
+103
include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Tenstorrent Atlantis PRCM Clock and Reset Indices
4
+
*
5
+
* Copyright (c) 2026 Tenstorrent
6
+
*/
7
+
8
+
#ifndef _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H
9
+
#define _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H
10
+
11
+
/*
12
+
* RCPU Domain Clock IDs
13
+
*/
14
+
#define CLK_RCPU_PLL 0
15
+
#define CLK_RCPU_ROOT 1
16
+
#define CLK_RCPU_DIV2 2
17
+
#define CLK_RCPU_DIV4 3
18
+
#define CLK_RCPU_RTC 4
19
+
#define CLK_SMNDMA0_ACLK 5
20
+
#define CLK_SMNDMA1_ACLK 6
21
+
#define CLK_WDT0_PCLK 7
22
+
#define CLK_WDT1_PCLK 8
23
+
#define CLK_TIMER_PCLK 9
24
+
#define CLK_PVTC_PCLK 10
25
+
#define CLK_PMU_PCLK 11
26
+
#define CLK_MAILBOX_HCLK 12
27
+
#define CLK_SEC_SPACC_HCLK 13
28
+
#define CLK_SEC_OTP_HCLK 14
29
+
#define CLK_TRNG_PCLK 15
30
+
#define CLK_SEC_CRC_HCLK 16
31
+
#define CLK_SMN_HCLK 17
32
+
#define CLK_AHB0_HCLK 18
33
+
#define CLK_SMN_PCLK 19
34
+
#define CLK_SMN_CLK 20
35
+
#define CLK_SCRATCHPAD_CLK 21
36
+
#define CLK_RCPU_CORE_CLK 22
37
+
#define CLK_RCPU_ROM_CLK 23
38
+
#define CLK_OTP_LOAD_CLK 24
39
+
#define CLK_NOC_PLL 25
40
+
#define CLK_NOCC_CLK 26
41
+
#define CLK_NOCC_DIV2 27
42
+
#define CLK_NOCC_DIV4 28
43
+
#define CLK_NOCC_RTC 29
44
+
#define CLK_NOCC_CAN 30
45
+
#define CLK_QSPI_SCLK 31
46
+
#define CLK_QSPI_HCLK 32
47
+
#define CLK_I2C0_PCLK 33
48
+
#define CLK_I2C1_PCLK 34
49
+
#define CLK_I2C2_PCLK 35
50
+
#define CLK_I2C3_PCLK 36
51
+
#define CLK_I2C4_PCLK 37
52
+
#define CLK_UART0_PCLK 38
53
+
#define CLK_UART1_PCLK 39
54
+
#define CLK_UART2_PCLK 40
55
+
#define CLK_UART3_PCLK 41
56
+
#define CLK_UART4_PCLK 42
57
+
#define CLK_SPI0_PCLK 43
58
+
#define CLK_SPI1_PCLK 44
59
+
#define CLK_SPI2_PCLK 45
60
+
#define CLK_SPI3_PCLK 46
61
+
#define CLK_GPIO_PCLK 47
62
+
#define CLK_CAN0_HCLK 48
63
+
#define CLK_CAN0_CLK 49
64
+
#define CLK_CAN1_HCLK 50
65
+
#define CLK_CAN1_CLK 51
66
+
#define CLK_CAN0_TIMER_CLK 52
67
+
#define CLK_CAN1_TIMER_CLK 53
68
+
69
+
/* RCPU domain reset */
70
+
#define RST_SMNDMA0 0
71
+
#define RST_SMNDMA1 1
72
+
#define RST_WDT0 2
73
+
#define RST_WDT1 3
74
+
#define RST_TMR 4
75
+
#define RST_PVTC 5
76
+
#define RST_PMU 6
77
+
#define RST_MAILBOX 7
78
+
#define RST_SPACC 8
79
+
#define RST_OTP 9
80
+
#define RST_TRNG 10
81
+
#define RST_CRC 11
82
+
#define RST_QSPI 12
83
+
#define RST_I2C0 13
84
+
#define RST_I2C1 14
85
+
#define RST_I2C2 15
86
+
#define RST_I2C3 16
87
+
#define RST_I2C4 17
88
+
#define RST_UART0 18
89
+
#define RST_UART1 19
90
+
#define RST_UART2 20
91
+
#define RST_UART3 21
92
+
#define RST_UART4 22
93
+
#define RST_SPI0 23
94
+
#define RST_SPI1 24
95
+
#define RST_SPI2 25
96
+
#define RST_SPI3 26
97
+
#define RST_GPIO 27
98
+
#define RST_CAN0 28
99
+
#define RST_CAN1 29
100
+
#define RST_I2S0 30
101
+
#define RST_I2S1 31
102
+
103
+
#endif /* _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H */
+5
-1
include/dt-bindings/clock/vf610-clock.h
+5
-1
include/dt-bindings/clock/vf610-clock.h
···
197
197
#define VF610_CLK_TCON1 188
198
198
#define VF610_CLK_CAAM 189
199
199
#define VF610_CLK_CRC 190
200
-
#define VF610_CLK_END 191
200
+
#define VF610_CLK_ESW 191
201
+
#define VF610_CLK_ESW_MAC_TAB0 192
202
+
#define VF610_CLK_ESW_MAC_TAB1 193
203
+
#define VF610_CLK_ESW_MAC_TAB2 194
204
+
#define VF610_CLK_ESW_MAC_TAB3 195
201
205
202
206
#endif /* __DT_BINDINGS_CLOCK_VF610_H */