tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: qcom: gcc-sdx55: get rid of test clock

The test clock apparently it's not used by anyone upstream. Remove it.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228185237.3111988-13-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson 523611f1 e21f2a94

-12
-12
drivers/clk/qcom/gcc-sdx55.c
··· 22 22 23 23 enum { 24 24 P_BI_TCXO, 25 - P_CORE_BI_PLL_TEST_SE, 26 25 P_GPLL0_OUT_EVEN, 27 26 P_GPLL0_OUT_MAIN, 28 27 P_GPLL4_OUT_EVEN, ··· 136 137 { P_BI_TCXO, 0 }, 137 138 { P_GPLL0_OUT_MAIN, 1 }, 138 139 { P_GPLL0_OUT_EVEN, 6 }, 139 - { P_CORE_BI_PLL_TEST_SE, 7 }, 140 140 }; 141 141 142 142 static const struct clk_parent_data gcc_parents_0[] = { 143 143 { .fw_name = "bi_tcxo" }, 144 144 { .hw = &gpll0.clkr.hw }, 145 145 { .hw = &gpll0_out_even.clkr.hw }, 146 - { .fw_name = "core_bi_pll_test_se" }, 147 146 }; 148 147 149 148 static const struct clk_parent_data gcc_parents_0_ao[] = { 150 149 { .fw_name = "bi_tcxo_ao" }, 151 150 { .hw = &gpll0.clkr.hw }, 152 151 { .hw = &gpll0_out_even.clkr.hw }, 153 - { .fw_name = "core_bi_pll_test_se" }, 154 152 }; 155 153 156 154 static const struct parent_map gcc_parent_map_2[] = { ··· 156 160 { P_GPLL4_OUT_EVEN, 2 }, 157 161 { P_GPLL5_OUT_MAIN, 5 }, 158 162 { P_GPLL0_OUT_EVEN, 6 }, 159 - { P_CORE_BI_PLL_TEST_SE, 7 }, 160 163 }; 161 164 162 165 static const struct clk_parent_data gcc_parents_2[] = { ··· 164 169 { .hw = &gpll4_out_even.clkr.hw }, 165 170 { .hw = &gpll5.clkr.hw }, 166 171 { .hw = &gpll0_out_even.clkr.hw }, 167 - { .fw_name = "core_bi_pll_test_se" }, 168 172 }; 169 173 170 174 static const struct parent_map gcc_parent_map_3[] = { ··· 171 177 { P_GPLL0_OUT_MAIN, 1 }, 172 178 { P_SLEEP_CLK, 5 }, 173 179 { P_GPLL0_OUT_EVEN, 6 }, 174 - { P_CORE_BI_PLL_TEST_SE, 7 }, 175 180 }; 176 181 177 182 static const struct clk_parent_data gcc_parents_3[] = { ··· 178 185 { .hw = &gpll0.clkr.hw }, 179 186 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 180 187 { .hw = &gpll0_out_even.clkr.hw }, 181 - { .fw_name = "core_bi_pll_test_se" }, 182 188 }; 183 189 184 190 static const struct parent_map gcc_parent_map_4[] = { 185 191 { P_BI_TCXO, 0 }, 186 192 { P_SLEEP_CLK, 5 }, 187 - { P_CORE_BI_PLL_TEST_SE, 7 }, 188 193 }; 189 194 190 195 static const struct clk_parent_data gcc_parents_4[] = { 191 196 { .fw_name = "bi_tcxo" }, 192 197 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 193 - { .fw_name = "core_bi_pll_test_se" }, 194 198 }; 195 199 196 200 static const struct parent_map gcc_parent_map_5[] = { ··· 195 205 { P_GPLL0_OUT_MAIN, 1 }, 196 206 { P_GPLL4_OUT_EVEN, 2 }, 197 207 { P_GPLL0_OUT_EVEN, 6 }, 198 - { P_CORE_BI_PLL_TEST_SE, 7 }, 199 208 }; 200 209 201 210 static const struct clk_parent_data gcc_parents_5[] = { ··· 202 213 { .hw = &gpll0.clkr.hw }, 203 214 { .hw = &gpll4_out_even.clkr.hw }, 204 215 { .hw = &gpll0_out_even.clkr.hw }, 205 - { .fw_name = "core_bi_pll_test_se" }, 206 216 }; 207 217 208 218 static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {