tjh.dev / kernel
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clk: qcom: gcc-sdx55: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data/names/hws easy and errorproof.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228185237.3111988-12-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson e21f2a94 bfa78833

+26 -26
+26 -26
drivers/clk/qcom/gcc-sdx55.c
··· 232 232 .clkr.hw.init = &(struct clk_init_data){ 233 233 .name = "gcc_blsp1_qup1_i2c_apps_clk_src", 234 234 .parent_data = gcc_parents_0, 235 - .num_parents = 4, 235 + .num_parents = ARRAY_SIZE(gcc_parents_0), 236 236 .ops = &clk_rcg2_ops, 237 237 }, 238 238 }; ··· 258 258 .clkr.hw.init = &(struct clk_init_data){ 259 259 .name = "gcc_blsp1_qup1_spi_apps_clk_src", 260 260 .parent_data = gcc_parents_0, 261 - .num_parents = 4, 261 + .num_parents = ARRAY_SIZE(gcc_parents_0), 262 262 .ops = &clk_rcg2_ops, 263 263 }, 264 264 }; ··· 272 272 .clkr.hw.init = &(struct clk_init_data){ 273 273 .name = "gcc_blsp1_qup2_i2c_apps_clk_src", 274 274 .parent_data = gcc_parents_0, 275 - .num_parents = 4, 275 + .num_parents = ARRAY_SIZE(gcc_parents_0), 276 276 .ops = &clk_rcg2_ops, 277 277 }, 278 278 }; ··· 286 286 .clkr.hw.init = &(struct clk_init_data){ 287 287 .name = "gcc_blsp1_qup2_spi_apps_clk_src", 288 288 .parent_data = gcc_parents_0, 289 - .num_parents = 4, 289 + .num_parents = ARRAY_SIZE(gcc_parents_0), 290 290 .ops = &clk_rcg2_ops, 291 291 }, 292 292 }; ··· 300 300 .clkr.hw.init = &(struct clk_init_data){ 301 301 .name = "gcc_blsp1_qup3_i2c_apps_clk_src", 302 302 .parent_data = gcc_parents_0, 303 - .num_parents = 4, 303 + .num_parents = ARRAY_SIZE(gcc_parents_0), 304 304 .ops = &clk_rcg2_ops, 305 305 }, 306 306 }; ··· 314 314 .clkr.hw.init = &(struct clk_init_data){ 315 315 .name = "gcc_blsp1_qup3_spi_apps_clk_src", 316 316 .parent_data = gcc_parents_0, 317 - .num_parents = 4, 317 + .num_parents = ARRAY_SIZE(gcc_parents_0), 318 318 .ops = &clk_rcg2_ops, 319 319 }, 320 320 }; ··· 328 328 .clkr.hw.init = &(struct clk_init_data){ 329 329 .name = "gcc_blsp1_qup4_i2c_apps_clk_src", 330 330 .parent_data = gcc_parents_0, 331 - .num_parents = 4, 331 + .num_parents = ARRAY_SIZE(gcc_parents_0), 332 332 .ops = &clk_rcg2_ops, 333 333 }, 334 334 }; ··· 342 342 .clkr.hw.init = &(struct clk_init_data){ 343 343 .name = "gcc_blsp1_qup4_spi_apps_clk_src", 344 344 .parent_data = gcc_parents_0, 345 - .num_parents = 4, 345 + .num_parents = ARRAY_SIZE(gcc_parents_0), 346 346 .ops = &clk_rcg2_ops, 347 347 }, 348 348 }; ··· 386 386 .clkr.hw.init = &(struct clk_init_data){ 387 387 .name = "gcc_blsp1_uart1_apps_clk_src", 388 388 .parent_data = gcc_parents_0, 389 - .num_parents = 4, 389 + .num_parents = ARRAY_SIZE(gcc_parents_0), 390 390 .ops = &clk_rcg2_ops, 391 391 }, 392 392 }; ··· 400 400 .clkr.hw.init = &(struct clk_init_data){ 401 401 .name = "gcc_blsp1_uart2_apps_clk_src", 402 402 .parent_data = gcc_parents_0, 403 - .num_parents = 4, 403 + .num_parents = ARRAY_SIZE(gcc_parents_0), 404 404 .ops = &clk_rcg2_ops, 405 405 }, 406 406 }; ··· 414 414 .clkr.hw.init = &(struct clk_init_data){ 415 415 .name = "gcc_blsp1_uart3_apps_clk_src", 416 416 .parent_data = gcc_parents_0, 417 - .num_parents = 4, 417 + .num_parents = ARRAY_SIZE(gcc_parents_0), 418 418 .ops = &clk_rcg2_ops, 419 419 }, 420 420 }; ··· 428 428 .clkr.hw.init = &(struct clk_init_data){ 429 429 .name = "gcc_blsp1_uart4_apps_clk_src", 430 430 .parent_data = gcc_parents_0, 431 - .num_parents = 4, 431 + .num_parents = ARRAY_SIZE(gcc_parents_0), 432 432 .ops = &clk_rcg2_ops, 433 433 }, 434 434 }; ··· 450 450 .clkr.hw.init = &(struct clk_init_data){ 451 451 .name = "gcc_cpuss_ahb_clk_src", 452 452 .parent_data = gcc_parents_0_ao, 453 - .num_parents = 4, 453 + .num_parents = ARRAY_SIZE(gcc_parents_0_ao), 454 454 .ops = &clk_rcg2_ops, 455 455 }, 456 456 }; ··· 469 469 .clkr.hw.init = &(struct clk_init_data){ 470 470 .name = "gcc_cpuss_rbcpr_clk_src", 471 471 .parent_data = gcc_parents_0_ao, 472 - .num_parents = 4, 472 + .num_parents = ARRAY_SIZE(gcc_parents_0_ao), 473 473 .ops = &clk_rcg2_ops, 474 474 }, 475 475 }; ··· 493 493 .clkr.hw.init = &(struct clk_init_data){ 494 494 .name = "gcc_emac_clk_src", 495 495 .parent_data = gcc_parents_5, 496 - .num_parents = 5, 496 + .num_parents = ARRAY_SIZE(gcc_parents_5), 497 497 .ops = &clk_rcg2_ops, 498 498 }, 499 499 }; ··· 514 514 .clkr.hw.init = &(struct clk_init_data){ 515 515 .name = "gcc_emac_ptp_clk_src", 516 516 .parent_data = gcc_parents_2, 517 - .num_parents = 6, 517 + .num_parents = ARRAY_SIZE(gcc_parents_2), 518 518 .ops = &clk_rcg2_ops, 519 519 }, 520 520 }; ··· 537 537 .clkr.hw.init = &(struct clk_init_data){ 538 538 .name = "gcc_gp1_clk_src", 539 539 .parent_data = gcc_parents_3, 540 - .num_parents = 5, 540 + .num_parents = ARRAY_SIZE(gcc_parents_3), 541 541 .ops = &clk_rcg2_ops, 542 542 }, 543 543 }; ··· 551 551 .clkr.hw.init = &(struct clk_init_data){ 552 552 .name = "gcc_gp2_clk_src", 553 553 .parent_data = gcc_parents_3, 554 - .num_parents = 5, 554 + .num_parents = ARRAY_SIZE(gcc_parents_3), 555 555 .ops = &clk_rcg2_ops, 556 556 }, 557 557 }; ··· 565 565 .clkr.hw.init = &(struct clk_init_data){ 566 566 .name = "gcc_gp3_clk_src", 567 567 .parent_data = gcc_parents_3, 568 - .num_parents = 5, 568 + .num_parents = ARRAY_SIZE(gcc_parents_3), 569 569 .ops = &clk_rcg2_ops, 570 570 }, 571 571 }; ··· 579 579 .clkr.hw.init = &(struct clk_init_data){ 580 580 .name = "gcc_pcie_aux_phy_clk_src", 581 581 .parent_data = gcc_parents_4, 582 - .num_parents = 3, 582 + .num_parents = ARRAY_SIZE(gcc_parents_4), 583 583 .ops = &clk_rcg2_ops, 584 584 }, 585 585 }; ··· 598 598 .clkr.hw.init = &(struct clk_init_data){ 599 599 .name = "gcc_pcie_rchng_phy_clk_src", 600 600 .parent_data = gcc_parents_3, 601 - .num_parents = 5, 601 + .num_parents = ARRAY_SIZE(gcc_parents_3), 602 602 .ops = &clk_rcg2_ops, 603 603 }, 604 604 }; ··· 619 619 .clkr.hw.init = &(struct clk_init_data){ 620 620 .name = "gcc_pdm2_clk_src", 621 621 .parent_data = gcc_parents_0, 622 - .num_parents = 4, 622 + .num_parents = ARRAY_SIZE(gcc_parents_0), 623 623 .ops = &clk_rcg2_ops, 624 624 }, 625 625 }; ··· 633 633 .clkr.hw.init = &(struct clk_init_data){ 634 634 .name = "gcc_sdcc1_apps_clk_src", 635 635 .parent_data = gcc_parents_0, 636 - .num_parents = 4, 636 + .num_parents = ARRAY_SIZE(gcc_parents_0), 637 637 .ops = &clk_rcg2_ops, 638 638 }, 639 639 }; ··· 652 652 .clkr.hw.init = &(struct clk_init_data){ 653 653 .name = "gcc_usb30_master_clk_src", 654 654 .parent_data = gcc_parents_0, 655 - .num_parents = 4, 655 + .num_parents = ARRAY_SIZE(gcc_parents_0), 656 656 .ops = &clk_rcg2_ops, 657 657 }, 658 658 }; ··· 671 671 .clkr.hw.init = &(struct clk_init_data){ 672 672 .name = "gcc_usb30_mock_utmi_clk_src", 673 673 .parent_data = gcc_parents_0, 674 - .num_parents = 4, 674 + .num_parents = ARRAY_SIZE(gcc_parents_0), 675 675 .ops = &clk_rcg2_ops, 676 676 }, 677 677 }; ··· 691 691 .clkr.hw.init = &(struct clk_init_data){ 692 692 .name = "gcc_usb3_phy_aux_clk_src", 693 693 .parent_data = gcc_parents_4, 694 - .num_parents = 3, 694 + .num_parents = ARRAY_SIZE(gcc_parents_4), 695 695 .ops = &clk_rcg2_ops, 696 696 }, 697 697 };