clk: microchip: mpfs: move id & offset out of clock structs

The id and offset are the only thing differentiating the clock structs
from "regular" clock structures. On the pretext of converting to more
normal structures, move the id and offset out of the clock structs and
into the hw structs instead.

Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-10-conor.dooley@microchip.com

authored by

Conor Dooley and committed by

Claudiu Beznea 3 years ago 52fe6b52 14016e4a

+15 -15

1 changed file

expand all

drivers

clk

microchip

clk-mpfs.c

+15 -15

drivers/clk/microchip/clk-mpfs.c

··· 51 51 52 52 struct mpfs_cfg_clock { 53 53 const struct clk_div_table *table; 54 - unsigned int id; 55 - u32 reg_offset; 56 54 u8 shift; 57 55 u8 width; 58 56 u8 flags; ··· 61 63 void __iomem *sys_base; 62 64 struct clk_hw hw; 63 65 struct clk_init_data init; 66 + unsigned int id; 67 + u32 reg_offset; 64 68 }; 65 69 66 70 #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 67 71 68 72 struct mpfs_periph_clock { 69 - unsigned int id; 70 73 u8 shift; 71 74 }; 72 75 ··· 75 76 struct mpfs_periph_clock periph; 76 77 void __iomem *sys_base; 77 78 struct clk_hw hw; 79 + unsigned int id; 78 80 }; 79 81 80 82 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) ··· 241 241 void __iomem *base_addr = cfg_hw->sys_base; 242 242 u32 val; 243 243 244 - val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; 244 + val = readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift; 245 245 val &= clk_div_mask(cfg->width); 246 246 247 247 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); ··· 270 270 return divider_setting; 271 271 272 272 spin_lock_irqsave(&mpfs_clk_lock, flags); 273 - val = readl_relaxed(base_addr + cfg->reg_offset); 273 + val = readl_relaxed(base_addr + cfg_hw->reg_offset); 274 274 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 275 275 val |= divider_setting << cfg->shift; 276 - writel_relaxed(val, base_addr + cfg->reg_offset); 276 + writel_relaxed(val, base_addr + cfg_hw->reg_offset); 277 277 278 278 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 279 279 ··· 287 287 }; 288 288 289 289 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 290 - .cfg.id = _id, \ 290 + .id = _id, \ 291 291 .cfg.shift = _shift, \ 292 292 .cfg.width = _width, \ 293 293 .cfg.table = _table, \ 294 - .cfg.reg_offset = _offset, \ 294 + .reg_offset = _offset, \ 295 295 .cfg.flags = _flags, \ 296 296 .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ 297 297 } ··· 309 309 CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 310 310 REG_CLOCK_CONFIG_CR), 311 311 { 312 - .cfg.id = CLK_RTCREF, 312 + .id = CLK_RTCREF, 313 313 .cfg.shift = 0, 314 314 .cfg.width = 12, 315 315 .cfg.table = mpfs_div_rtcref_table, 316 - .cfg.reg_offset = REG_RTC_CLOCK_CR, 316 + .reg_offset = REG_RTC_CLOCK_CR, 317 317 .cfg.flags = CLK_DIVIDER_ONE_BASED, 318 318 .hw.init = 319 319 CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), ··· 341 341 ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); 342 342 if (ret) 343 343 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 344 - cfg_hw->cfg.id); 344 + cfg_hw->id); 345 345 346 - id = cfg_hw->cfg.id; 346 + id = cfg_hw->id; 347 347 data->hw_data.hws[id] = &cfg_hw->hw; 348 348 } 349 349 ··· 411 411 }; 412 412 413 413 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 414 - .periph.id = _id, \ 414 + .id = _id, \ 415 415 .periph.shift = _shift, \ 416 416 .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 417 417 _flags), \ ··· 486 486 ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); 487 487 if (ret) 488 488 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 489 - periph_hw->periph.id); 489 + periph_hw->id); 490 490 491 - id = periph_hws[i].periph.id; 491 + id = periph_hws[i].id; 492 492 data->hw_data.hws[id] = &periph_hw->hw; 493 493 } 494 494

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