Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
- Handle RTAS delay requests in configure_bridge from Russell Currey
- Refactor the configure_bridge RTAS tokens from Russell Currey
- Fix definition of SIAR and SDAR registers from Thomas Huth
- Use privileged SPR number for MMCR2 from Thomas Huth
- Update LPCR only if it is powernv from Aneesh Kumar K.V
- Fix the reference bit update when handling hash fault from Aneesh
Kumar K.V
- Add missing tlb flush from Aneesh Kumar K.V
- Add POWER8NVL support to ibm,client-architecture-support call from
Thomas Huth
* tag 'powerpc-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support call
powerpc/mm/radix: Add missing tlb flush
powerpc/mm/hash: Fix the reference bit update when handling hash fault
powerpc/mm/radix: Update LPCR only if it is powernv
powerpc: Use privileged SPR number for MMCR2
powerpc: Fix definition of SIAR and SDAR registers
powerpc/pseries/eeh: Refactor the configure_bridge RTAS tokens
powerpc/pseries/eeh: Handle RTAS delay requests in configure_bridge
+68
-38
+3
-3
arch/powerpc/include/asm/reg.h
+3
-3
arch/powerpc/include/asm/reg.h
···
717
717
#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
718
718
#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
719
719
#define SPRN_MMCR1 798
720
-
#define SPRN_MMCR2 769
720
+
#define SPRN_MMCR2 785
721
721
#define SPRN_MMCRA 0x312
722
722
#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
723
723
#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
···
754
754
#define SPRN_PMC6 792
755
755
#define SPRN_PMC7 793
756
756
#define SPRN_PMC8 794
757
-
#define SPRN_SIAR 780
758
-
#define SPRN_SDAR 781
759
757
#define SPRN_SIER 784
760
758
#define SIER_SIPR 0x2000000 /* Sampled MSR_PR */
761
759
#define SIER_SIHV 0x1000000 /* Sampled MSR_HV */
762
760
#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */
763
761
#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */
762
+
#define SPRN_SIAR 796
763
+
#define SPRN_SDAR 797
764
764
#define SPRN_TACR 888
765
765
#define SPRN_TCSCR 889
766
766
#define SPRN_CSIGR 890
+1
arch/powerpc/kernel/prom_init.c
+1
arch/powerpc/kernel/prom_init.c
···
656
656
W(0xffff0000), W(0x003e0000), /* POWER6 */
657
657
W(0xffff0000), W(0x003f0000), /* POWER7 */
658
658
W(0xffff0000), W(0x004b0000), /* POWER8E */
659
+
W(0xffff0000), W(0x004c0000), /* POWER8NVL */
659
660
W(0xffff0000), W(0x004d0000), /* POWER8 */
660
661
W(0xffffffff), W(0x0f000004), /* all 2.07-compliant */
661
662
W(0xffffffff), W(0x0f000003), /* all 2.06-compliant */
+20
-2
arch/powerpc/mm/hash_utils_64.c
+20
-2
arch/powerpc/mm/hash_utils_64.c
···
159
159
},
160
160
};
161
161
162
+
/*
163
+
* 'R' and 'C' update notes:
164
+
* - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
165
+
* create writeable HPTEs without C set, because the hcall H_PROTECT
166
+
* that we use in that case will not update C
167
+
* - The above is however not a problem, because we also don't do that
168
+
* fancy "no flush" variant of eviction and we use H_REMOVE which will
169
+
* do the right thing and thus we don't have the race I described earlier
170
+
*
171
+
* - Under bare metal, we do have the race, so we need R and C set
172
+
* - We make sure R is always set and never lost
173
+
* - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
174
+
*/
162
175
unsigned long htab_convert_pte_flags(unsigned long pteflags)
163
176
{
164
177
unsigned long rflags = 0;
···
199
186
rflags |= 0x1;
200
187
}
201
188
/*
202
-
* Always add "C" bit for perf. Memory coherence is always enabled
189
+
* We can't allow hardware to update hpte bits. Hence always
190
+
* set 'R' bit and set 'C' if it is a write fault
191
+
* Memory coherence is always enabled
203
192
*/
204
-
rflags |= HPTE_R_C | HPTE_R_M;
193
+
rflags |= HPTE_R_R | HPTE_R_M;
194
+
195
+
if (pteflags & _PAGE_DIRTY)
196
+
rflags |= HPTE_R_C;
205
197
/*
206
198
* Add in WIG bits
207
199
*/
+1
-4
arch/powerpc/mm/pgtable-book3s64.c
+1
-4
arch/powerpc/mm/pgtable-book3s64.c
···
33
33
changed = !pmd_same(*(pmdp), entry);
34
34
if (changed) {
35
35
__ptep_set_access_flags(pmdp_ptep(pmdp), pmd_pte(entry));
36
-
/*
37
-
* Since we are not supporting SW TLB systems, we don't
38
-
* have any thing similar to flush_tlb_page_nohash()
39
-
*/
36
+
flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
40
37
}
41
38
return changed;
42
39
}
+10
-13
arch/powerpc/mm/pgtable-radix.c
+10
-13
arch/powerpc/mm/pgtable-radix.c
···
296
296
void __init radix__early_init_mmu(void)
297
297
{
298
298
unsigned long lpcr;
299
-
/*
300
-
* setup LPCR UPRT based on mmu_features
301
-
*/
302
-
lpcr = mfspr(SPRN_LPCR);
303
-
mtspr(SPRN_LPCR, lpcr | LPCR_UPRT);
304
299
305
300
#ifdef CONFIG_PPC_64K_PAGES
306
301
/* PAGE_SIZE mappings */
···
338
343
__pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
339
344
340
345
radix_init_page_sizes();
341
-
if (!firmware_has_feature(FW_FEATURE_LPAR))
346
+
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
347
+
lpcr = mfspr(SPRN_LPCR);
348
+
mtspr(SPRN_LPCR, lpcr | LPCR_UPRT);
342
349
radix_init_partition_table();
350
+
}
343
351
344
352
radix_init_pgtable();
345
353
}
···
351
353
{
352
354
unsigned long lpcr;
353
355
/*
354
-
* setup LPCR UPRT based on mmu_features
356
+
* update partition table control register and UPRT
355
357
*/
356
-
lpcr = mfspr(SPRN_LPCR);
357
-
mtspr(SPRN_LPCR, lpcr | LPCR_UPRT);
358
-
/*
359
-
* update partition table control register, 64 K size.
360
-
*/
361
-
if (!firmware_has_feature(FW_FEATURE_LPAR))
358
+
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
359
+
lpcr = mfspr(SPRN_LPCR);
360
+
mtspr(SPRN_LPCR, lpcr | LPCR_UPRT);
361
+
362
362
mtspr(SPRN_PTCR,
363
363
__pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
364
+
}
364
365
}
365
366
366
367
void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
+33
-16
arch/powerpc/platforms/pseries/eeh_pseries.c
+33
-16
arch/powerpc/platforms/pseries/eeh_pseries.c
···
53
53
static int ibm_slot_error_detail;
54
54
static int ibm_get_config_addr_info;
55
55
static int ibm_get_config_addr_info2;
56
-
static int ibm_configure_bridge;
57
56
static int ibm_configure_pe;
58
57
59
58
/*
···
80
81
ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
81
82
ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
82
83
ibm_configure_pe = rtas_token("ibm,configure-pe");
83
-
ibm_configure_bridge = rtas_token("ibm,configure-bridge");
84
+
85
+
/*
86
+
* ibm,configure-pe and ibm,configure-bridge have the same semantics,
87
+
* however ibm,configure-pe can be faster. If we can't find
88
+
* ibm,configure-pe then fall back to using ibm,configure-bridge.
89
+
*/
90
+
if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE)
91
+
ibm_configure_pe = rtas_token("ibm,configure-bridge");
84
92
85
93
/*
86
94
* Necessary sanity check. We needn't check "get-config-addr-info"
···
99
93
(ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
100
94
ibm_read_slot_reset_state == RTAS_UNKNOWN_SERVICE) ||
101
95
ibm_slot_error_detail == RTAS_UNKNOWN_SERVICE ||
102
-
(ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
103
-
ibm_configure_bridge == RTAS_UNKNOWN_SERVICE)) {
96
+
ibm_configure_pe == RTAS_UNKNOWN_SERVICE) {
104
97
pr_info("EEH functionality not supported\n");
105
98
return -EINVAL;
106
99
}
···
620
615
{
621
616
int config_addr;
622
617
int ret;
618
+
/* Waiting 0.2s maximum before skipping configuration */
619
+
int max_wait = 200;
623
620
624
621
/* Figure out the PE address */
625
622
config_addr = pe->config_addr;
626
623
if (pe->addr)
627
624
config_addr = pe->addr;
628
625
629
-
/* Use new configure-pe function, if supported */
630
-
if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE) {
626
+
while (max_wait > 0) {
631
627
ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
632
628
config_addr, BUID_HI(pe->phb->buid),
633
629
BUID_LO(pe->phb->buid));
634
-
} else if (ibm_configure_bridge != RTAS_UNKNOWN_SERVICE) {
635
-
ret = rtas_call(ibm_configure_bridge, 3, 1, NULL,
636
-
config_addr, BUID_HI(pe->phb->buid),
637
-
BUID_LO(pe->phb->buid));
638
-
} else {
639
-
return -EFAULT;
630
+
631
+
if (!ret)
632
+
return ret;
633
+
634
+
/*
635
+
* If RTAS returns a delay value that's above 100ms, cut it
636
+
* down to 100ms in case firmware made a mistake. For more
637
+
* on how these delay values work see rtas_busy_delay_time
638
+
*/
639
+
if (ret > RTAS_EXTENDED_DELAY_MIN+2 &&
640
+
ret <= RTAS_EXTENDED_DELAY_MAX)
641
+
ret = RTAS_EXTENDED_DELAY_MIN+2;
642
+
643
+
max_wait -= rtas_busy_delay_time(ret);
644
+
645
+
if (max_wait < 0)
646
+
break;
647
+
648
+
rtas_busy_delay(ret);
640
649
}
641
650
642
-
if (ret)
643
-
pr_warn("%s: Unable to configure bridge PHB#%d-PE#%x (%d)\n",
644
-
__func__, pe->phb->global_number, pe->addr, ret);
645
-
651
+
pr_warn("%s: Unable to configure bridge PHB#%d-PE#%x (%d)\n",
652
+
__func__, pe->phb->global_number, pe->addr, ret);
646
653
return ret;
647
654
}
648
655