Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'devicetree-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT Bindings:
- Various LED binding conversions and clean-ups. Convert the
ir-spi-led, pwm-ir-tx, and gpio-ir-tx LED bindings to schemas.
Consistently reference LED common.yaml or multi-led schemas and
disallow undefined properties.
- Convert IDT 89HPESx, pwm-clock, st,stmipid02, Xilinx PCIe hosts,
and fsl,imx-fb bindings to schema
- Add ata-generic, Broadcom u-boot environment, and dynamic MTD
sub-partitions bindings.
- Make all SPI based displays reference spi-peripheral-props.yaml
- Fix some schema property regex's which should be fixed strings or
were missing start/end anchors
- Remove 'status' in examples, again...
DT Core:
- Fix a possible NULL dereference in overlay functions
- Fix kexec reading 32-bit "linux,initrd-{start,end}" values (which
never worked)
- Add of_address_count() helper to count number of 'reg' entries
- Support .dtso extension for DT overlay source files. Rename staging
and unittest overlay files.
- Update dtc to upstream v1.6.1-63-g55778a03df61"
* tag 'devicetree-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (42 commits)
dt-bindings: leds: Add missing references to common LED schema
dt-bindings: leds: intel,lgm: Add missing 'led-gpios' property
of: overlay: fix null pointer dereferencing in find_dup_cset_node_entry() and find_dup_cset_prop()
dt-bindings: lcdif: Fix constraints for imx8mp
media: dt-bindings: atmel,isc: Drop unneeded unevaluatedProperties
dt-bindings: Drop Jee Heng Sia
dt-bindings: thermal: cooling-devices: Add missing cache related properties
dt-bindings: leds: irled: ir-spi-led: convert to DT schema
dt-bindings: leds: irled: pwm-ir-tx: convert to DT schema
dt-bindings: leds: irled: gpio-ir-tx: convert to DT schema
dt-bindings: leds: mt6360: rework to match multi-led
dt-bindings: leds: lp55xx: rework to match multi-led
dt-bindings: leds: lp55xx: switch to preferred 'gpios' suffix
dt-bindings: leds: lp55xx: allow label
dt-bindings: leds: use unevaluatedProperties for common.yaml
dt-bindings: thermal: tsens: Add SM6115 compatible
of/kexec: Fix reading 32-bit "linux,initrd-{start,end}" values
dt-bindings: display: Convert fsl,imx-fb.txt to dt-schema
dt-bindings: Add missing start and/or end of line regex anchors
dt-bindings: qcom,pdc: Add missing compatibles
...
+1357
-719
-1
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
-1
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
+27
-27
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+27
-27
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
···
123
123
some PLLs, clocks and then brings up CPU0 for resuming the
124
124
system.
125
125
126
+
core-supply:
127
+
description:
128
+
Phandle to voltage regulator connected to the SoC Core power rail.
129
+
130
+
core-domain:
131
+
type: object
132
+
description: |
133
+
The vast majority of hardware blocks of Tegra SoC belong to a
134
+
Core power domain, which has a dedicated voltage rail that powers
135
+
the blocks.
136
+
137
+
properties:
138
+
operating-points-v2:
139
+
description:
140
+
Should contain level, voltages and opp-supported-hw property.
141
+
The supported-hw is a bitfield indicating SoC speedo or process
142
+
ID mask.
143
+
144
+
"#power-domain-cells":
145
+
const: 0
146
+
147
+
required:
148
+
- operating-points-v2
149
+
- "#power-domain-cells"
150
+
151
+
additionalProperties: false
152
+
126
153
i2c-thermtrip:
127
154
type: object
128
155
description:
···
326
299
- pins
327
300
328
301
additionalProperties: false
329
-
330
-
core-domain:
331
-
type: object
332
-
description: |
333
-
The vast majority of hardware blocks of Tegra SoC belong to a
334
-
Core power domain, which has a dedicated voltage rail that powers
335
-
the blocks.
336
-
337
-
properties:
338
-
operating-points-v2:
339
-
description:
340
-
Should contain level, voltages and opp-supported-hw property.
341
-
The supported-hw is a bitfield indicating SoC speedo or process
342
-
ID mask.
343
-
344
-
"#power-domain-cells":
345
-
const: 0
346
-
347
-
required:
348
-
- operating-points-v2
349
-
- "#power-domain-cells"
350
-
351
-
additionalProperties: false
352
-
353
-
core-supply:
354
-
description:
355
-
Phandle to voltage regulator connected to the SoC Core power rail.
356
302
357
303
required:
358
304
- compatible
+58
Documentation/devicetree/bindings/ata/ata-generic.yaml
+58
Documentation/devicetree/bindings/ata/ata-generic.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ata/ata-generic.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Generic Parallel ATA Controller
8
+
9
+
maintainers:
10
+
- Linus Walleij <linus.walleij@linaro.org>
11
+
12
+
description:
13
+
Generic Parallel ATA controllers supporting PIO modes only.
14
+
15
+
properties:
16
+
compatible:
17
+
items:
18
+
- enum:
19
+
- arm,vexpress-cf
20
+
- fsl,mpc8349emitx-pata
21
+
- const: ata-generic
22
+
23
+
reg:
24
+
items:
25
+
- description: Command interface registers
26
+
- description: Control interface registers
27
+
28
+
reg-shift:
29
+
enum: [ 1, 2 ]
30
+
31
+
interrupts:
32
+
maxItems: 1
33
+
34
+
ata-generic,use16bit:
35
+
type: boolean
36
+
description: Use 16-bit accesses instead of 32-bit for data transfers
37
+
38
+
pio-mode:
39
+
description: Maximum ATA PIO transfer mode
40
+
$ref: /schemas/types.yaml#/definitions/uint32
41
+
maximum: 6
42
+
default: 0
43
+
44
+
required:
45
+
- compatible
46
+
- reg
47
+
48
+
additionalProperties: false
49
+
50
+
examples:
51
+
- |
52
+
compact-flash@1a000 {
53
+
compatible = "arm,vexpress-cf", "ata-generic";
54
+
reg = <0x1a000 0x100>,
55
+
<0x1a100 0xf00>;
56
+
reg-shift = <2>;
57
+
};
58
+
...
-26
Documentation/devicetree/bindings/clock/pwm-clock.txt
-26
Documentation/devicetree/bindings/clock/pwm-clock.txt
···
1
-
Binding for an external clock signal driven by a PWM pin.
2
-
3
-
This binding uses the common clock binding[1] and the common PWM binding[2].
4
-
5
-
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
-
[2] Documentation/devicetree/bindings/pwm/pwm.txt
7
-
8
-
Required properties:
9
-
- compatible : shall be "pwm-clock".
10
-
- #clock-cells : from common clock binding; shall be set to 0.
11
-
- pwms : from common PWM binding; this determines the clock frequency
12
-
via the period given in the PWM specifier.
13
-
14
-
Optional properties:
15
-
- clock-output-names : From common clock binding.
16
-
- clock-frequency : Exact output frequency, in case the PWM period
17
-
is not exact but was rounded to nanoseconds.
18
-
19
-
Example:
20
-
clock {
21
-
compatible = "pwm-clock";
22
-
#clock-cells = <0>;
23
-
clock-frequency = <25000000>;
24
-
clock-output-names = "mipi_mclk";
25
-
pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */
26
-
};
+45
Documentation/devicetree/bindings/clock/pwm-clock.yaml
+45
Documentation/devicetree/bindings/clock/pwm-clock.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/pwm-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: An external clock signal driven by a PWM pin.
8
+
9
+
maintainers:
10
+
- Philipp Zabel <p.zabel@pengutronix.de>
11
+
12
+
properties:
13
+
compatible:
14
+
const: pwm-clock
15
+
16
+
'#clock-cells':
17
+
const: 0
18
+
19
+
clock-frequency:
20
+
description: Exact output frequency, in case the PWM period is not exact
21
+
but was rounded to nanoseconds.
22
+
23
+
clock-output-names:
24
+
maxItems: 1
25
+
26
+
pwms:
27
+
maxItems: 1
28
+
29
+
required:
30
+
- compatible
31
+
- '#clock-cells'
32
+
- pwms
33
+
34
+
additionalProperties: false
35
+
36
+
examples:
37
+
- |
38
+
clock {
39
+
compatible = "pwm-clock";
40
+
#clock-cells = <0>;
41
+
clock-frequency = <25000000>;
42
+
clock-output-names = "mipi_mclk";
43
+
pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */
44
+
};
45
+
...
+1
-1
Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
+1
-1
Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
+28
-1
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
+28
-1
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
···
52
52
interrupts:
53
53
maxItems: 1
54
54
55
+
power-domains:
56
+
maxItems: 1
57
+
55
58
port:
56
59
$ref: /schemas/graph.yaml#/properties/port
57
60
description: The LCDIF output port
···
84
81
maxItems: 3
85
82
required:
86
83
- clock-names
87
-
else:
84
+
- if:
85
+
properties:
86
+
compatible:
87
+
contains:
88
+
const: fsl,imx8mp-lcdif
89
+
then:
90
+
properties:
91
+
clocks:
92
+
minItems: 3
93
+
maxItems: 3
94
+
clock-names:
95
+
minItems: 3
96
+
maxItems: 3
97
+
required:
98
+
- clock-names
99
+
- power-domains
100
+
- if:
101
+
not:
102
+
properties:
103
+
compatible:
104
+
contains:
105
+
enum:
106
+
- fsl,imx6sx-lcdif
107
+
- fsl,imx8mp-lcdif
108
+
then:
88
109
properties:
89
110
clocks:
90
111
maxItems: 1
-57
Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt
-57
Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt
···
1
-
Freescale imx21 Framebuffer
2
-
3
-
This framebuffer driver supports devices imx1, imx21, imx25, and imx27.
4
-
5
-
Required properties:
6
-
- compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
7
-
- reg : Should contain 1 register ranges(address and length)
8
-
- interrupts : One interrupt of the fb dev
9
-
10
-
Required nodes:
11
-
- display: Phandle to a display node as described in
12
-
Documentation/devicetree/bindings/display/panel/display-timing.txt
13
-
Additional, the display node has to define properties:
14
-
- bits-per-pixel: Bits per pixel
15
-
- fsl,pcr: LCDC PCR value
16
-
A display node may optionally define
17
-
- fsl,aus-mode: boolean to enable AUS mode (only for imx21)
18
-
19
-
Optional properties:
20
-
- lcd-supply: Regulator for LCD supply voltage.
21
-
- fsl,dmacr: DMA Control Register value. This is optional. By default, the
22
-
register is not modified as recommended by the datasheet.
23
-
- fsl,lpccr: Contrast Control Register value. This property provides the
24
-
default value for the contrast control register.
25
-
If that property is omitted, the register is zeroed.
26
-
- fsl,lscr1: LCDC Sharp Configuration Register value.
27
-
28
-
Example:
29
-
30
-
imxfb: fb@10021000 {
31
-
compatible = "fsl,imx21-fb";
32
-
interrupts = <61>;
33
-
reg = <0x10021000 0x1000>;
34
-
display = <&display0>;
35
-
};
36
-
37
-
...
38
-
39
-
display0: display0 {
40
-
model = "Primeview-PD050VL1";
41
-
bits-per-pixel = <16>;
42
-
fsl,pcr = <0xf0c88080>; /* non-standard but required */
43
-
display-timings {
44
-
native-mode = <&timing_disp0>;
45
-
timing_disp0: 640x480 {
46
-
hactive = <640>;
47
-
vactive = <480>;
48
-
hback-porch = <112>;
49
-
hfront-porch = <36>;
50
-
hsync-len = <32>;
51
-
vback-porch = <33>;
52
-
vfront-porch = <33>;
53
-
vsync-len = <2>;
54
-
clock-frequency = <25000000>;
55
-
};
56
-
};
57
-
};
+102
Documentation/devicetree/bindings/display/imx/fsl,imx-lcdc.yaml
+102
Documentation/devicetree/bindings/display/imx/fsl,imx-lcdc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale i.MX LCD Controller, found on i.MX1, i.MX21, i.MX25 and i.MX27
8
+
9
+
maintainers:
10
+
- Sascha Hauer <s.hauer@pengutronix.de>
11
+
- Pengutronix Kernel Team <kernel@pengutronix.de>
12
+
13
+
properties:
14
+
compatible:
15
+
oneOf:
16
+
- enum:
17
+
- fsl,imx1-fb
18
+
- fsl,imx21-fb
19
+
- items:
20
+
- enum:
21
+
- fsl,imx25-fb
22
+
- fsl,imx27-fb
23
+
- const: fsl,imx21-fb
24
+
25
+
clocks:
26
+
maxItems: 3
27
+
28
+
clock-names:
29
+
items:
30
+
- const: ipg
31
+
- const: ahb
32
+
- const: per
33
+
34
+
display:
35
+
$ref: /schemas/types.yaml#/definitions/phandle
36
+
37
+
interrupts:
38
+
maxItems: 1
39
+
40
+
reg:
41
+
maxItems: 1
42
+
43
+
lcd-supply:
44
+
description:
45
+
Regulator for LCD supply voltage.
46
+
47
+
fsl,dmacr:
48
+
$ref: /schemas/types.yaml#/definitions/uint32
49
+
description:
50
+
Override value for DMA Control Register
51
+
52
+
fsl,lpccr:
53
+
$ref: /schemas/types.yaml#/definitions/uint32
54
+
description:
55
+
Contrast Control Register value.
56
+
57
+
fsl,lscr1:
58
+
$ref: /schemas/types.yaml#/definitions/uint32
59
+
description:
60
+
LCDC Sharp Configuration Register value.
61
+
62
+
required:
63
+
- compatible
64
+
- clocks
65
+
- clock-names
66
+
- display
67
+
- interrupts
68
+
- reg
69
+
70
+
additionalProperties: false
71
+
72
+
examples:
73
+
- |
74
+
imxfb: fb@10021000 {
75
+
compatible = "fsl,imx21-fb";
76
+
interrupts = <61>;
77
+
reg = <0x10021000 0x1000>;
78
+
display = <&display0>;
79
+
clocks = <&clks 103>, <&clks 49>, <&clks 66>;
80
+
clock-names = "ipg", "ahb", "per";
81
+
};
82
+
83
+
display0: display0 {
84
+
model = "Primeview-PD050VL1";
85
+
bits-per-pixel = <16>;
86
+
fsl,pcr = <0xf0c88080>; /* non-standard but required */
87
+
88
+
display-timings {
89
+
native-mode = <&timing_disp0>;
90
+
timing_disp0: timing0 {
91
+
hactive = <640>;
92
+
vactive = <480>;
93
+
hback-porch = <112>;
94
+
hfront-porch = <36>;
95
+
hsync-len = <32>;
96
+
vback-porch = <33>;
97
+
vfront-porch = <33>;
98
+
vsync-len = <2>;
99
+
clock-frequency = <25000000>;
100
+
};
101
+
};
102
+
};
+2
-1
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
+2
-1
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
+1
Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
+1
Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
+2
-1
Documentation/devicetree/bindings/display/panel/nec,nl8048hl11.yaml
+2
-1
Documentation/devicetree/bindings/display/panel/nec,nl8048hl11.yaml
+2
-3
Documentation/devicetree/bindings/display/panel/samsung,lms380kf01.yaml
+2
-3
Documentation/devicetree/bindings/display/panel/samsung,lms380kf01.yaml
···
9
9
description: The LMS380KF01 is a 480x800 DPI display panel from Samsung Mobile
10
10
Displays (SMD) utilizing the WideChips WS2401 display controller. It can be
11
11
used with internal or external backlight control.
12
-
The panel must obey the rules for a SPI slave device as specified in
13
-
spi/spi-controller.yaml
14
12
15
13
maintainers:
16
14
- Linus Walleij <linus.walleij@linaro.org>
17
15
18
16
allOf:
19
17
- $ref: panel-common.yaml#
18
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
20
19
21
20
properties:
22
21
compatible:
···
58
59
- spi-cpol
59
60
- port
60
61
61
-
additionalProperties: false
62
+
unevaluatedProperties: false
62
63
63
64
examples:
64
65
- |
+2
-1
Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml
+2
-1
Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml
+2
-2
Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
+2
-2
Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
···
7
7
title: Samsung S6D27A1 display panel
8
8
9
9
description: The S6D27A1 is a 480x800 DPI display panel from Samsung Mobile
10
-
Displays (SMD). The panel must obey the rules for a SPI slave device
11
-
as specified in spi/spi-controller.yaml
10
+
Displays (SMD).
12
11
13
12
maintainers:
14
13
- Markuss Broks <markuss.broks@gmail.com>
15
14
16
15
allOf:
17
16
- $ref: panel-common.yaml#
17
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
18
18
19
19
properties:
20
20
compatible:
+1
Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml
+1
Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml
-1
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
-1
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
···
138
138
<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
139
139
<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
140
140
clock-names = "disp", "dsc", "hub";
141
-
status = "disabled";
142
141
143
142
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
144
143
···
226
227
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
227
228
<&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
228
229
clock-names = "disp", "hub";
229
-
status = "disabled";
230
230
231
231
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
232
232
-1
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
-1
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+2
-2
Documentation/devicetree/bindings/hwmon/adt7475.yaml
+2
-2
Documentation/devicetree/bindings/hwmon/adt7475.yaml
···
61
61
$ref: /schemas/types.yaml#/definitions/uint32
62
62
enum: [0, 1]
63
63
64
-
"adi,pin(5|10)-function":
64
+
"^adi,pin(5|10)-function$":
65
65
description: |
66
66
Configures the function for pin 5 on the adi,adt7473 and adi,adt7475. Or
67
67
pin 10 on the adi,adt7476 and adi,adt7490.
···
70
70
- pwm2
71
71
- smbalert#
72
72
73
-
"adi,pin(9|14)-function":
73
+
"^adi,pin(9|14)-function$":
74
74
description: |
75
75
Configures the function for pin 9 on the adi,adt7473 and adi,adt7475. Or
76
76
pin 14 on the adi,adt7476 and adi,adt7490
-1
Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml
-1
Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml
-1
Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
-1
Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
+4
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+4
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
···
28
28
- enum:
29
29
- qcom,sc7180-pdc
30
30
- qcom,sc7280-pdc
31
+
- qcom,sc8280xp-pdc
31
32
- qcom,sdm845-pdc
33
+
- qcom,sdx55-pdc
34
+
- qcom,sdx65-pdc
32
35
- qcom,sm6350-pdc
33
36
- qcom,sm8150-pdc
34
37
- qcom,sm8250-pdc
35
38
- qcom,sm8350-pdc
39
+
- qcom,sm8450-pdc
36
40
- const: qcom,pdc
37
41
38
42
reg:
+4
-2
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+4
-2
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
···
29
29
- renesas,ipmmu-r8a7793 # R-Car M2-N
30
30
- renesas,ipmmu-r8a7794 # R-Car E2
31
31
- const: renesas,ipmmu-vmsa # R-Mobile APE6 or R-Car Gen2 or RZ/G1
32
+
32
33
- items:
33
34
- enum:
34
35
- renesas,ipmmu-r8a774a1 # RZ/G2M
···
44
43
- renesas,ipmmu-r8a77980 # R-Car V3H
45
44
- renesas,ipmmu-r8a77990 # R-Car E3
46
45
- renesas,ipmmu-r8a77995 # R-Car D3
47
-
- renesas,ipmmu-r8a779a0 # R-Car V3U
46
+
48
47
- items:
49
48
- enum:
50
-
- renesas,ipmmu-r8a779f0 # R-Car S4-8
49
+
- renesas,ipmmu-r8a779a0 # R-Car V3U
50
+
- renesas,ipmmu-r8a779f0 # R-Car S4-8
51
51
- const: renesas,rcar-gen4-ipmmu-vmsa # R-Car Gen4
52
52
53
53
reg:
-14
Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.txt
-14
Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.txt
···
1
-
Device tree bindings for IR LED connected through gpio pin which is used as
2
-
remote controller transmitter.
3
-
4
-
Required properties:
5
-
- compatible: should be "gpio-ir-tx".
6
-
- gpios : Should specify the IR LED GPIO, see "gpios property" in
7
-
Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs
8
-
should be indicated using flags in the GPIO specifier.
9
-
10
-
Example:
11
-
irled@0 {
12
-
compatible = "gpio-ir-tx";
13
-
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
14
-
};
+36
Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.yaml
+36
Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/leds/irled/gpio-ir-tx.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: IR LED connected through GPIO pin
8
+
9
+
maintainers:
10
+
- Sean Young <sean@mess.org>
11
+
12
+
description:
13
+
IR LED connected through GPIO pin which is used as remote controller
14
+
transmitter.
15
+
16
+
properties:
17
+
compatible:
18
+
const: gpio-ir-tx
19
+
20
+
gpios:
21
+
maxItems: 1
22
+
23
+
required:
24
+
- compatible
25
+
- gpios
26
+
27
+
additionalProperties: false
28
+
29
+
examples:
30
+
- |
31
+
#include <dt-bindings/gpio/gpio.h>
32
+
33
+
irled {
34
+
compatible = "gpio-ir-tx";
35
+
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
36
+
};
+61
Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml
+61
Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/leds/irled/ir-spi-led.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: IR LED connected through SPI bus
8
+
9
+
maintainers:
10
+
- Sean Young <sean@mess.org>
11
+
12
+
description:
13
+
IR LED switch is connected to the MOSI line of the SPI device and the data
14
+
is delivered through that.
15
+
16
+
allOf:
17
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
18
+
19
+
properties:
20
+
compatible:
21
+
const: ir-spi-led
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
duty-cycle:
27
+
$ref: /schemas/types.yaml#/definitions/uint8
28
+
enum: [50, 60, 70, 75, 80, 90]
29
+
description:
30
+
Percentage of one period in which the signal is active.
31
+
32
+
led-active-low:
33
+
type: boolean
34
+
description:
35
+
Output is negated with a NOT gate.
36
+
37
+
power-supply: true
38
+
39
+
required:
40
+
- compatible
41
+
- reg
42
+
43
+
unevaluatedProperties: false
44
+
45
+
examples:
46
+
- |
47
+
spi {
48
+
#address-cells = <1>;
49
+
#size-cells = <0>;
50
+
51
+
irled@0 {
52
+
compatible = "ir-spi-led";
53
+
reg = <0x0>;
54
+
55
+
duty-cycle = /bits/ 8 <60>;
56
+
led-active-low;
57
+
power-supply = <&irda_regulator>;
58
+
spi-max-frequency = <5000000>;
59
+
};
60
+
};
61
+
-13
Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.txt
-13
Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.txt
···
1
-
Device tree bindings for IR LED connected through pwm pin which is used as
2
-
remote controller transmitter.
3
-
4
-
Required properties:
5
-
- compatible: should be "pwm-ir-tx".
6
-
- pwms : PWM property to point to the PWM device (phandle)/port (id)
7
-
and to specify the period time to be used: <&phandle id period_ns>;
8
-
9
-
Example:
10
-
irled {
11
-
compatible = "pwm-ir-tx";
12
-
pwms = <&pwm0 0 10000000>;
13
-
};
+34
Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.yaml
+34
Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/leds/irled/pwm-ir-tx.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: IR LED connected through PWM pin
8
+
9
+
maintainers:
10
+
- Sean Young <sean@mess.org>
11
+
12
+
description:
13
+
IR LED connected through PWM pin which is used as remote controller
14
+
transmitter.
15
+
16
+
properties:
17
+
compatible:
18
+
const: pwm-ir-tx
19
+
20
+
pwms:
21
+
maxItems: 1
22
+
23
+
required:
24
+
- compatible
25
+
- pwms
26
+
27
+
additionalProperties: false
28
+
29
+
examples:
30
+
- |
31
+
irled {
32
+
compatible = "pwm-ir-tx";
33
+
pwms = <&pwm0 0 10000000>;
34
+
};
-29
Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt
-29
Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt
···
1
-
Device tree bindings for IR LED connected through SPI bus which is used as
2
-
remote controller.
3
-
4
-
The IR LED switch is connected to the MOSI line of the SPI device and the data
5
-
are delivered thourgh that.
6
-
7
-
Required properties:
8
-
- compatible: should be "ir-spi-led".
9
-
10
-
Optional properties:
11
-
- duty-cycle: 8 bit value that represents the percentage of one period
12
-
in which the signal is active. It can be 50, 60, 70, 75, 80 or 90.
13
-
- led-active-low: boolean value that specifies whether the output is
14
-
negated with a NOT gate.
15
-
- power-supply: specifies the power source. It can either be a regulator
16
-
or a gpio which enables a regulator, i.e. a regulator-fixed as
17
-
described in
18
-
Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
19
-
20
-
Example:
21
-
22
-
irled@0 {
23
-
compatible = "ir-spi-led";
24
-
reg = <0x0>;
25
-
spi-max-frequency = <5000000>;
26
-
power-supply = <&vdd_led>;
27
-
led-active-low;
28
-
duty-cycle = /bits/ 8 <60>;
29
-
};
+1
Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml
+1
Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml
+1
Documentation/devicetree/bindings/leds/leds-aw2013.yaml
+1
Documentation/devicetree/bindings/leds/leds-aw2013.yaml
+1
-1
Documentation/devicetree/bindings/leds/leds-gpio.yaml
+1
-1
Documentation/devicetree/bindings/leds/leds-gpio.yaml
+7
-3
Documentation/devicetree/bindings/leds/leds-lgm.yaml
+7
-3
Documentation/devicetree/bindings/leds/leds-lgm.yaml
···
56
56
57
57
patternProperties:
58
58
"^led@[0-2]$":
59
-
type: object
59
+
$ref: common.yaml#
60
+
unevaluatedProperties: false
60
61
61
62
properties:
62
63
reg:
63
64
description: Index of the LED.
64
65
minimum: 0
65
66
maximum: 2
67
+
68
+
led-gpios:
69
+
maxItems: 1
66
70
67
71
intel,sso-hw-trigger:
68
72
type: boolean
···
122
118
reg = <0>;
123
119
function = "gphy";
124
120
color = <LED_COLOR_ID_GREEN>;
125
-
led-gpio = <&ssogpio 0 0>;
121
+
led-gpios = <&ssogpio 0 0>;
126
122
};
127
123
128
124
led@2 {
129
125
reg = <2>;
130
126
function = LED_FUNCTION_POWER;
131
127
color = <LED_COLOR_ID_GREEN>;
132
-
led-gpio = <&ssogpio 23 0>;
128
+
led-gpios = <&ssogpio 23 0>;
133
129
};
134
130
};
135
131
};
+8
Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
+8
Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
+45
-2
Documentation/devicetree/bindings/leds/leds-lp55xx.yaml
+45
-2
Documentation/devicetree/bindings/leds/leds-lp55xx.yaml
···
43
43
- 1 # internal
44
44
- 2 # external
45
45
46
-
enable-gpio:
46
+
enable-gpios:
47
47
maxItems: 1
48
48
description: |
49
49
GPIO attached to the chip's enable pin
50
+
51
+
label: true
50
52
51
53
pwr-sel:
52
54
$ref: /schemas/types.yaml#/definitions/uint8
···
67
65
const: 0
68
66
69
67
patternProperties:
70
-
"(^led@[0-9a-f]$|led)":
68
+
'^multi-led@[0-8]$':
69
+
type: object
70
+
$ref: leds-class-multicolor.yaml#
71
+
unevaluatedProperties: false
72
+
73
+
properties:
74
+
reg:
75
+
maximum: 8
76
+
77
+
'#address-cells':
78
+
const: 1
79
+
80
+
'#size-cells':
81
+
const: 0
82
+
83
+
patternProperties:
84
+
"^led@[0-8]$":
85
+
type: object
86
+
$ref: common.yaml#
87
+
unevaluatedProperties: false
88
+
89
+
properties:
90
+
led-cur:
91
+
$ref: /schemas/types.yaml#/definitions/uint8
92
+
description: |
93
+
Current setting at each LED channel (mA x10, 0 if LED is not connected)
94
+
minimum: 0
95
+
maximum: 255
96
+
97
+
max-cur:
98
+
$ref: /schemas/types.yaml#/definitions/uint8
99
+
description: Maximun current at each LED channel.
100
+
101
+
reg:
102
+
maximum: 8
103
+
104
+
required:
105
+
- reg
106
+
107
+
"^led@[0-8]$":
71
108
type: object
72
109
$ref: common.yaml#
110
+
unevaluatedProperties: false
111
+
73
112
properties:
74
113
led-cur:
75
114
$ref: /schemas/types.yaml#/definitions/uint8
+2
-7
Documentation/devicetree/bindings/leds/leds-max77650.yaml
+2
-7
Documentation/devicetree/bindings/leds/leds-max77650.yaml
···
30
30
31
31
patternProperties:
32
32
"^led@[0-2]$":
33
-
type: object
34
-
description: |
35
-
Properties for a single LED.
33
+
$ref: common.yaml#
34
+
unevaluatedProperties: false
36
35
37
36
properties:
38
37
reg:
···
39
40
Index of the LED.
40
41
minimum: 0
41
42
maximum: 2
42
-
43
-
label: true
44
-
45
-
linux,default-trigger: true
46
43
47
44
required:
48
45
- compatible
+39
-4
Documentation/devicetree/bindings/leds/leds-mt6360.yaml
+39
-4
Documentation/devicetree/bindings/leds/leds-mt6360.yaml
···
26
26
const: 0
27
27
28
28
patternProperties:
29
-
"^(multi-)?led@[0-5]$":
29
+
"^multi-led@[0-5]$":
30
30
type: object
31
-
$ref: common.yaml#
32
-
description:
33
-
Properties for a single LED.
31
+
$ref: leds-class-multicolor.yaml#
32
+
unevaluatedProperties: false
34
33
35
34
properties:
36
35
reg:
···
41
42
- 3 # LED output ISINKML
42
43
- 4 # LED output FLASH1
43
44
- 5 # LED output FLASH2
45
+
46
+
"#address-cells":
47
+
const: 1
48
+
49
+
"#size-cells":
50
+
const: 0
51
+
52
+
patternProperties:
53
+
"^led@[0-2]$":
54
+
type: object
55
+
$ref: common.yaml#
56
+
unevaluatedProperties: false
57
+
58
+
properties:
59
+
reg:
60
+
enum: [0, 1, 2]
61
+
62
+
required:
63
+
- reg
64
+
- color
65
+
66
+
required:
67
+
- reg
68
+
- "#address-cells"
69
+
- "#size-cells"
70
+
71
+
"^led@[0-5]$":
72
+
type: object
73
+
$ref: common.yaml#
74
+
unevaluatedProperties: false
75
+
description:
76
+
Properties for a single LED.
77
+
78
+
properties:
79
+
reg:
80
+
enum: [0, 1, 2, 3, 4, 5]
44
81
45
82
required:
46
83
- compatible
+1
-1
Documentation/devicetree/bindings/leds/leds-pwm.yaml
+1
-1
Documentation/devicetree/bindings/leds/leds-pwm.yaml
+11
-1
Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml
+11
-1
Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml
···
72
72
"^led@[0-9a-f]$":
73
73
type: object
74
74
$ref: common.yaml#
75
+
unevaluatedProperties: false
76
+
77
+
properties:
78
+
reg:
79
+
maxItems: 1
80
+
81
+
required:
82
+
- reg
75
83
76
84
patternProperties:
77
85
"^led@[0-9a-f]$":
78
86
type: object
79
87
$ref: common.yaml#
88
+
unevaluatedProperties: false
80
89
81
90
properties:
82
-
reg: true
91
+
reg:
92
+
maxItems: 1
83
93
84
94
required:
85
95
- reg
+1
Documentation/devicetree/bindings/leds/leds-rt4505.yaml
+1
Documentation/devicetree/bindings/leds/leds-rt4505.yaml
+4
-1
Documentation/devicetree/bindings/leds/leds-sgm3140.yaml
+4
-1
Documentation/devicetree/bindings/leds/leds-sgm3140.yaml
···
18
18
19
19
properties:
20
20
compatible:
21
-
const: sgmicro,sgm3140
21
+
enum:
22
+
- ocs,ocp8110
23
+
- sgmicro,sgm3140
22
24
23
25
enable-gpios:
24
26
maxItems: 1
···
36
34
led:
37
35
type: object
38
36
$ref: common.yaml#
37
+
unevaluatedProperties: false
39
38
40
39
required:
41
40
- compatible
+3
-13
Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
+3
-13
Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
···
26
26
27
27
patternProperties:
28
28
"^led-[1-2]$":
29
-
type: object
30
-
description:
31
-
Properties for a single LED.
29
+
$ref: common.yaml#
30
+
unevaluatedProperties: false
31
+
32
32
properties:
33
-
#allOf:
34
-
#- $ref: "common.yaml#"
35
33
rohm,led-compatible:
36
34
description: LED identification string
37
35
$ref: "/schemas/types.yaml#/definitions/string"
38
36
enum:
39
37
- bd71828-ambled
40
38
- bd71828-grnled
41
-
function:
42
-
description:
43
-
Purpose of LED as defined in dt-bindings/leds/common.h
44
-
$ref: "/schemas/types.yaml#/definitions/string"
45
-
color:
46
-
description:
47
-
LED colour as defined in dt-bindings/leds/common.h
48
-
$ref: "/schemas/types.yaml#/definitions/uint32"
49
39
50
40
required:
51
41
- compatible
+1
-1
Documentation/devicetree/bindings/leds/ti,tca6507.yaml
+1
-1
Documentation/devicetree/bindings/leds/ti,tca6507.yaml
+1
-3
Documentation/devicetree/bindings/media/atmel,isc.yaml
+1
-3
Documentation/devicetree/bindings/media/atmel,isc.yaml
···
45
45
46
46
port:
47
47
$ref: /schemas/graph.yaml#/$defs/port-base
48
-
unevaluatedProperties: false
48
+
additionalProperties: false
49
49
description:
50
50
Input port node, single endpoint describing the input pad.
51
51
···
76
76
- remote-endpoint
77
77
78
78
additionalProperties: false
79
-
80
-
additionalProperties: false
81
79
82
80
required:
83
81
- compatible
-82
Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
-82
Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
···
1
-
STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
2
-
3
-
MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4
-
time. Active port input stream will be de-serialized and its content outputted
5
-
through PARALLEL output port.
6
-
CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7
-
input port is a single lane 800Mbps. Both ports support clock and data lane
8
-
polarity swap. First port also supports data lane swap.
9
-
PARALLEL output port has a maximum width of 12 bits.
10
-
Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
11
-
YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
12
-
13
-
Required Properties:
14
-
- compatible: shall be "st,st-mipid02"
15
-
- clocks: reference to the xclk input clock.
16
-
- clock-names: shall be "xclk".
17
-
- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
18
-
- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
19
-
20
-
Optional Properties:
21
-
- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
22
-
This is an active low signal to the mipid02.
23
-
24
-
Required subnodes:
25
-
- ports: A ports node with one port child node per device input and output
26
-
port, in accordance with the video interface bindings defined in
27
-
Documentation/devicetree/bindings/media/video-interfaces.txt. The
28
-
port nodes are numbered as follows:
29
-
30
-
Port Description
31
-
-----------------------------
32
-
0 CSI-2 first input port
33
-
1 CSI-2 second input port
34
-
2 PARALLEL output
35
-
36
-
Endpoint node required property for CSI-2 connection is:
37
-
- data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38
-
<1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
39
-
Endpoint node optional property for CSI-2 connection is:
40
-
- lane-polarities: any lane can be inverted or not.
41
-
42
-
Endpoint node required property for PARALLEL connection is:
43
-
- bus-width: shall be set to <6>, <7>, <8>, <10> or <12>.
44
-
Endpoint node optional properties for PARALLEL connection are:
45
-
- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
46
-
LOW being the default.
47
-
- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
48
-
LOW being the default.
49
-
50
-
Example:
51
-
52
-
mipid02: csi2rx@14 {
53
-
compatible = "st,st-mipid02";
54
-
reg = <0x14>;
55
-
status = "okay";
56
-
clocks = <&clk_ext_camera_12>;
57
-
clock-names = "xclk";
58
-
VDDE-supply = <&vdd>;
59
-
VDDIN-supply = <&vdd>;
60
-
ports {
61
-
#address-cells = <1>;
62
-
#size-cells = <0>;
63
-
port@0 {
64
-
reg = <0>;
65
-
66
-
ep0: endpoint {
67
-
data-lanes = <1 2>;
68
-
remote-endpoint = <&mipi_csi2_in>;
69
-
};
70
-
};
71
-
port@2 {
72
-
reg = <2>;
73
-
74
-
ep2: endpoint {
75
-
bus-width = <8>;
76
-
hsync-active = <0>;
77
-
vsync-active = <0>;
78
-
remote-endpoint = <¶llel_out>;
79
-
};
80
-
};
81
-
};
82
-
};
+176
Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml
+176
Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
8
+
9
+
maintainers:
10
+
- Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11
+
- Sylvain Petinot <sylvain.petinot@foss.st.com>
12
+
13
+
description:
14
+
MIPID02 has two CSI-2 input ports, only one of those ports can be
15
+
active at a time. Active port input stream will be de-serialized
16
+
and its content outputted through PARALLEL output port.
17
+
CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
18
+
second input port is a single lane 800Mbps. Both ports support clock
19
+
and data lane polarity swap. First port also supports data lane swap.
20
+
PARALLEL output port has a maximum width of 12 bits.
21
+
Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888,
22
+
RGB444, YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
23
+
24
+
properties:
25
+
compatible:
26
+
const: st,st-mipid02
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
clocks:
32
+
maxItems: 1
33
+
34
+
clock-names:
35
+
const: xclk
36
+
37
+
VDDE-supply:
38
+
description:
39
+
Sensor digital IO supply. Must be 1.8 volts.
40
+
41
+
VDDIN-supply:
42
+
description:
43
+
Sensor internal regulator supply. Must be 1.8 volts.
44
+
45
+
reset-gpios:
46
+
description:
47
+
Reference to the GPIO connected to the xsdn pin, if any.
48
+
This is an active low signal to the mipid02.
49
+
50
+
ports:
51
+
$ref: /schemas/graph.yaml#/properties/ports
52
+
properties:
53
+
port@0:
54
+
$ref: /schemas/graph.yaml#/$defs/port-base
55
+
unevaluatedProperties: false
56
+
description: CSI-2 first input port
57
+
properties:
58
+
endpoint:
59
+
$ref: /schemas/media/video-interfaces.yaml#
60
+
unevaluatedProperties: false
61
+
62
+
properties:
63
+
data-lanes:
64
+
description:
65
+
Single-lane operation shall be <1> or <2> .
66
+
Dual-lane operation shall be <1 2> or <2 1> .
67
+
minItems: 1
68
+
maxItems: 2
69
+
70
+
lane-polarities:
71
+
description:
72
+
Any lane can be inverted or not.
73
+
minItems: 1
74
+
maxItems: 2
75
+
76
+
required:
77
+
- data-lanes
78
+
79
+
port@1:
80
+
$ref: /schemas/graph.yaml#/$defs/port-base
81
+
unevaluatedProperties: false
82
+
description: CSI-2 second input port
83
+
properties:
84
+
endpoint:
85
+
$ref: /schemas/media/video-interfaces.yaml#
86
+
unevaluatedProperties: false
87
+
88
+
properties:
89
+
data-lanes:
90
+
description:
91
+
Single-lane operation shall be <1> or <2> .
92
+
maxItems: 1
93
+
94
+
lane-polarities:
95
+
description:
96
+
Any lane can be inverted or not.
97
+
maxItems: 1
98
+
99
+
required:
100
+
- data-lanes
101
+
102
+
port@2:
103
+
$ref: /schemas/graph.yaml#/$defs/port-base
104
+
unevaluatedProperties: false
105
+
description: Output port
106
+
properties:
107
+
endpoint:
108
+
$ref: /schemas/media/video-interfaces.yaml#
109
+
unevaluatedProperties: false
110
+
111
+
properties:
112
+
bus-width:
113
+
enum: [6, 7, 8, 10, 12]
114
+
115
+
required:
116
+
- bus-width
117
+
118
+
anyOf:
119
+
- required:
120
+
- port@0
121
+
- required:
122
+
- port@1
123
+
124
+
required:
125
+
- port@2
126
+
127
+
additionalProperties: false
128
+
129
+
required:
130
+
- compatible
131
+
- reg
132
+
- clocks
133
+
- clock-names
134
+
- VDDE-supply
135
+
- VDDIN-supply
136
+
- ports
137
+
138
+
examples:
139
+
- |
140
+
i2c {
141
+
#address-cells = <1>;
142
+
#size-cells = <0>;
143
+
mipid02: csi2rx@14 {
144
+
compatible = "st,st-mipid02";
145
+
reg = <0x14>;
146
+
status = "okay";
147
+
clocks = <&clk_ext_camera_12>;
148
+
clock-names = "xclk";
149
+
VDDE-supply = <&vdd>;
150
+
VDDIN-supply = <&vdd>;
151
+
ports {
152
+
#address-cells = <1>;
153
+
#size-cells = <0>;
154
+
port@0 {
155
+
reg = <0>;
156
+
157
+
ep0: endpoint {
158
+
data-lanes = <1 2>;
159
+
remote-endpoint = <&mipi_csi2_in>;
160
+
};
161
+
};
162
+
port@2 {
163
+
reg = <2>;
164
+
165
+
ep2: endpoint {
166
+
bus-width = <8>;
167
+
hsync-active = <0>;
168
+
vsync-active = <0>;
169
+
remote-endpoint = <¶llel_out>;
170
+
};
171
+
};
172
+
};
173
+
};
174
+
};
175
+
176
+
...
+72
Documentation/devicetree/bindings/misc/idt,89hpesx.yaml
+72
Documentation/devicetree/bindings/misc/idt,89hpesx.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/misc/idt,89hpesx.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
8
+
9
+
maintainers:
10
+
- Serge Semin <fancer.lancer@gmail.com>
11
+
12
+
select:
13
+
properties:
14
+
compatible:
15
+
contains:
16
+
pattern: '^idt,89hpes'
17
+
required:
18
+
- compatible
19
+
20
+
properties:
21
+
compatible:
22
+
oneOf:
23
+
- pattern: '^idt,89hpes(8nt2|12nt3|12n3a?|24n3a?|(12|24)t3g2|4t4g2|10t4g2|[56]t5|8t5a?)$'
24
+
- pattern: '^idt,89hpes(6t6g2|16t7|(24t6|32t8|48t12|16t4a?)(g2)?)$'
25
+
- pattern: '^idt,89hpes(24nt6a|32nt8[ab]|12nt12|16nt16|24nt24|32nt24[ab])g2$'
26
+
- pattern: '^idt,89hpes((32h8|48h12a?|22h16|34h16|64h16a?)(g2)?|16h16)$'
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
'#address-cells':
32
+
const: 1
33
+
34
+
'#size-cells':
35
+
const: 0
36
+
37
+
patternProperties:
38
+
'^eeprom@':
39
+
$ref: /schemas/eeprom/at24.yaml#
40
+
unevaluatedProperties: false
41
+
42
+
properties:
43
+
compatible:
44
+
description: Only a subset of devices are supported
45
+
pattern: ',24c(32|64|128|256|512)$'
46
+
47
+
required:
48
+
- compatible
49
+
- reg
50
+
51
+
additionalProperties: false
52
+
53
+
examples:
54
+
- |
55
+
i2c {
56
+
#address-cells = <1>;
57
+
#size-cells = <0>;
58
+
59
+
idt@74 {
60
+
compatible = "idt,89hpes32nt8ag2";
61
+
reg = <0x74>;
62
+
#address-cells = <1>;
63
+
#size-cells = <0>;
64
+
65
+
eeprom@50 {
66
+
compatible = "atmel,24c64";
67
+
reg = <0x50>;
68
+
read-only;
69
+
};
70
+
};
71
+
};
72
+
...
-44
Documentation/devicetree/bindings/misc/idt_89hpesx.txt
-44
Documentation/devicetree/bindings/misc/idt_89hpesx.txt
···
1
-
EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
2
-
3
-
Required properties:
4
-
- compatible : should be "<manufacturer>,<type>"
5
-
Basically there is only one manufacturer: idt, but some
6
-
compatible devices may be produced in future. Following devices
7
-
are supported: 89hpes8nt2, 89hpes12nt3, 89hpes24nt6ag2,
8
-
89hpes32nt8ag2, 89hpes32nt8bg2, 89hpes12nt12g2, 89hpes16nt16g2,
9
-
89hpes24nt24g2, 89hpes32nt24ag2, 89hpes32nt24bg2;
10
-
89hpes12n3, 89hpes12n3a, 89hpes24n3, 89hpes24n3a;
11
-
89hpes32h8, 89hpes32h8g2, 89hpes48h12, 89hpes48h12g2,
12
-
89hpes48h12ag2, 89hpes16h16, 89hpes22h16, 89hpes22h16g2,
13
-
89hpes34h16, 89hpes34h16g2, 89hpes64h16, 89hpes64h16g2,
14
-
89hpes64h16ag2;
15
-
89hpes12t3g2, 89hpes24t3g2, 89hpes16t4, 89hpes4t4g2,
16
-
89hpes10t4g2, 89hpes16t4g2, 89hpes16t4ag2, 89hpes5t5,
17
-
89hpes6t5, 89hpes8t5, 89hpes8t5a, 89hpes24t6, 89hpes6t6g2,
18
-
89hpes24t6g2, 89hpes16t7, 89hpes32t8, 89hpes32t8g2,
19
-
89hpes48t12, 89hpes48t12g2.
20
-
- reg : I2C address of the IDT 89HPESx device.
21
-
22
-
Optionally there can be EEPROM-compatible subnode:
23
-
- compatible: There are five EEPROM devices supported: 24c32, 24c64, 24c128,
24
-
24c256 and 24c512 differed by size.
25
-
- reg: Custom address of EEPROM device (If not specified IDT 89HPESx
26
-
(optional) device will try to communicate with EEPROM sited by default
27
-
address - 0x50)
28
-
- read-only : Parameterless property disables writes to the EEPROM
29
-
(optional)
30
-
31
-
Example:
32
-
idt@60 {
33
-
compatible = "idt,89hpes32nt8ag2";
34
-
reg = <0x74>;
35
-
#address-cells = <1>;
36
-
#size-cells = <0>;
37
-
38
-
eeprom@50 {
39
-
compatible = "onsemi,24c64";
40
-
reg = <0x50>;
41
-
read-only;
42
-
};
43
-
};
44
-
+7
Documentation/devicetree/bindings/mtd/partitions/u-boot.yaml
+7
Documentation/devicetree/bindings/mtd/partitions/u-boot.yaml
···
27
27
Broadcom stores environment variables inside a U-Boot partition. They
28
28
can be identified by a custom header with magic value.
29
29
30
+
patternProperties:
31
+
"^partition-.*$":
32
+
$ref: partition.yaml#
33
+
30
34
unevaluatedProperties: false
31
35
32
36
examples:
···
44
40
compatible = "brcm,u-boot";
45
41
reg = <0x0 0x100000>;
46
42
label = "u-boot";
43
+
44
+
partition-u-boot-env {
45
+
};
47
46
};
48
47
49
48
partition@100000 {
-1
Documentation/devicetree/bindings/net/cdns,macb.yaml
-1
Documentation/devicetree/bindings/net/cdns,macb.yaml
-1
Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml
-1
Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml
+21
Documentation/devicetree/bindings/nvmem/u-boot,env.yaml
+21
Documentation/devicetree/bindings/nvmem/u-boot,env.yaml
···
38
38
const: u-boot,env-redundant-bool
39
39
- description: Two redundant blocks with active having higher counter
40
40
const: u-boot,env-redundant-count
41
+
- description: Broadcom's variant with custom header
42
+
const: brcm,env
41
43
42
44
reg:
43
45
maxItems: 1
···
72
70
reg = <0x40000 0x10000>;
73
71
74
72
mac: ethaddr {
73
+
};
74
+
};
75
+
};
76
+
- |
77
+
partitions {
78
+
compatible = "fixed-partitions";
79
+
#address-cells = <1>;
80
+
#size-cells = <1>;
81
+
82
+
partition@0 {
83
+
reg = <0x0 0x100000>;
84
+
compatible = "brcm,u-boot";
85
+
label = "u-boot";
86
+
87
+
partition-u-boot-env {
88
+
compatible = "brcm,env";
89
+
90
+
ethaddr {
91
+
};
75
92
};
76
93
};
77
94
};
+2
-2
Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
+2
-2
Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
···
41
41
- nvmem-cells
42
42
43
43
patternProperties:
44
-
"opp-[0-9]+":
44
+
"^opp-[0-9]+$":
45
45
type: object
46
46
47
47
properties:
···
49
49
clock-latency-ns: true
50
50
51
51
patternProperties:
52
-
"opp-microvolt-.*": true
52
+
"^opp-microvolt-speed[0-9]$": true
53
53
54
54
required:
55
55
- opp-hz
+1
-1
Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
+1
-1
Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
+1
-1
Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
+1
-1
Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
-73
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
-73
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
···
1
-
* Xilinx NWL PCIe Root Port Bridge DT description
2
-
3
-
Required properties:
4
-
- compatible: Should contain "xlnx,nwl-pcie-2.11"
5
-
- #address-cells: Address representation for root ports, set to <3>
6
-
- #size-cells: Size representation for root ports, set to <2>
7
-
- #interrupt-cells: specifies the number of cells needed to encode an
8
-
interrupt source. The value must be 1.
9
-
- reg: Should contain Bridge, PCIe Controller registers location,
10
-
configuration space, and length
11
-
- reg-names: Must include the following entries:
12
-
"breg": bridge registers
13
-
"pcireg": PCIe controller registers
14
-
"cfg": configuration space region
15
-
- device_type: must be "pci"
16
-
- interrupts: Should contain NWL PCIe interrupt
17
-
- interrupt-names: Must include the following entries:
18
-
"msi1, msi0": interrupt asserted when an MSI is received
19
-
"intx": interrupt asserted when a legacy interrupt is received
20
-
"misc": interrupt asserted when miscellaneous interrupt is received
21
-
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
22
-
mapping of the PCI interface to interrupt numbers.
23
-
- ranges: ranges for the PCI memory regions (I/O space region is not
24
-
supported by hardware)
25
-
Please refer to the standard PCI bus binding document for a more
26
-
detailed explanation
27
-
- msi-controller: indicates that this is MSI controller node
28
-
- msi-parent: MSI parent of the root complex itself
29
-
- legacy-interrupt-controller: Interrupt controller device node for Legacy
30
-
interrupts
31
-
- interrupt-controller: identifies the node as an interrupt controller
32
-
- #interrupt-cells: should be set to 1
33
-
- #address-cells: specifies the number of cells needed to encode an
34
-
address. The value must be 0.
35
-
36
-
Optional properties:
37
-
- dma-coherent: present if DMA operations are coherent
38
-
- clocks: Input clock specifier. Refer to common clock bindings
39
-
40
-
Example:
41
-
++++++++
42
-
43
-
nwl_pcie: pcie@fd0e0000 {
44
-
#address-cells = <3>;
45
-
#size-cells = <2>;
46
-
compatible = "xlnx,nwl-pcie-2.11";
47
-
#interrupt-cells = <1>;
48
-
msi-controller;
49
-
device_type = "pci";
50
-
interrupt-parent = <&gic>;
51
-
interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
52
-
interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
53
-
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
54
-
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
55
-
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
56
-
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
57
-
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
58
-
59
-
msi-parent = <&nwl_pcie>;
60
-
reg = <0x0 0xfd0e0000 0x0 0x1000>,
61
-
<0x0 0xfd480000 0x0 0x1000>,
62
-
<0x80 0x00000000 0x0 0x1000000>;
63
-
reg-names = "breg", "pcireg", "cfg";
64
-
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
65
-
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
66
-
67
-
pcie_intc: legacy-interrupt-controller {
68
-
interrupt-controller;
69
-
#address-cells = <0>;
70
-
#interrupt-cells = <1>;
71
-
};
72
-
73
-
};
-88
Documentation/devicetree/bindings/pci/xilinx-pcie.txt
-88
Documentation/devicetree/bindings/pci/xilinx-pcie.txt
···
1
-
* Xilinx AXI PCIe Root Port Bridge DT description
2
-
3
-
Required properties:
4
-
- #address-cells: Address representation for root ports, set to <3>
5
-
- #size-cells: Size representation for root ports, set to <2>
6
-
- #interrupt-cells: specifies the number of cells needed to encode an
7
-
interrupt source. The value must be 1.
8
-
- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9
-
- reg: Should contain AXI PCIe registers location and length
10
-
- device_type: must be "pci"
11
-
- interrupts: Should contain AXI PCIe interrupt
12
-
- interrupt-map-mask,
13
-
interrupt-map: standard PCI properties to define the mapping of the
14
-
PCI interface to interrupt numbers.
15
-
- ranges: ranges for the PCI memory regions (I/O space region is not
16
-
supported by hardware)
17
-
Please refer to the standard PCI bus binding document for a more
18
-
detailed explanation
19
-
20
-
Optional properties for Zynq/Microblaze:
21
-
- bus-range: PCI bus numbers covered
22
-
23
-
Interrupt controller child node
24
-
+++++++++++++++++++++++++++++++
25
-
Required properties:
26
-
- interrupt-controller: identifies the node as an interrupt controller
27
-
- #address-cells: specifies the number of cells needed to encode an
28
-
address. The value must be 0.
29
-
- #interrupt-cells: specifies the number of cells needed to encode an
30
-
interrupt source. The value must be 1.
31
-
32
-
NOTE:
33
-
The core provides a single interrupt for both INTx/MSI messages. So,
34
-
created a interrupt controller node to support 'interrupt-map' DT
35
-
functionality. The driver will create an IRQ domain for this map, decode
36
-
the four INTx interrupts in ISR and route them to this domain.
37
-
38
-
39
-
Example:
40
-
++++++++
41
-
Zynq:
42
-
pci_express: axi-pcie@50000000 {
43
-
#address-cells = <3>;
44
-
#size-cells = <2>;
45
-
#interrupt-cells = <1>;
46
-
compatible = "xlnx,axi-pcie-host-1.00.a";
47
-
reg = < 0x50000000 0x1000000 >;
48
-
device_type = "pci";
49
-
interrupts = < 0 52 4 >;
50
-
interrupt-map-mask = <0 0 0 7>;
51
-
interrupt-map = <0 0 0 1 &pcie_intc 1>,
52
-
<0 0 0 2 &pcie_intc 2>,
53
-
<0 0 0 3 &pcie_intc 3>,
54
-
<0 0 0 4 &pcie_intc 4>;
55
-
ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
56
-
57
-
pcie_intc: interrupt-controller {
58
-
interrupt-controller;
59
-
#address-cells = <0>;
60
-
#interrupt-cells = <1>;
61
-
};
62
-
};
63
-
64
-
65
-
Microblaze:
66
-
pci_express: axi-pcie@10000000 {
67
-
#address-cells = <3>;
68
-
#size-cells = <2>;
69
-
#interrupt-cells = <1>;
70
-
compatible = "xlnx,axi-pcie-host-1.00.a";
71
-
reg = <0x10000000 0x4000000>;
72
-
device_type = "pci";
73
-
interrupt-parent = <µblaze_0_intc>;
74
-
interrupts = <1 2>;
75
-
interrupt-map-mask = <0 0 0 7>;
76
-
interrupt-map = <0 0 0 1 &pcie_intc 1>,
77
-
<0 0 0 2 &pcie_intc 2>,
78
-
<0 0 0 3 &pcie_intc 3>,
79
-
<0 0 0 4 &pcie_intc 4>;
80
-
ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
81
-
82
-
pcie_intc: interrupt-controller {
83
-
interrupt-controller;
84
-
#address-cells = <0>;
85
-
#interrupt-cells = <1>;
86
-
};
87
-
88
-
};
+88
Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml
+88
Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Xilinx AXI PCIe Root Port Bridge
8
+
9
+
maintainers:
10
+
- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/pci/pci-bus.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: xlnx,axi-pcie-host-1.00.a
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
interrupts:
23
+
maxItems: 1
24
+
25
+
ranges:
26
+
items:
27
+
- description: |
28
+
ranges for the PCI memory regions (I/O space region is not
29
+
supported by hardware)
30
+
31
+
"#interrupt-cells":
32
+
const: 1
33
+
34
+
interrupt-controller:
35
+
description: identifies the node as an interrupt controller
36
+
type: object
37
+
properties:
38
+
interrupt-controller: true
39
+
40
+
"#address-cells":
41
+
const: 0
42
+
43
+
"#interrupt-cells":
44
+
const: 1
45
+
46
+
required:
47
+
- interrupt-controller
48
+
- "#address-cells"
49
+
- "#interrupt-cells"
50
+
51
+
additionalProperties: false
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
- ranges
57
+
- interrupts
58
+
- interrupt-map
59
+
- "#interrupt-cells"
60
+
- interrupt-controller
61
+
62
+
unevaluatedProperties: false
63
+
64
+
examples:
65
+
- |
66
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
67
+
#include <dt-bindings/interrupt-controller/irq.h>
68
+
69
+
pcie@50000000 {
70
+
compatible = "xlnx,axi-pcie-host-1.00.a";
71
+
reg = <0x50000000 0x1000000>;
72
+
#address-cells = <3>;
73
+
#size-cells = <2>;
74
+
#interrupt-cells = <1>;
75
+
device_type = "pci";
76
+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
77
+
interrupt-map-mask = <0 0 0 7>;
78
+
interrupt-map = <0 0 0 1 &pcie_intc 1>,
79
+
<0 0 0 2 &pcie_intc 2>,
80
+
<0 0 0 3 &pcie_intc 3>,
81
+
<0 0 0 4 &pcie_intc 4>;
82
+
ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>;
83
+
pcie_intc: interrupt-controller {
84
+
interrupt-controller;
85
+
#address-cells = <0>;
86
+
#interrupt-cells = <1>;
87
+
};
88
+
};
+149
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
+149
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Xilinx NWL PCIe Root Port Bridge
8
+
9
+
maintainers:
10
+
- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/pci/pci-bus.yaml#
14
+
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: xlnx,nwl-pcie-2.11
19
+
20
+
reg:
21
+
items:
22
+
- description: PCIe bridge registers location.
23
+
- description: PCIe Controller registers location.
24
+
- description: PCIe Configuration space region.
25
+
26
+
reg-names:
27
+
items:
28
+
- const: breg
29
+
- const: pcireg
30
+
- const: cfg
31
+
32
+
interrupts:
33
+
items:
34
+
- description: interrupt asserted when miscellaneous interrupt is received
35
+
- description: unused interrupt(dummy)
36
+
- description: interrupt asserted when a legacy interrupt is received
37
+
- description: msi1 interrupt asserted when an MSI is received
38
+
- description: msi0 interrupt asserted when an MSI is received
39
+
40
+
interrupt-names:
41
+
items:
42
+
- const: misc
43
+
- const: dummy
44
+
- const: intx
45
+
- const: msi1
46
+
- const: msi0
47
+
48
+
interrupt-map-mask:
49
+
items:
50
+
- const: 0
51
+
- const: 0
52
+
- const: 0
53
+
- const: 7
54
+
55
+
"#interrupt-cells":
56
+
const: 1
57
+
58
+
msi-parent:
59
+
description: MSI controller the device is capable of using.
60
+
61
+
interrupt-map:
62
+
maxItems: 4
63
+
64
+
power-domains:
65
+
maxItems: 1
66
+
67
+
iommus:
68
+
maxItems: 1
69
+
70
+
dma-coherent:
71
+
description: optional, only needed if DMA operations are coherent.
72
+
73
+
clocks:
74
+
maxItems: 1
75
+
description: optional, input clock specifier.
76
+
77
+
legacy-interrupt-controller:
78
+
description: Interrupt controller node for handling legacy PCI interrupts.
79
+
type: object
80
+
properties:
81
+
"#address-cells":
82
+
const: 0
83
+
84
+
"#interrupt-cells":
85
+
const: 1
86
+
87
+
"interrupt-controller": true
88
+
89
+
required:
90
+
- "#address-cells"
91
+
- "#interrupt-cells"
92
+
- interrupt-controller
93
+
94
+
additionalProperties: false
95
+
96
+
required:
97
+
- compatible
98
+
- reg
99
+
- reg-names
100
+
- interrupts
101
+
- "#interrupt-cells"
102
+
- interrupt-map
103
+
- interrupt-map-mask
104
+
- msi-controller
105
+
- power-domains
106
+
107
+
unevaluatedProperties: false
108
+
109
+
examples:
110
+
- |
111
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
112
+
#include <dt-bindings/interrupt-controller/irq.h>
113
+
#include <dt-bindings/power/xlnx-zynqmp-power.h>
114
+
soc {
115
+
#address-cells = <2>;
116
+
#size-cells = <2>;
117
+
nwl_pcie: pcie@fd0e0000 {
118
+
compatible = "xlnx,nwl-pcie-2.11";
119
+
reg = <0x0 0xfd0e0000 0x0 0x1000>,
120
+
<0x0 0xfd480000 0x0 0x1000>,
121
+
<0x80 0x00000000 0x0 0x1000000>;
122
+
reg-names = "breg", "pcireg", "cfg";
123
+
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
124
+
<0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
125
+
#address-cells = <3>;
126
+
#size-cells = <2>;
127
+
#interrupt-cells = <1>;
128
+
msi-controller;
129
+
device_type = "pci";
130
+
interrupt-parent = <&gic>;
131
+
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
132
+
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
133
+
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
134
+
interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
135
+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
136
+
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
137
+
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
138
+
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
139
+
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
140
+
msi-parent = <&nwl_pcie>;
141
+
power-domains = <&zynqmp_firmware PD_PCIE>;
142
+
iommus = <&smmu 0x4d0>;
143
+
pcie_intc: legacy-interrupt-controller {
144
+
interrupt-controller;
145
+
#address-cells = <0>;
146
+
#interrupt-cells = <1>;
147
+
};
148
+
};
149
+
};
-3
Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
-3
Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
+7
-8
Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml
+7
-8
Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml
···
36
36
37
37
examples:
38
38
- |
39
-
mmc_phy@80440800 {
40
-
#phy-cells = <0x0>;
41
-
compatible = "intel,thunderbay-emmc-phy";
42
-
status = "okay";
43
-
reg = <0x80440800 0x100>;
44
-
clocks = <&emmc>;
45
-
clock-names = "emmcclk";
46
-
};
39
+
mmc_phy@80440800 {
40
+
#phy-cells = <0x0>;
41
+
compatible = "intel,thunderbay-emmc-phy";
42
+
reg = <0x80440800 0x100>;
43
+
clocks = <&emmc>;
44
+
clock-names = "emmcclk";
45
+
};
+2
-4
Documentation/devicetree/bindings/power/renesas,apmu.yaml
+2
-4
Documentation/devicetree/bindings/power/renesas,apmu.yaml
···
34
34
maxItems: 1
35
35
36
36
cpus:
37
-
$ref: /schemas/types.yaml#/definitions/phandle-array
38
-
items:
39
-
minItems: 1
40
-
maxItems: 4
37
+
minItems: 1
38
+
maxItems: 4
41
39
description: |
42
40
Array of phandles pointing to CPU cores, which should match the order of
43
41
CPU cores used by the WUPCR and PSTR registers in the Advanced Power
+1
-1
Documentation/devicetree/bindings/regulator/max8660.yaml
+1
-1
Documentation/devicetree/bindings/regulator/max8660.yaml
+1
-1
Documentation/devicetree/bindings/regulator/maxim,max77802.yaml
+1
-1
Documentation/devicetree/bindings/regulator/maxim,max77802.yaml
+1
-1
Documentation/devicetree/bindings/regulator/regulator.yaml
+1
-1
Documentation/devicetree/bindings/regulator/regulator.yaml
+1
-1
Documentation/devicetree/bindings/regulator/rohm,bd9576-regulator.yaml
+1
-1
Documentation/devicetree/bindings/regulator/rohm,bd9576-regulator.yaml
+7
-7
Documentation/devicetree/bindings/regulator/ti,tps65219.yaml
+7
-7
Documentation/devicetree/bindings/regulator/ti,tps65219.yaml
···
51
51
where the board has a button wired to the pin and triggers
52
52
an interrupt on pressing it.
53
53
54
-
patternProperties:
55
-
"^buck[1-3]-supply$":
56
-
description: Input supply phandle of one regulator.
57
-
58
-
"^ldo[1-4]-supply$":
59
-
description: Input supply phandle of one regulator.
60
-
61
54
regulators:
62
55
type: object
63
56
description: |
···
74
81
unevaluatedProperties: false
75
82
76
83
additionalProperties: false
84
+
85
+
patternProperties:
86
+
"^buck[1-3]-supply$":
87
+
description: Input supply phandle of one regulator.
88
+
89
+
"^ldo[1-4]-supply$":
90
+
description: Input supply phandle of one regulator.
77
91
78
92
required:
79
93
- compatible
+2
-1
Documentation/devicetree/bindings/sound/intel,keembay-i2s.yaml
+2
-1
Documentation/devicetree/bindings/sound/intel,keembay-i2s.yaml
+1
-1
Documentation/devicetree/bindings/sound/renesas,rsnd.yaml
+1
-1
Documentation/devicetree/bindings/sound/renesas,rsnd.yaml
+32
-32
Documentation/devicetree/bindings/sound/tlv320adcx140.yaml
+32
-32
Documentation/devicetree/bindings/sound/tlv320adcx140.yaml
···
109
109
maximum: 7
110
110
default: [0, 0, 0, 0]
111
111
112
-
ti,asi-tx-drive:
113
-
type: boolean
114
-
description: |
115
-
When set the device will set the Tx ASI output to a Hi-Z state for unused
116
-
data cycles. Default is to drive the output low on unused ASI cycles.
117
-
118
-
patternProperties:
119
-
'^ti,gpo-config-[1-4]$':
120
-
$ref: /schemas/types.yaml#/definitions/uint32-array
121
-
description: |
122
-
Defines the configuration and output driver for the general purpose
123
-
output pins (GPO). These values are pairs, the first value is for the
124
-
configuration type and the second value is for the output drive type.
125
-
The array is defined as <GPO_CFG GPO_DRV>
126
-
127
-
GPO output configuration can be one of the following:
128
-
129
-
0 - (default) disabled
130
-
1 - GPOX is configured as a general-purpose output (GPO)
131
-
2 - GPOX is configured as a device interrupt output (IRQ)
132
-
3 - GPOX is configured as a secondary ASI output (SDOUT2)
133
-
4 - GPOX is configured as a PDM clock output (PDMCLK)
134
-
135
-
GPO output drive configuration for the GPO pins can be one of the following:
136
-
137
-
0d - (default) Hi-Z output
138
-
1d - Drive active low and active high
139
-
2d - Drive active low and weak high
140
-
3d - Drive active low and Hi-Z
141
-
4d - Drive weak low and active high
142
-
5d - Drive Hi-Z and active high
143
-
144
112
ti,gpio-config:
145
113
description: |
146
114
Defines the configuration and output drive for the General Purpose
···
150
182
items:
151
183
maximum: 15
152
184
default: [2, 2]
185
+
186
+
ti,asi-tx-drive:
187
+
type: boolean
188
+
description: |
189
+
When set the device will set the Tx ASI output to a Hi-Z state for unused
190
+
data cycles. Default is to drive the output low on unused ASI cycles.
191
+
192
+
patternProperties:
193
+
'^ti,gpo-config-[1-4]$':
194
+
$ref: /schemas/types.yaml#/definitions/uint32-array
195
+
description: |
196
+
Defines the configuration and output driver for the general purpose
197
+
output pins (GPO). These values are pairs, the first value is for the
198
+
configuration type and the second value is for the output drive type.
199
+
The array is defined as <GPO_CFG GPO_DRV>
200
+
201
+
GPO output configuration can be one of the following:
202
+
203
+
0 - (default) disabled
204
+
1 - GPOX is configured as a general-purpose output (GPO)
205
+
2 - GPOX is configured as a device interrupt output (IRQ)
206
+
3 - GPOX is configured as a secondary ASI output (SDOUT2)
207
+
4 - GPOX is configured as a PDM clock output (PDMCLK)
208
+
209
+
GPO output drive configuration for the GPO pins can be one of the following:
210
+
211
+
0d - (default) Hi-Z output
212
+
1d - Drive active low and active high
213
+
2d - Drive active low and weak high
214
+
3d - Drive active low and Hi-Z
215
+
4d - Drive weak low and active high
216
+
5d - Drive Hi-Z and active high
153
217
154
218
required:
155
219
- compatible
+1
-1
Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
+1
-1
Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
+1
-1
Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
+1
-1
Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
+1
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+1
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+4
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
+4
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
+75
-69
Documentation/devicetree/bindings/thermal/thermal-idle.yaml
+75
-69
Documentation/devicetree/bindings/thermal/thermal-idle.yaml
···
48
48
49
49
examples:
50
50
- |
51
-
#include <dt-bindings/thermal/thermal.h>
51
+
/{
52
+
#include <dt-bindings/thermal/thermal.h>
52
53
53
-
// Example: Combining idle cooling device on big CPUs with cpufreq cooling device
54
-
cpus {
54
+
compatible = "foo";
55
+
model = "foo";
56
+
#address-cells = <1>;
57
+
#size-cells = <1>;
58
+
59
+
// Example: Combining idle cooling device on big CPUs with cpufreq cooling device
60
+
cpus {
55
61
#address-cells = <2>;
56
62
#size-cells = <0>;
57
63
58
64
/* ... */
59
65
60
-
cpu_b0: cpu@100 {
61
-
device_type = "cpu";
62
-
compatible = "arm,cortex-a72";
63
-
reg = <0x0 0x100>;
64
-
enable-method = "psci";
65
-
capacity-dmips-mhz = <1024>;
66
-
dynamic-power-coefficient = <436>;
67
-
#cooling-cells = <2>; /* min followed by max */
68
-
cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
69
-
thermal-idle {
70
-
#cooling-cells = <2>;
71
-
duration-us = <10000>;
72
-
exit-latency-us = <500>;
73
-
};
66
+
cpu_b0: cpu@100 {
67
+
device_type = "cpu";
68
+
compatible = "arm,cortex-a72";
69
+
reg = <0x0 0x100>;
70
+
enable-method = "psci";
71
+
capacity-dmips-mhz = <1024>;
72
+
dynamic-power-coefficient = <436>;
73
+
#cooling-cells = <2>; /* min followed by max */
74
+
cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
75
+
cpu_b0_therm: thermal-idle {
76
+
#cooling-cells = <2>;
77
+
duration-us = <10000>;
78
+
exit-latency-us = <500>;
74
79
};
80
+
};
75
81
76
-
cpu_b1: cpu@101 {
77
-
device_type = "cpu";
78
-
compatible = "arm,cortex-a72";
79
-
reg = <0x0 0x101>;
80
-
enable-method = "psci";
81
-
capacity-dmips-mhz = <1024>;
82
-
dynamic-power-coefficient = <436>;
83
-
#cooling-cells = <2>; /* min followed by max */
84
-
cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
85
-
thermal-idle {
86
-
#cooling-cells = <2>;
87
-
duration-us = <10000>;
88
-
exit-latency-us = <500>;
89
-
};
90
-
};
82
+
cpu_b1: cpu@101 {
83
+
device_type = "cpu";
84
+
compatible = "arm,cortex-a72";
85
+
reg = <0x0 0x101>;
86
+
enable-method = "psci";
87
+
capacity-dmips-mhz = <1024>;
88
+
dynamic-power-coefficient = <436>;
89
+
#cooling-cells = <2>; /* min followed by max */
90
+
cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
91
+
cpu_b1_therm: thermal-idle {
92
+
#cooling-cells = <2>;
93
+
duration-us = <10000>;
94
+
exit-latency-us = <500>;
95
+
};
96
+
};
91
97
92
-
/* ... */
98
+
/* ... */
93
99
94
-
};
100
+
};
95
101
96
-
/* ... */
102
+
/* ... */
97
103
98
-
thermal_zones {
99
-
cpu_thermal: cpu {
104
+
thermal_zones {
105
+
cpu_thermal: cpu {
100
106
polling-delay-passive = <100>;
101
107
polling-delay = <1000>;
102
108
103
109
/* ... */
104
110
105
111
trips {
106
-
cpu_alert0: cpu_alert0 {
107
-
temperature = <65000>;
108
-
hysteresis = <2000>;
109
-
type = "passive";
110
-
};
112
+
cpu_alert0: cpu_alert0 {
113
+
temperature = <65000>;
114
+
hysteresis = <2000>;
115
+
type = "passive";
116
+
};
111
117
112
-
cpu_alert1: cpu_alert1 {
113
-
temperature = <70000>;
114
-
hysteresis = <2000>;
115
-
type = "passive";
116
-
};
118
+
cpu_alert1: cpu_alert1 {
119
+
temperature = <70000>;
120
+
hysteresis = <2000>;
121
+
type = "passive";
122
+
};
117
123
118
-
cpu_alert2: cpu_alert2 {
119
-
temperature = <75000>;
120
-
hysteresis = <2000>;
121
-
type = "passive";
122
-
};
124
+
cpu_alert2: cpu_alert2 {
125
+
temperature = <75000>;
126
+
hysteresis = <2000>;
127
+
type = "passive";
128
+
};
123
129
124
-
cpu_crit: cpu_crit {
125
-
temperature = <95000>;
126
-
hysteresis = <2000>;
127
-
type = "critical";
128
-
};
130
+
cpu_crit: cpu_crit {
131
+
temperature = <95000>;
132
+
hysteresis = <2000>;
133
+
type = "critical";
134
+
};
129
135
};
130
136
131
137
cooling-maps {
132
-
map0 {
133
-
trip = <&cpu_alert1>;
134
-
cooling-device = <&{/cpus/cpu@100/thermal-idle} 0 15 >,
135
-
<&{/cpus/cpu@101/thermal-idle} 0 15>;
136
-
};
138
+
map0 {
139
+
trip = <&cpu_alert1>;
140
+
cooling-device = <&cpu_b0_therm 0 15 >,
141
+
<&cpu_b1_therm 0 15>;
142
+
};
137
143
138
-
map1 {
139
-
trip = <&cpu_alert2>;
140
-
cooling-device =
141
-
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
142
-
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
143
-
};
144
+
map1 {
145
+
trip = <&cpu_alert2>;
146
+
cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
147
+
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
148
+
};
144
149
};
145
-
};
150
+
};
151
+
};
146
152
};
+2
Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
+2
Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
+3
-1
MAINTAINERS
+3
-1
MAINTAINERS
···
8796
8796
M: Sean Young <sean@mess.org>
8797
8797
L: linux-media@vger.kernel.org
8798
8798
S: Maintained
8799
+
F: Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.yaml
8799
8800
F: drivers/media/rc/gpio-ir-tx.c
8800
8801
8801
8802
GPIO MOCKUP DRIVER
···
16848
16847
M: Sean Young <sean@mess.org>
16849
16848
L: linux-media@vger.kernel.org
16850
16849
S: Maintained
16850
+
F: Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.yaml
16851
16851
F: drivers/media/rc/pwm-ir-tx.c
16852
16852
16853
16853
PWM SUBSYSTEM
···
19619
19617
L: linux-media@vger.kernel.org
19620
19618
S: Maintained
19621
19619
T: git git://linuxtv.org/media_tree.git
19622
-
F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
19620
+
F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml
19623
19621
F: drivers/media/i2c/st-mipid02.c
19624
19622
19625
19623
ST STM32 I2C/SMBUS DRIVER
+5
-5
drivers/of/kexec.c
+5
-5
drivers/of/kexec.c
···
281
281
const char *cmdline, size_t extra_fdt_size)
282
282
{
283
283
void *fdt;
284
-
int ret, chosen_node;
284
+
int ret, chosen_node, len;
285
285
const void *prop;
286
286
size_t fdt_size;
287
287
···
324
324
goto out;
325
325
326
326
/* Did we boot using an initrd? */
327
-
prop = fdt_getprop(fdt, chosen_node, "linux,initrd-start", NULL);
327
+
prop = fdt_getprop(fdt, chosen_node, "linux,initrd-start", &len);
328
328
if (prop) {
329
329
u64 tmp_start, tmp_end, tmp_size;
330
330
331
-
tmp_start = fdt64_to_cpu(*((const fdt64_t *) prop));
331
+
tmp_start = of_read_number(prop, len / 4);
332
332
333
-
prop = fdt_getprop(fdt, chosen_node, "linux,initrd-end", NULL);
333
+
prop = fdt_getprop(fdt, chosen_node, "linux,initrd-end", &len);
334
334
if (!prop) {
335
335
ret = -EINVAL;
336
336
goto out;
337
337
}
338
338
339
-
tmp_end = fdt64_to_cpu(*((const fdt64_t *) prop));
339
+
tmp_end = of_read_number(prop, len / 4);
340
340
341
341
/*
342
342
* kexec reserves exact initrd size, while firmware may
+2
-2
drivers/of/overlay.c
+2
-2
drivers/of/overlay.c
···
545
545
546
546
fn_1 = kasprintf(GFP_KERNEL, "%pOF", ce_1->np);
547
547
fn_2 = kasprintf(GFP_KERNEL, "%pOF", ce_2->np);
548
-
node_path_match = !strcmp(fn_1, fn_2);
548
+
node_path_match = !fn_1 || !fn_2 || !strcmp(fn_1, fn_2);
549
549
kfree(fn_1);
550
550
kfree(fn_2);
551
551
if (node_path_match) {
···
580
580
581
581
fn_1 = kasprintf(GFP_KERNEL, "%pOF", ce_1->np);
582
582
fn_2 = kasprintf(GFP_KERNEL, "%pOF", ce_2->np);
583
-
node_path_match = !strcmp(fn_1, fn_2);
583
+
node_path_match = !fn_1 || !fn_2 || !strcmp(fn_1, fn_2);
584
584
kfree(fn_1);
585
585
kfree(fn_2);
586
586
if (node_path_match &&
+2
-3
drivers/of/platform.c
+2
-3
drivers/of/platform.c
···
115
115
{
116
116
struct platform_device *dev;
117
117
int rc, i, num_reg = 0;
118
-
struct resource *res, temp_res;
118
+
struct resource *res;
119
119
120
120
dev = platform_device_alloc("", PLATFORM_DEVID_NONE);
121
121
if (!dev)
122
122
return NULL;
123
123
124
124
/* count the io resources */
125
-
while (of_address_to_resource(np, num_reg, &temp_res) == 0)
126
-
num_reg++;
125
+
num_reg = of_address_count(np);
127
126
128
127
/* Populate the resource table */
129
128
if (num_reg) {
+4
-6
drivers/of/unittest.c
+4
-6
drivers/of/unittest.c
···
2508
2508
},
2509
2509
};
2510
2510
2511
-
static int unittest_i2c_dev_probe(struct i2c_client *client,
2512
-
const struct i2c_device_id *id)
2511
+
static int unittest_i2c_dev_probe(struct i2c_client *client)
2513
2512
{
2514
2513
struct device *dev = &client->dev;
2515
2514
struct device_node *np = client->dev.of_node;
···
2540
2541
.driver = {
2541
2542
.name = "unittest-i2c-dev",
2542
2543
},
2543
-
.probe = unittest_i2c_dev_probe,
2544
+
.probe_new = unittest_i2c_dev_probe,
2544
2545
.remove = unittest_i2c_dev_remove,
2545
2546
.id_table = unittest_i2c_dev_id,
2546
2547
};
···
2552
2553
return 0;
2553
2554
}
2554
2555
2555
-
static int unittest_i2c_mux_probe(struct i2c_client *client,
2556
-
const struct i2c_device_id *id)
2556
+
static int unittest_i2c_mux_probe(struct i2c_client *client)
2557
2557
{
2558
2558
int i, nchans;
2559
2559
struct device *dev = &client->dev;
···
2617
2619
.driver = {
2618
2620
.name = "unittest-i2c-mux",
2619
2621
},
2620
-
.probe = unittest_i2c_mux_probe,
2622
+
.probe_new = unittest_i2c_mux_probe,
2621
2623
.remove = unittest_i2c_mux_remove,
2622
2624
.id_table = unittest_i2c_mux_id,
2623
2625
};
+2
-2
include/linux/of.h
+2
-2
include/linux/of.h
···
1549
1549
OF_OVERLAY_POST_REMOVE,
1550
1550
};
1551
1551
1552
-
static inline char *of_overlay_action_name(enum of_overlay_notify_action action)
1552
+
static inline const char *of_overlay_action_name(enum of_overlay_notify_action action)
1553
1553
{
1554
-
static char *of_overlay_action_name[] = {
1554
+
static const char *const of_overlay_action_name[] = {
1555
1555
"init",
1556
1556
"pre-apply",
1557
1557
"post-apply",
+11
include/linux/of_address.h
+11
include/linux/of_address.h
···
154
154
return __of_get_address(dev, -1, bar_no, size, flags);
155
155
}
156
156
157
+
static inline int of_address_count(struct device_node *np)
158
+
{
159
+
struct resource res;
160
+
int count = 0;
161
+
162
+
while (of_address_to_resource(np, count, &res) == 0)
163
+
count++;
164
+
165
+
return count;
166
+
}
167
+
157
168
#endif /* __OF_ADDRESS_H */
+8
-4
scripts/Makefile.lib
+8
-4
scripts/Makefile.lib
···
334
334
# DTC
335
335
# ---------------------------------------------------------------------------
336
336
DTC ?= $(objtree)/scripts/dtc/dtc
337
-
DTC_FLAGS += -Wno-interrupt_provider
337
+
DTC_FLAGS += -Wno-interrupt_provider \
338
+
-Wno-unique_unit_address
338
339
339
340
# Disable noisy checks by default
340
341
ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)
···
343
342
-Wno-avoid_unnecessary_addr_size \
344
343
-Wno-alias_paths \
345
344
-Wno-graph_child_address \
346
-
-Wno-simple_bus_reg \
347
-
-Wno-unique_unit_address
345
+
-Wno-simple_bus_reg
346
+
else
347
+
DTC_FLAGS += \
348
+
-Wunique_unit_address_if_enabled
348
349
endif
349
350
350
351
ifneq ($(findstring 2,$(KBUILD_EXTRA_WARN)),)
351
352
DTC_FLAGS += -Wnode_name_chars_strict \
352
353
-Wproperty_name_chars_strict \
353
-
-Winterrupt_provider
354
+
-Winterrupt_provider \
355
+
-Wunique_unit_address
354
356
endif
355
357
356
358
DTC_FLAGS += $(DTC_FLAGS_$(basetarget))
+9
-6
scripts/dtc/checks.c
+9
-6
scripts/dtc/checks.c
···
1382
1382
};
1383
1383
1384
1384
static void check_property_phandle_args(struct check *c,
1385
-
struct dt_info *dti,
1386
-
struct node *node,
1387
-
struct property *prop,
1388
-
const struct provider *provider)
1385
+
struct dt_info *dti,
1386
+
struct node *node,
1387
+
struct property *prop,
1388
+
const struct provider *provider)
1389
1389
{
1390
1390
struct node *root = dti->dt;
1391
1391
unsigned int cell, cellsize = 0;
···
1401
1401
struct node *provider_node;
1402
1402
struct property *cellprop;
1403
1403
cell_t phandle;
1404
+
unsigned int expected;
1404
1405
1405
1406
phandle = propval_cell_n(prop, cell);
1406
1407
/*
···
1451
1450
break;
1452
1451
}
1453
1452
1454
-
if (prop->val.len < ((cell + cellsize + 1) * sizeof(cell_t))) {
1453
+
expected = (cell + cellsize + 1) * sizeof(cell_t);
1454
+
if ((expected <= cell) || prop->val.len < expected) {
1455
1455
FAIL_PROP(c, dti, node, prop,
1456
-
"property size (%d) too small for cell size %d",
1456
+
"property size (%d) too small for cell size %u",
1457
1457
prop->val.len, cellsize);
1458
+
break;
1458
1459
}
1459
1460
}
1460
1461
}
+1
-1
scripts/dtc/dtc-lexer.l
+1
-1
scripts/dtc/dtc-lexer.l
+13
scripts/dtc/dtc-parser.y
+13
scripts/dtc/dtc-parser.y
···
23
23
24
24
extern struct dt_info *parser_output;
25
25
extern bool treesource_error;
26
+
27
+
static bool is_ref_relative(const char *ref)
28
+
{
29
+
return ref[0] != '/' && strchr(&ref[1], '/');
30
+
}
31
+
26
32
%}
27
33
28
34
%union {
···
175
169
*/
176
170
if (!($<flags>-1 & DTSF_PLUGIN))
177
171
ERROR(&@2, "Label or path %s not found", $1);
172
+
else if (is_ref_relative($1))
173
+
ERROR(&@2, "Label-relative reference %s not supported in plugin", $1);
178
174
$$ = add_orphan_node(
179
175
name_node(build_node(NULL, NULL, NULL),
180
176
""),
···
185
177
| devicetree DT_LABEL dt_ref nodedef
186
178
{
187
179
struct node *target = get_node_by_ref($1, $3);
180
+
181
+
if (($<flags>-1 & DTSF_PLUGIN) && is_ref_relative($3))
182
+
ERROR(&@2, "Label-relative reference %s not supported in plugin", $3);
188
183
189
184
if (target) {
190
185
add_label(&target->labels, $2);
···
204
193
* so $-1 is what we want (plugindecl)
205
194
*/
206
195
if ($<flags>-1 & DTSF_PLUGIN) {
196
+
if (is_ref_relative($2))
197
+
ERROR(&@2, "Label-relative reference %s not supported in plugin", $2);
207
198
add_orphan_node($1, $3, $2);
208
199
} else {
209
200
struct node *target = get_node_by_ref($1, $2);
+12
-8
scripts/dtc/libfdt/fdt.c
+12
-8
scripts/dtc/libfdt/fdt.c
···
106
106
}
107
107
hdrsize = fdt_header_size(fdt);
108
108
if (!can_assume(VALID_DTB)) {
109
-
110
109
if ((fdt_totalsize(fdt) < hdrsize)
111
110
|| (fdt_totalsize(fdt) > INT_MAX))
112
111
return -FDT_ERR_TRUNCATED;
···
114
115
if (!check_off_(hdrsize, fdt_totalsize(fdt),
115
116
fdt_off_mem_rsvmap(fdt)))
116
117
return -FDT_ERR_TRUNCATED;
117
-
}
118
118
119
-
if (!can_assume(VALID_DTB)) {
120
119
/* Bounds check structure block */
121
120
if (!can_assume(LATEST) && fdt_version(fdt) < 17) {
122
121
if (!check_off_(hdrsize, fdt_totalsize(fdt),
···
162
165
uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
163
166
{
164
167
const fdt32_t *tagp, *lenp;
165
-
uint32_t tag;
168
+
uint32_t tag, len, sum;
166
169
int offset = startoffset;
167
170
const char *p;
168
171
···
188
191
lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));
189
192
if (!can_assume(VALID_DTB) && !lenp)
190
193
return FDT_END; /* premature end */
194
+
195
+
len = fdt32_to_cpu(*lenp);
196
+
sum = len + offset;
197
+
if (!can_assume(VALID_DTB) &&
198
+
(INT_MAX <= sum || sum < (uint32_t) offset))
199
+
return FDT_END; /* premature end */
200
+
191
201
/* skip-name offset, length and value */
192
-
offset += sizeof(struct fdt_property) - FDT_TAGSIZE
193
-
+ fdt32_to_cpu(*lenp);
202
+
offset += sizeof(struct fdt_property) - FDT_TAGSIZE + len;
203
+
194
204
if (!can_assume(LATEST) &&
195
-
fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 &&
196
-
((offset - fdt32_to_cpu(*lenp)) % 8) != 0)
205
+
fdt_version(fdt) < 0x10 && len >= 8 &&
206
+
((offset - len) % 8) != 0)
197
207
offset += 4;
198
208
break;
199
209
+2
-2
scripts/dtc/libfdt/fdt.h
+2
-2
scripts/dtc/libfdt/fdt.h
+1
-1
scripts/dtc/libfdt/fdt_addresses.c
+1
-1
scripts/dtc/libfdt/fdt_addresses.c
···
73
73
/* check validity of address */
74
74
prop = data;
75
75
if (addr_cells == 1) {
76
-
if ((addr > UINT32_MAX) || ((UINT32_MAX + 1 - addr) < size))
76
+
if ((addr > UINT32_MAX) || (((uint64_t) UINT32_MAX + 1 - addr) < size))
77
77
return -FDT_ERR_BADVALUE;
78
78
79
79
fdt32_st(prop, (uint32_t)addr);
+7
-22
scripts/dtc/libfdt/fdt_overlay.c
+7
-22
scripts/dtc/libfdt/fdt_overlay.c
···
40
40
return fdt32_to_cpu(*val);
41
41
}
42
42
43
-
/**
44
-
* overlay_get_target - retrieves the offset of a fragment's target
45
-
* @fdt: Base device tree blob
46
-
* @fdto: Device tree overlay blob
47
-
* @fragment: node offset of the fragment in the overlay
48
-
* @pathp: pointer which receives the path of the target (or NULL)
49
-
*
50
-
* overlay_get_target() retrieves the target offset in the base
51
-
* device tree of a fragment, no matter how the actual targeting is
52
-
* done (through a phandle or a path)
53
-
*
54
-
* returns:
55
-
* the targeted node offset in the base device tree
56
-
* Negative error code on error
57
-
*/
58
-
static int overlay_get_target(const void *fdt, const void *fdto,
59
-
int fragment, char const **pathp)
43
+
int fdt_overlay_target_offset(const void *fdt, const void *fdto,
44
+
int fragment_offset, char const **pathp)
60
45
{
61
46
uint32_t phandle;
62
47
const char *path = NULL;
63
48
int path_len = 0, ret;
64
49
65
50
/* Try first to do a phandle based lookup */
66
-
phandle = overlay_get_target_phandle(fdto, fragment);
51
+
phandle = overlay_get_target_phandle(fdto, fragment_offset);
67
52
if (phandle == (uint32_t)-1)
68
53
return -FDT_ERR_BADPHANDLE;
69
54
70
55
/* no phandle, try path */
71
56
if (!phandle) {
72
57
/* And then a path based lookup */
73
-
path = fdt_getprop(fdto, fragment, "target-path", &path_len);
58
+
path = fdt_getprop(fdto, fragment_offset, "target-path", &path_len);
74
59
if (path)
75
60
ret = fdt_path_offset(fdt, path);
76
61
else
···
621
636
if (overlay < 0)
622
637
return overlay;
623
638
624
-
target = overlay_get_target(fdt, fdto, fragment, NULL);
639
+
target = fdt_overlay_target_offset(fdt, fdto, fragment, NULL);
625
640
if (target < 0)
626
641
return target;
627
642
···
764
779
return -FDT_ERR_BADOVERLAY;
765
780
766
781
/* get the target of the fragment */
767
-
ret = overlay_get_target(fdt, fdto, fragment, &target_path);
782
+
ret = fdt_overlay_target_offset(fdt, fdto, fragment, &target_path);
768
783
if (ret < 0)
769
784
return ret;
770
785
target = ret;
···
786
801
787
802
if (!target_path) {
788
803
/* again in case setprop_placeholder changed it */
789
-
ret = overlay_get_target(fdt, fdto, fragment, &target_path);
804
+
ret = fdt_overlay_target_offset(fdt, fdto, fragment, &target_path);
790
805
if (ret < 0)
791
806
return ret;
792
807
target = ret;
+1
-1
scripts/dtc/libfdt/fdt_ro.c
+1
-1
scripts/dtc/libfdt/fdt_ro.c
···
481
481
if (!can_assume(VALID_INPUT)) {
482
482
name = fdt_get_string(fdt, fdt32_ld_(&prop->nameoff),
483
483
&namelen);
484
+
*namep = name;
484
485
if (!name) {
485
486
if (lenp)
486
487
*lenp = namelen;
487
488
return NULL;
488
489
}
489
-
*namep = name;
490
490
} else {
491
491
*namep = fdt_string(fdt, fdt32_ld_(&prop->nameoff));
492
492
}
+25
scripts/dtc/libfdt/libfdt.h
+25
scripts/dtc/libfdt/libfdt.h
···
660
660
const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
661
661
int offset,
662
662
int *lenp);
663
+
static inline struct fdt_property *fdt_get_property_by_offset_w(void *fdt,
664
+
int offset,
665
+
int *lenp)
666
+
{
667
+
return (struct fdt_property *)(uintptr_t)
668
+
fdt_get_property_by_offset(fdt, offset, lenp);
669
+
}
663
670
664
671
/**
665
672
* fdt_get_property_namelen - find a property based on substring
···
2122
2115
* -FDT_ERR_TRUNCATED, standard meanings
2123
2116
*/
2124
2117
int fdt_overlay_apply(void *fdt, void *fdto);
2118
+
2119
+
/**
2120
+
* fdt_overlay_target_offset - retrieves the offset of a fragment's target
2121
+
* @fdt: Base device tree blob
2122
+
* @fdto: Device tree overlay blob
2123
+
* @fragment_offset: node offset of the fragment in the overlay
2124
+
* @pathp: pointer which receives the path of the target (or NULL)
2125
+
*
2126
+
* fdt_overlay_target_offset() retrieves the target offset in the base
2127
+
* device tree of a fragment, no matter how the actual targeting is
2128
+
* done (through a phandle or a path)
2129
+
*
2130
+
* returns:
2131
+
* the targeted node offset in the base device tree
2132
+
* Negative error code on error
2133
+
*/
2134
+
int fdt_overlay_target_offset(const void *fdt, const void *fdto,
2135
+
int fragment_offset, char const **pathp);
2125
2136
2126
2137
/**********************************************************************/
2127
2138
/* Debugging / informational functions */
+36
-3
scripts/dtc/livetree.c
+36
-3
scripts/dtc/livetree.c
···
581
581
582
582
struct node *get_node_by_ref(struct node *tree, const char *ref)
583
583
{
584
+
struct node *target = tree;
585
+
const char *label = NULL, *path = NULL;
586
+
584
587
if (streq(ref, "/"))
585
588
return tree;
586
-
else if (ref[0] == '/')
587
-
return get_node_by_path(tree, ref);
589
+
590
+
if (ref[0] == '/')
591
+
path = ref;
588
592
else
589
-
return get_node_by_label(tree, ref);
593
+
label = ref;
594
+
595
+
if (label) {
596
+
const char *slash = strchr(label, '/');
597
+
char *buf = NULL;
598
+
599
+
if (slash) {
600
+
buf = xstrndup(label, slash - label);
601
+
label = buf;
602
+
path = slash + 1;
603
+
}
604
+
605
+
target = get_node_by_label(tree, label);
606
+
607
+
free(buf);
608
+
609
+
if (!target)
610
+
return NULL;
611
+
}
612
+
613
+
if (path)
614
+
target = get_node_by_path(target, path);
615
+
616
+
return target;
590
617
}
591
618
592
619
cell_t get_node_phandle(struct node *root, struct node *node)
···
918
891
919
892
/* m->ref can only be a REF_PHANDLE, but check anyway */
920
893
assert(m->type == REF_PHANDLE);
894
+
895
+
/* The format only permits fixups for references to label, not
896
+
* references to path */
897
+
if (strchr(m->ref, '/'))
898
+
die("Can't generate fixup for reference to path &{%s}\n",
899
+
m->ref);
921
900
922
901
/* there shouldn't be any ':' in the arguments */
923
902
if (strchr(node->fullpath, ':') || strchr(prop->name, ':'))
+13
-2
scripts/dtc/util.c
+13
-2
scripts/dtc/util.c
···
33
33
return d;
34
34
}
35
35
36
+
char *xstrndup(const char *s, size_t n)
37
+
{
38
+
size_t len = strnlen(s, n) + 1;
39
+
char *d = xmalloc(len);
40
+
41
+
memcpy(d, s, len - 1);
42
+
d[len - 1] = '\0';
43
+
44
+
return d;
45
+
}
46
+
36
47
int xavsprintf_append(char **strp, const char *fmt, va_list ap)
37
48
{
38
49
int n, size = 0; /* start with 128 bytes */
···
364
353
}
365
354
366
355
/* we should now have a type */
367
-
if ((*fmt == '\0') || !strchr("iuxs", *fmt))
356
+
if ((*fmt == '\0') || !strchr("iuxsr", *fmt))
368
357
return -1;
369
358
370
359
/* convert qualifier (bhL) to byte size */
371
-
if (*fmt != 's')
360
+
if (*fmt != 's' && *fmt != 'r')
372
361
*size = qualifier == 'b' ? 1 :
373
362
qualifier == 'h' ? 2 :
374
363
qualifier == 'l' ? 4 : -1;
+3
-1
scripts/dtc/util.h
+3
-1
scripts/dtc/util.h
···
61
61
}
62
62
63
63
extern char *xstrdup(const char *s);
64
+
extern char *xstrndup(const char *s, size_t len);
64
65
65
66
extern int PRINTF(2, 3) xasprintf(char **strp, const char *fmt, ...);
66
67
extern int PRINTF(2, 3) xasprintf_append(char **strp, const char *fmt, ...);
···
144
143
* i signed integer
145
144
* u unsigned integer
146
145
* x hex
146
+
* r raw
147
147
*
148
148
* TODO: Implement ll modifier (8 bytes)
149
149
* TODO: Implement o type (octal)
···
162
160
*/
163
161
164
162
#define USAGE_TYPE_MSG \
165
-
"<type>\ts=string, i=int, u=unsigned, x=hex\n" \
163
+
"<type>\ts=string, i=int, u=unsigned, x=hex, r=raw\n" \
166
164
"\tOptional modifier prefix:\n" \
167
165
"\t\thh or b=byte, h=2 byte, l=4 byte (default)";
168
166