tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: qcom: mmcc-msm8960: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-8-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson 53e1409c a6976f85

+42 -42
+42 -42
drivers/clk/qcom/mmcc-msm8960.c
··· 193 193 .hw.init = &(struct clk_init_data){ 194 194 .name = "camclk0_src", 195 195 .parent_names = mmcc_pxo_pll8_pll2, 196 - .num_parents = 3, 196 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 197 197 .ops = &clk_rcg_ops, 198 198 }, 199 199 }, ··· 242 242 .hw.init = &(struct clk_init_data){ 243 243 .name = "camclk1_src", 244 244 .parent_names = mmcc_pxo_pll8_pll2, 245 - .num_parents = 3, 245 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 246 246 .ops = &clk_rcg_ops, 247 247 }, 248 248 }, ··· 291 291 .hw.init = &(struct clk_init_data){ 292 292 .name = "camclk2_src", 293 293 .parent_names = mmcc_pxo_pll8_pll2, 294 - .num_parents = 3, 294 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 295 295 .ops = &clk_rcg_ops, 296 296 }, 297 297 }, ··· 346 346 .hw.init = &(struct clk_init_data){ 347 347 .name = "csi0_src", 348 348 .parent_names = mmcc_pxo_pll8_pll2, 349 - .num_parents = 3, 349 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 350 350 .ops = &clk_rcg_ops, 351 351 }, 352 352 }, ··· 410 410 .hw.init = &(struct clk_init_data){ 411 411 .name = "csi1_src", 412 412 .parent_names = mmcc_pxo_pll8_pll2, 413 - .num_parents = 3, 413 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 414 414 .ops = &clk_rcg_ops, 415 415 }, 416 416 }, ··· 474 474 .hw.init = &(struct clk_init_data){ 475 475 .name = "csi2_src", 476 476 .parent_names = mmcc_pxo_pll8_pll2, 477 - .num_parents = 3, 477 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 478 478 .ops = &clk_rcg_ops, 479 479 }, 480 480 }, ··· 619 619 .hw.init = &(struct clk_init_data){ 620 620 .name = "csi_pix_clk", 621 621 .parent_names = pix_rdi_parents, 622 - .num_parents = 3, 622 + .num_parents = ARRAY_SIZE(pix_rdi_parents), 623 623 .ops = &clk_ops_pix_rdi, 624 624 }, 625 625 }, ··· 636 636 .hw.init = &(struct clk_init_data){ 637 637 .name = "csi_pix1_clk", 638 638 .parent_names = pix_rdi_parents, 639 - .num_parents = 3, 639 + .num_parents = ARRAY_SIZE(pix_rdi_parents), 640 640 .ops = &clk_ops_pix_rdi, 641 641 }, 642 642 }, ··· 653 653 .hw.init = &(struct clk_init_data){ 654 654 .name = "csi_rdi_clk", 655 655 .parent_names = pix_rdi_parents, 656 - .num_parents = 3, 656 + .num_parents = ARRAY_SIZE(pix_rdi_parents), 657 657 .ops = &clk_ops_pix_rdi, 658 658 }, 659 659 }, ··· 670 670 .hw.init = &(struct clk_init_data){ 671 671 .name = "csi_rdi1_clk", 672 672 .parent_names = pix_rdi_parents, 673 - .num_parents = 3, 673 + .num_parents = ARRAY_SIZE(pix_rdi_parents), 674 674 .ops = &clk_ops_pix_rdi, 675 675 }, 676 676 }, ··· 687 687 .hw.init = &(struct clk_init_data){ 688 688 .name = "csi_rdi2_clk", 689 689 .parent_names = pix_rdi_parents, 690 - .num_parents = 3, 690 + .num_parents = ARRAY_SIZE(pix_rdi_parents), 691 691 .ops = &clk_ops_pix_rdi, 692 692 }, 693 693 }, ··· 726 726 .hw.init = &(struct clk_init_data){ 727 727 .name = "csiphytimer_src", 728 728 .parent_names = mmcc_pxo_pll8_pll2, 729 - .num_parents = 3, 729 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 730 730 .ops = &clk_rcg_ops, 731 731 }, 732 732 }, ··· 742 742 .enable_mask = BIT(0), 743 743 .hw.init = &(struct clk_init_data){ 744 744 .parent_names = csixphy_timer_src, 745 - .num_parents = 1, 745 + .num_parents = ARRAY_SIZE(csixphy_timer_src), 746 746 .name = "csiphy0_timer_clk", 747 747 .ops = &clk_branch_ops, 748 748 .flags = CLK_SET_RATE_PARENT, ··· 758 758 .enable_mask = BIT(9), 759 759 .hw.init = &(struct clk_init_data){ 760 760 .parent_names = csixphy_timer_src, 761 - .num_parents = 1, 761 + .num_parents = ARRAY_SIZE(csixphy_timer_src), 762 762 .name = "csiphy1_timer_clk", 763 763 .ops = &clk_branch_ops, 764 764 .flags = CLK_SET_RATE_PARENT, ··· 774 774 .enable_mask = BIT(11), 775 775 .hw.init = &(struct clk_init_data){ 776 776 .parent_names = csixphy_timer_src, 777 - .num_parents = 1, 777 + .num_parents = ARRAY_SIZE(csixphy_timer_src), 778 778 .name = "csiphy2_timer_clk", 779 779 .ops = &clk_branch_ops, 780 780 .flags = CLK_SET_RATE_PARENT, ··· 836 836 .hw.init = &(struct clk_init_data){ 837 837 .name = "gfx2d0_src", 838 838 .parent_names = mmcc_pxo_pll8_pll2, 839 - .num_parents = 3, 839 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 840 840 .ops = &clk_dyn_rcg_ops, 841 841 }, 842 842 }, ··· 896 896 .hw.init = &(struct clk_init_data){ 897 897 .name = "gfx2d1_src", 898 898 .parent_names = mmcc_pxo_pll8_pll2, 899 - .num_parents = 3, 899 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 900 900 .ops = &clk_dyn_rcg_ops, 901 901 }, 902 902 }, ··· 997 997 .hw.init = &(struct clk_init_data){ 998 998 .name = "gfx3d_src", 999 999 .parent_names = mmcc_pxo_pll8_pll2_pll3, 1000 - .num_parents = 4, 1000 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3), 1001 1001 .ops = &clk_dyn_rcg_ops, 1002 1002 }, 1003 1003 }, ··· 1006 1006 static const struct clk_init_data gfx3d_8064_init = { 1007 1007 .name = "gfx3d_src", 1008 1008 .parent_names = mmcc_pxo_pll8_pll2_pll15, 1009 - .num_parents = 4, 1009 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15), 1010 1010 .ops = &clk_dyn_rcg_ops, 1011 1011 }; 1012 1012 ··· 1075 1075 .hw.init = &(struct clk_init_data){ 1076 1076 .name = "vcap_src", 1077 1077 .parent_names = mmcc_pxo_pll8_pll2, 1078 - .num_parents = 3, 1078 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1079 1079 .ops = &clk_dyn_rcg_ops, 1080 1080 }, 1081 1081 }, ··· 1154 1154 .hw.init = &(struct clk_init_data){ 1155 1155 .name = "ijpeg_src", 1156 1156 .parent_names = mmcc_pxo_pll8_pll2, 1157 - .num_parents = 3, 1157 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1158 1158 .ops = &clk_rcg_ops, 1159 1159 }, 1160 1160 }, ··· 1202 1202 .hw.init = &(struct clk_init_data){ 1203 1203 .name = "jpegd_src", 1204 1204 .parent_names = mmcc_pxo_pll8_pll2, 1205 - .num_parents = 3, 1205 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1206 1206 .ops = &clk_rcg_ops, 1207 1207 }, 1208 1208 }, ··· 1282 1282 .hw.init = &(struct clk_init_data){ 1283 1283 .name = "mdp_src", 1284 1284 .parent_names = mmcc_pxo_pll8_pll2, 1285 - .num_parents = 3, 1285 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1286 1286 .ops = &clk_dyn_rcg_ops, 1287 1287 }, 1288 1288 }, ··· 1381 1381 .hw.init = &(struct clk_init_data){ 1382 1382 .name = "rot_src", 1383 1383 .parent_names = mmcc_pxo_pll8_pll2, 1384 - .num_parents = 3, 1384 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1385 1385 .ops = &clk_dyn_rcg_ops, 1386 1386 }, 1387 1387 }, ··· 1444 1444 .hw.init = &(struct clk_init_data){ 1445 1445 .name = "tv_src", 1446 1446 .parent_names = mmcc_pxo_hdmi, 1447 - .num_parents = 2, 1447 + .num_parents = ARRAY_SIZE(mmcc_pxo_hdmi), 1448 1448 .ops = &clk_rcg_bypass_ops, 1449 1449 .flags = CLK_SET_RATE_PARENT, 1450 1450 }, ··· 1461 1461 .enable_mask = BIT(8), 1462 1462 .hw.init = &(struct clk_init_data){ 1463 1463 .parent_names = tv_src_name, 1464 - .num_parents = 1, 1464 + .num_parents = ARRAY_SIZE(tv_src_name), 1465 1465 .name = "tv_enc_clk", 1466 1466 .ops = &clk_branch_ops, 1467 1467 .flags = CLK_SET_RATE_PARENT, ··· 1477 1477 .enable_mask = BIT(10), 1478 1478 .hw.init = &(struct clk_init_data){ 1479 1479 .parent_names = tv_src_name, 1480 - .num_parents = 1, 1480 + .num_parents = ARRAY_SIZE(tv_src_name), 1481 1481 .name = "tv_dac_clk", 1482 1482 .ops = &clk_branch_ops, 1483 1483 .flags = CLK_SET_RATE_PARENT, ··· 1493 1493 .enable_mask = BIT(0), 1494 1494 .hw.init = &(struct clk_init_data){ 1495 1495 .parent_names = tv_src_name, 1496 - .num_parents = 1, 1496 + .num_parents = ARRAY_SIZE(tv_src_name), 1497 1497 .name = "mdp_tv_clk", 1498 1498 .ops = &clk_branch_ops, 1499 1499 .flags = CLK_SET_RATE_PARENT, ··· 1509 1509 .enable_mask = BIT(12), 1510 1510 .hw.init = &(struct clk_init_data){ 1511 1511 .parent_names = tv_src_name, 1512 - .num_parents = 1, 1512 + .num_parents = ARRAY_SIZE(tv_src_name), 1513 1513 .name = "hdmi_tv_clk", 1514 1514 .ops = &clk_branch_ops, 1515 1515 .flags = CLK_SET_RATE_PARENT, ··· 1525 1525 .enable_mask = BIT(14), 1526 1526 .hw.init = &(struct clk_init_data){ 1527 1527 .parent_names = tv_src_name, 1528 - .num_parents = 1, 1528 + .num_parents = ARRAY_SIZE(tv_src_name), 1529 1529 .name = "rgb_tv_clk", 1530 1530 .ops = &clk_branch_ops, 1531 1531 .flags = CLK_SET_RATE_PARENT, ··· 1541 1541 .enable_mask = BIT(16), 1542 1542 .hw.init = &(struct clk_init_data){ 1543 1543 .parent_names = tv_src_name, 1544 - .num_parents = 1, 1544 + .num_parents = ARRAY_SIZE(tv_src_name), 1545 1545 .name = "npl_tv_clk", 1546 1546 .ops = &clk_branch_ops, 1547 1547 .flags = CLK_SET_RATE_PARENT, ··· 1615 1615 .hw.init = &(struct clk_init_data){ 1616 1616 .name = "vcodec_src", 1617 1617 .parent_names = mmcc_pxo_pll8_pll2, 1618 - .num_parents = 3, 1618 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1619 1619 .ops = &clk_dyn_rcg_ops, 1620 1620 }, 1621 1621 }, ··· 1666 1666 .hw.init = &(struct clk_init_data){ 1667 1667 .name = "vpe_src", 1668 1668 .parent_names = mmcc_pxo_pll8_pll2, 1669 - .num_parents = 3, 1669 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1670 1670 .ops = &clk_rcg_ops, 1671 1671 }, 1672 1672 }, ··· 1734 1734 .hw.init = &(struct clk_init_data){ 1735 1735 .name = "vfe_src", 1736 1736 .parent_names = mmcc_pxo_pll8_pll2, 1737 - .num_parents = 3, 1737 + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1738 1738 .ops = &clk_rcg_ops, 1739 1739 }, 1740 1740 }, ··· 2068 2068 .hw.init = &(struct clk_init_data){ 2069 2069 .name = "dsi1_src", 2070 2070 .parent_names = mmcc_pxo_dsi2_dsi1, 2071 - .num_parents = 3, 2071 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2072 2072 .ops = &clk_rcg_bypass2_ops, 2073 2073 .flags = CLK_SET_RATE_PARENT, 2074 2074 }, ··· 2116 2116 .hw.init = &(struct clk_init_data){ 2117 2117 .name = "dsi2_src", 2118 2118 .parent_names = mmcc_pxo_dsi2_dsi1, 2119 - .num_parents = 3, 2119 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2120 2120 .ops = &clk_rcg_bypass2_ops, 2121 2121 .flags = CLK_SET_RATE_PARENT, 2122 2122 }, ··· 2155 2155 .hw.init = &(struct clk_init_data){ 2156 2156 .name = "dsi1_byte_src", 2157 2157 .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2158 - .num_parents = 3, 2158 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), 2159 2159 .ops = &clk_rcg_bypass2_ops, 2160 2160 .flags = CLK_SET_RATE_PARENT, 2161 2161 }, ··· 2194 2194 .hw.init = &(struct clk_init_data){ 2195 2195 .name = "dsi2_byte_src", 2196 2196 .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2197 - .num_parents = 3, 2197 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), 2198 2198 .ops = &clk_rcg_bypass2_ops, 2199 2199 .flags = CLK_SET_RATE_PARENT, 2200 2200 }, ··· 2233 2233 .hw.init = &(struct clk_init_data){ 2234 2234 .name = "dsi1_esc_src", 2235 2235 .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2236 - .num_parents = 3, 2236 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), 2237 2237 .ops = &clk_rcg_esc_ops, 2238 2238 }, 2239 2239 }, ··· 2271 2271 .hw.init = &(struct clk_init_data){ 2272 2272 .name = "dsi2_esc_src", 2273 2273 .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2274 - .num_parents = 3, 2274 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), 2275 2275 .ops = &clk_rcg_esc_ops, 2276 2276 }, 2277 2277 }, ··· 2318 2318 .hw.init = &(struct clk_init_data){ 2319 2319 .name = "dsi1_pixel_src", 2320 2320 .parent_names = mmcc_pxo_dsi2_dsi1, 2321 - .num_parents = 3, 2321 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2322 2322 .ops = &clk_rcg_pixel_ops, 2323 2323 }, 2324 2324 }, ··· 2365 2365 .hw.init = &(struct clk_init_data){ 2366 2366 .name = "dsi2_pixel_src", 2367 2367 .parent_names = mmcc_pxo_dsi2_dsi1, 2368 - .num_parents = 3, 2368 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2369 2369 .ops = &clk_rcg_pixel_ops, 2370 2370 }, 2371 2371 },