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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: qcom: lcc-msm8960: use parent_hws/_data instead of parent_names
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-7-dmitry.baryshkov@linaro.org
authored by
Dmitry Baryshkov
and committed by
Bjorn Andersson
a6976f85
7026af10
+37
-32
+37
-32
drivers/clk/qcom/lcc-msm8960.c
+37
-32
drivers/clk/qcom/lcc-msm8960.c
···
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.status_bit = 16,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pll4",
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-
.parent_names = (const char *[]){ "pxo" },
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+
.parent_data = (const struct clk_parent_data[]){
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{ .fw_name = "pxo", .name = "pxo_board" },
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},
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
···
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{ P_PLL4, 2 }
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};
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-
static const char * const lcc_pxo_pll4[] = {
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"pxo",
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"pll4_vote",
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static const struct clk_parent_data lcc_pxo_pll4[] = {
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{ .fw_name = "pxo", .name = "pxo_board" },
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{ .fw_name = "pll4_vote", .name = "pll4_vote" },
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};
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static struct freq_tbl clk_tbl_aif_osr_492[] = {
···
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.enable_mask = BIT(9), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_osr_src", \
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.parent_names = lcc_pxo_pll4, \
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.num_parents = 2, \
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.parent_data = lcc_pxo_pll4, \
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.num_parents = ARRAY_SIZE(lcc_pxo_pll4), \
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.ops = &clk_rcg_ops, \
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.flags = CLK_SET_RATE_GATE, \
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}, \
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}, \
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}; \
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\
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static const char * const lcc_##prefix##_parents[] = { \
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#prefix "_osr_src", \
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}; \
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#define CLK_AIF_OSR_CLK(prefix, _ns, hr, en_bit) \
···
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.enable_mask = BIT(en_bit), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_osr_clk", \
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.parent_names = lcc_##prefix##_parents, \
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.parent_hws = (const struct clk_hw*[]){ \
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&prefix##_osr_src.clkr.hw, \
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+
}, \
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.num_parents = 1, \
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.ops = &clk_branch_ops, \
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.flags = CLK_SET_RATE_PARENT, \
···
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.clkr = { \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_div_clk", \
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.parent_names = lcc_##prefix##_parents, \
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.parent_hws = (const struct clk_hw*[]){ \
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&prefix##_osr_src.clkr.hw, \
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}, \
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.num_parents = 1, \
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.ops = &clk_regmap_div_ops, \
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}, \
···
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.enable_mask = BIT(en_bit), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_bit_div_clk", \
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-
.parent_names = (const char *[]){ \
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#prefix "_div_clk" \
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}, \
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.parent_hws = (const struct clk_hw*[]){ \
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&prefix##_div_clk.clkr.hw, \
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}, \
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.num_parents = 1, \
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.ops = &clk_branch_ops, \
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.flags = CLK_SET_RATE_PARENT, \
···
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.clkr = { \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_bit_clk", \
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.parent_names = (const char *[]){ \
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#prefix "_bit_div_clk", \
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#prefix "_codec_clk", \
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.parent_data = (const struct clk_parent_data[]){ \
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{ .hw = &prefix##_bit_div_clk.clkr.hw, }, \
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{ .fw_name = #prefix "_codec_clk", \
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.name = #prefix "_codec_clk", }, \
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}, \
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.num_parents = 2, \
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.ops = &clk_regmap_mux_closest_ops, \
···
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_src",
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.parent_names = lcc_pxo_pll4,
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.num_parents = 2,
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.parent_data = lcc_pxo_pll4,
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.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
···
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk_out",
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.parent_names = (const char *[]){ "pcm_src" },
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.parent_hws = (const struct clk_hw*[]){
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&pcm_src.clkr.hw
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},
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
···
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk",
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.parent_names = (const char *[]){
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"pcm_clk_out",
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"pcm_codec_clk",
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.parent_data = (const struct clk_parent_data[]){
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{ .hw = &pcm_clk_out.clkr.hw },
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{ .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
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},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
···
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "slimbus_src",
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.parent_names = lcc_pxo_pll4,
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.num_parents = 2,
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.parent_data = lcc_pxo_pll4,
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.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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-
};
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static const char * const lcc_slimbus_parents[] = {
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"slimbus_src",
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};
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static struct clk_branch audio_slimbus_clk = {
···
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.enable_mask = BIT(10),
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.hw.init = &(struct clk_init_data){
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.name = "audio_slimbus_clk",
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.parent_names = lcc_slimbus_parents,
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.parent_hws = (const struct clk_hw*[]){
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&slimbus_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
···
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.enable_mask = BIT(12),
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.hw.init = &(struct clk_init_data){
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.name = "sps_slimbus_clk",
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.parent_names = lcc_slimbus_parents,
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.parent_hws = (const struct clk_hw*[]){
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&slimbus_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,