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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: lan966x: Add lan966x SoC clock driver
This adds Generic Clock Controller driver for lan966x SoC.
Lan966x clock controller contains 3 PLLs - cpu_clk, ddr_clk
and sys_clk. It generates and supplies clock to various
peripherals within SoC.
Register settings required to provide GCK clocking to a
peripheral is as below:
GCK_SRC_SEL = Select clock source.
GCK_PRESCALER = Set divider value.
GCK_ENA = 1 - Enable GCK clock.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Co-developed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103061935.25677-4-kavyasree.kotagiri@microchip.com
authored by
Kavyasree Kotagiri
and committed by
Nicolas Ferre
54104ee0
07300ef4
+248
+7
drivers/clk/Kconfig
+7
drivers/clk/Kconfig
···
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This driver supports the SoC clocks on the Cortina Systems Gemini
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platform, also known as SL3516 or CS3516.
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config COMMON_CLK_LAN966X
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bool "Generic Clock Controller driver for LAN966X SoC"
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help
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This driver provides support for Generic Clock Controller(GCK) on
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LAN966X SoC. GCK generates and supplies clock to various peripherals
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within the SoC.
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config COMMON_CLK_ASPEED
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bool "Clock driver for Aspeed BMC SoCs"
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depends on ARCH_ASPEED || COMPILE_TEST
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
···
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
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obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
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obj-$(CONFIG_LMK04832) += clk-lmk04832.o
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obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o
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obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
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obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
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obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
+240
drivers/clk/clk-lan966x.c
+240
drivers/clk/clk-lan966x.c
···
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Microchip LAN966x SoC Clock driver.
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*
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* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
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*
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* Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/microchip,lan966x.h>
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#define GCK_ENA BIT(0)
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#define GCK_SRC_SEL GENMASK(9, 8)
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#define GCK_PRESCALER GENMASK(23, 16)
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#define DIV_MAX 255
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static const char *clk_names[N_CLOCKS] = {
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"qspi0", "qspi1", "qspi2", "sdmmc0",
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"pi", "mcan0", "mcan1", "flexcom0",
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"flexcom1", "flexcom2", "flexcom3",
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"flexcom4", "timer1", "usb_refclk",
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};
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struct lan966x_gck {
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struct clk_hw hw;
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void __iomem *reg;
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};
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#define to_lan966x_gck(hw) container_of(hw, struct lan966x_gck, hw)
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static const struct clk_parent_data lan966x_gck_pdata[] = {
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{ .fw_name = "cpu", },
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{ .fw_name = "ddr", },
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{ .fw_name = "sys", },
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};
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static struct clk_init_data init = {
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.parent_data = lan966x_gck_pdata,
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.num_parents = ARRAY_SIZE(lan966x_gck_pdata),
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};
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static void __iomem *base;
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static int lan966x_gck_enable(struct clk_hw *hw)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 val = readl(gck->reg);
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val |= GCK_ENA;
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writel(val, gck->reg);
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return 0;
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}
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static void lan966x_gck_disable(struct clk_hw *hw)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 val = readl(gck->reg);
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val &= ~GCK_ENA;
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writel(val, gck->reg);
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}
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static int lan966x_gck_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 div, val = readl(gck->reg);
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if (rate == 0 || parent_rate == 0)
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return -EINVAL;
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/* Set Prescalar */
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div = parent_rate / rate;
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val &= ~GCK_PRESCALER;
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val |= FIELD_PREP(GCK_PRESCALER, (div - 1));
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writel(val, gck->reg);
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return 0;
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}
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static long lan966x_gck_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned int div;
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if (rate == 0 || *parent_rate == 0)
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return -EINVAL;
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if (rate >= *parent_rate)
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return *parent_rate;
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div = DIV_ROUND_CLOSEST(*parent_rate, rate);
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return *parent_rate / div;
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}
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static unsigned long lan966x_gck_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 div, val = readl(gck->reg);
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div = FIELD_GET(GCK_PRESCALER, val);
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return parent_rate / (div + 1);
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}
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static int lan966x_gck_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_hw *parent;
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int i;
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for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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/* Allowed prescaler divider range is 0-255 */
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if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) {
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req->best_parent_hw = parent;
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req->best_parent_rate = clk_hw_get_rate(parent);
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return 0;
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}
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}
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return -EINVAL;
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}
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static u8 lan966x_gck_get_parent(struct clk_hw *hw)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 val = readl(gck->reg);
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return FIELD_GET(GCK_SRC_SEL, val);
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}
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static int lan966x_gck_set_parent(struct clk_hw *hw, u8 index)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 val = readl(gck->reg);
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val &= ~GCK_SRC_SEL;
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val |= FIELD_PREP(GCK_SRC_SEL, index);
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writel(val, gck->reg);
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return 0;
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}
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static const struct clk_ops lan966x_gck_ops = {
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.enable = lan966x_gck_enable,
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.disable = lan966x_gck_disable,
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.set_rate = lan966x_gck_set_rate,
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.round_rate = lan966x_gck_round_rate,
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.recalc_rate = lan966x_gck_recalc_rate,
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.determine_rate = lan966x_gck_determine_rate,
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.set_parent = lan966x_gck_set_parent,
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.get_parent = lan966x_gck_get_parent,
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};
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static struct clk_hw *lan966x_gck_clk_register(struct device *dev, int i)
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{
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struct lan966x_gck *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return ERR_PTR(-ENOMEM);
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priv->reg = base + (i * 4);
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priv->hw.init = &init;
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ret = devm_clk_hw_register(dev, &priv->hw);
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if (ret)
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return ERR_PTR(ret);
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return &priv->hw;
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};
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static int lan966x_clk_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *hw_data;
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struct device *dev = &pdev->dev;
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int i;
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hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS),
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GFP_KERNEL);
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if (!hw_data)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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init.ops = &lan966x_gck_ops;
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hw_data->num = N_CLOCKS;
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for (i = 0; i < N_CLOCKS; i++) {
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init.name = clk_names[i];
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hw_data->hws[i] = lan966x_gck_clk_register(dev, i);
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if (IS_ERR(hw_data->hws[i])) {
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dev_err(dev, "failed to register %s clock\n",
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init.name);
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return PTR_ERR(hw_data->hws[i]);
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}
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}
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data);
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}
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static const struct of_device_id lan966x_clk_dt_ids[] = {
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{ .compatible = "microchip,lan966x-gck", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids);
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static struct platform_driver lan966x_clk_driver = {
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.probe = lan966x_clk_probe,
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.driver = {
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.name = "lan966x-clk",
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.of_match_table = lan966x_clk_dt_ids,
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},
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};
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builtin_platform_driver(lan966x_clk_driver);
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MODULE_AUTHOR("Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>");
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MODULE_DESCRIPTION("LAN966X clock driver");
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MODULE_LICENSE("GPL v2");