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mtd: spinand: gigadevice: add support for GD5FxGM7xExxG

Add support for:
GD5F{1,2}GM7{U,R}ExxG
GD5F4GM8{U,R}ExxG

These are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice
with 8b/512b on-die ECC capability.
These chips (and currently supported GD5FxGQ5 chips) have QIO DTR
instruction for reading page cache. It isn't added in this patch because
I don't have a DTR spi controller for testing.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-6-gch981213@gmail.com

authored by

Chuanhong Guo and committed by
Miquel Raynal 54647cd0 194ec04b

+60
+60
drivers/mtd/nand/spi/gigadevice.c
··· 441 441 SPINAND_HAS_QE_BIT, 442 442 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, 443 443 gd5fxgq5xexxg_ecc_get_status)), 444 + SPINAND_INFO("GD5F1GM7UExxG", 445 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91), 446 + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 447 + NAND_ECCREQ(8, 512), 448 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, 449 + &write_cache_variants, 450 + &update_cache_variants), 451 + SPINAND_HAS_QE_BIT, 452 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, 453 + gd5fxgq4uexxg_ecc_get_status)), 454 + SPINAND_INFO("GD5F1GM7RExxG", 455 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81), 456 + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 457 + NAND_ECCREQ(8, 512), 458 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, 459 + &write_cache_variants, 460 + &update_cache_variants), 461 + SPINAND_HAS_QE_BIT, 462 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, 463 + gd5fxgq4uexxg_ecc_get_status)), 464 + SPINAND_INFO("GD5F2GM7UExxG", 465 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), 466 + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), 467 + NAND_ECCREQ(8, 512), 468 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, 469 + &write_cache_variants, 470 + &update_cache_variants), 471 + SPINAND_HAS_QE_BIT, 472 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, 473 + gd5fxgq4uexxg_ecc_get_status)), 474 + SPINAND_INFO("GD5F2GM7RExxG", 475 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82), 476 + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), 477 + NAND_ECCREQ(8, 512), 478 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, 479 + &write_cache_variants, 480 + &update_cache_variants), 481 + SPINAND_HAS_QE_BIT, 482 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, 483 + gd5fxgq4uexxg_ecc_get_status)), 484 + SPINAND_INFO("GD5F4GM8UExxG", 485 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95), 486 + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), 487 + NAND_ECCREQ(8, 512), 488 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, 489 + &write_cache_variants, 490 + &update_cache_variants), 491 + SPINAND_HAS_QE_BIT, 492 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, 493 + gd5fxgq4uexxg_ecc_get_status)), 494 + SPINAND_INFO("GD5F4GM8RExxG", 495 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85), 496 + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), 497 + NAND_ECCREQ(8, 512), 498 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, 499 + &write_cache_variants, 500 + &update_cache_variants), 501 + SPINAND_HAS_QE_BIT, 502 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, 503 + gd5fxgq4uexxg_ecc_get_status)), 444 504 }; 445 505 446 506 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {