Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: dts: rockchip: Add Rockchip RV1126 SoC
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch add basic core dtsi support.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20221129075424.189655-5-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
authored by
Jagan Teki
and committed by
Heiko Stuebner
5496d279
0fa22d06
+438
+438
arch/arm/boot/dts/rv1126.dtsi
+438
arch/arm/boot/dts/rv1126.dtsi
···
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/clock/rockchip,rv1126-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/power/rockchip,rv1126-power.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rv1126";
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+
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interrupt-parent = <&gic>;
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+
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aliases {
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i2c0 = &i2c0;
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};
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+
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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+
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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};
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+
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cpu1: cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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};
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+
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cpu2: cpu@f02 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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};
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+
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cpu3: cpu@f03 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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+
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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+
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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+
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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+
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grf: syscon@fe000000 {
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compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
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reg = <0xfe000000 0x20000>;
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};
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+
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pmugrf: syscon@fe020000 {
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compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
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reg = <0xfe020000 0x1000>;
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+
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pmu_io_domains: io-domains {
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compatible = "rockchip,rv1126-pmu-io-voltage-domain";
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status = "disabled";
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};
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};
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qos_emmc: qos@fe860000 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe860000 0x20>;
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};
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qos_nandc: qos@fe860080 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe860080 0x20>;
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};
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qos_sfc: qos@fe860200 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe860200 0x20>;
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};
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qos_sdio: qos@fe86c000 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe86c000 0x20>;
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};
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+
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gic: interrupt-controller@feff0000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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+
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reg = <0xfeff1000 0x1000>,
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<0xfeff2000 0x2000>,
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<0xfeff4000 0x2000>,
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<0xfeff6000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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+
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pmu: power-management@ff3e0000 {
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compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
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reg = <0xff3e0000 0x1000>;
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+
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power: power-controller {
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compatible = "rockchip,rv1126-power-controller";
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#power-domain-cells = <1>;
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+
#address-cells = <1>;
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+
#size-cells = <0>;
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+
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power-domain@RV1126_PD_NVM {
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reg = <RV1126_PD_NVM>;
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clocks = <&cru HCLK_EMMC>,
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<&cru CLK_EMMC>,
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<&cru HCLK_NANDC>,
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<&cru CLK_NANDC>,
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<&cru HCLK_SFC>,
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<&cru HCLK_SFCXIP>,
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<&cru SCLK_SFC>;
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pm_qos = <&qos_emmc>,
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<&qos_nandc>,
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<&qos_sfc>;
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#power-domain-cells = <0>;
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};
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+
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power-domain@RV1126_PD_SDIO {
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reg = <RV1126_PD_SDIO>;
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clocks = <&cru HCLK_SDIO>,
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<&cru CLK_SDIO>;
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pm_qos = <&qos_sdio>;
171
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#power-domain-cells = <0>;
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};
173
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};
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};
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+
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i2c0: i2c@ff3f0000 {
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compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
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reg = <0xff3f0000 0x1000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,grf = <&pmugrf>;
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clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
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clock-names = "i2c", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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+
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uart1: serial@ff410000 {
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
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reg = <0xff410000 0x100>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 7>, <&dmac 6>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1m0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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+
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pmucru: clock-controller@ff480000 {
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compatible = "rockchip,rv1126-pmucru";
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reg = <0xff480000 0x1000>;
209
+
rockchip,grf = <&grf>;
210
+
#clock-cells = <1>;
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+
#reset-cells = <1>;
212
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};
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+
214
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cru: clock-controller@ff490000 {
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compatible = "rockchip,rv1126-cru";
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reg = <0xff490000 0x1000>;
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clocks = <&xin24m>;
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clock-names = "xin24m";
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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+
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dmac: dma-controller@ff4e0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xff4e0000 0x4000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
230
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arm,pl330-periph-burst;
231
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
233
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};
234
+
235
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uart0: serial@ff560000 {
236
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
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reg = <0xff560000 0x100>;
238
+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
239
+
clock-frequency = <24000000>;
240
+
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
241
+
clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 5>, <&dmac 4>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
249
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};
250
+
251
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uart2: serial@ff570000 {
252
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
253
+
reg = <0xff570000 0x100>;
254
+
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
255
+
clock-frequency = <24000000>;
256
+
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
257
+
clock-names = "baudclk", "apb_pclk";
258
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dmas = <&dmac 9>, <&dmac 8>;
259
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dma-names = "tx", "rx";
260
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pinctrl-names = "default";
261
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pinctrl-0 = <&uart2m1_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
264
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status = "disabled";
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};
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+
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uart3: serial@ff580000 {
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
269
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reg = <0xff580000 0x100>;
270
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
271
+
clock-frequency = <24000000>;
272
+
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
273
+
clock-names = "baudclk", "apb_pclk";
274
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dmas = <&dmac 11>, <&dmac 10>;
275
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dma-names = "tx", "rx";
276
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pinctrl-names = "default";
277
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pinctrl-0 = <&uart3m0_xfer>;
278
+
reg-shift = <2>;
279
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reg-io-width = <4>;
280
+
status = "disabled";
281
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};
282
+
283
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uart4: serial@ff590000 {
284
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
285
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reg = <0xff590000 0x100>;
286
+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
287
+
clock-frequency = <24000000>;
288
+
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
289
+
clock-names = "baudclk", "apb_pclk";
290
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dmas = <&dmac 13>, <&dmac 12>;
291
+
dma-names = "tx", "rx";
292
+
pinctrl-names = "default";
293
+
pinctrl-0 = <&uart4m0_xfer>;
294
+
reg-shift = <2>;
295
+
reg-io-width = <4>;
296
+
status = "disabled";
297
+
};
298
+
299
+
uart5: serial@ff5a0000 {
300
+
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
301
+
reg = <0xff5a0000 0x100>;
302
+
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
303
+
clock-frequency = <24000000>;
304
+
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
305
+
clock-names = "baudclk", "apb_pclk";
306
+
dmas = <&dmac 15>, <&dmac 14>;
307
+
dma-names = "tx", "rx";
308
+
pinctrl-names = "default";
309
+
pinctrl-0 = <&uart5m0_xfer>;
310
+
reg-shift = <2>;
311
+
reg-io-width = <4>;
312
+
status = "disabled";
313
+
};
314
+
315
+
saradc: adc@ff5e0000 {
316
+
compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
317
+
reg = <0xff5e0000 0x100>;
318
+
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
319
+
#io-channel-cells = <1>;
320
+
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
321
+
clock-names = "saradc", "apb_pclk";
322
+
resets = <&cru SRST_SARADC_P>;
323
+
reset-names = "saradc-apb";
324
+
status = "disabled";
325
+
};
326
+
327
+
timer0: timer@ff660000 {
328
+
compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
329
+
reg = <0xff660000 0x20>;
330
+
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
331
+
clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
332
+
clock-names = "pclk", "timer";
333
+
};
334
+
335
+
emmc: mmc@ffc50000 {
336
+
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
337
+
reg = <0xffc50000 0x4000>;
338
+
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
339
+
clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
340
+
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
341
+
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
342
+
fifo-depth = <0x100>;
343
+
max-frequency = <200000000>;
344
+
power-domains = <&power RV1126_PD_NVM>;
345
+
status = "disabled";
346
+
};
347
+
348
+
sdmmc: mmc@ffc60000 {
349
+
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
350
+
reg = <0xffc60000 0x4000>;
351
+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
352
+
clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
353
+
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
354
+
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
355
+
fifo-depth = <0x100>;
356
+
max-frequency = <200000000>;
357
+
status = "disabled";
358
+
};
359
+
360
+
sdio: mmc@ffc70000 {
361
+
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
362
+
reg = <0xffc70000 0x4000>;
363
+
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
364
+
clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
365
+
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
366
+
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
367
+
fifo-depth = <0x100>;
368
+
max-frequency = <200000000>;
369
+
power-domains = <&power RV1126_PD_SDIO>;
370
+
status = "disabled";
371
+
};
372
+
373
+
pinctrl: pinctrl {
374
+
compatible = "rockchip,rv1126-pinctrl";
375
+
rockchip,grf = <&grf>;
376
+
rockchip,pmu = <&pmugrf>;
377
+
#address-cells = <1>;
378
+
#size-cells = <1>;
379
+
ranges;
380
+
381
+
gpio0: gpio@ff460000 {
382
+
compatible = "rockchip,gpio-bank";
383
+
reg = <0xff460000 0x100>;
384
+
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
385
+
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
386
+
gpio-controller;
387
+
#gpio-cells = <2>;
388
+
interrupt-controller;
389
+
#interrupt-cells = <2>;
390
+
};
391
+
392
+
gpio1: gpio@ff620000 {
393
+
compatible = "rockchip,gpio-bank";
394
+
reg = <0xff620000 0x100>;
395
+
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
396
+
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
397
+
gpio-controller;
398
+
#gpio-cells = <2>;
399
+
interrupt-controller;
400
+
#interrupt-cells = <2>;
401
+
};
402
+
403
+
gpio2: gpio@ff630000 {
404
+
compatible = "rockchip,gpio-bank";
405
+
reg = <0xff630000 0x100>;
406
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
407
+
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
408
+
gpio-controller;
409
+
#gpio-cells = <2>;
410
+
interrupt-controller;
411
+
#interrupt-cells = <2>;
412
+
};
413
+
414
+
gpio3: gpio@ff640000 {
415
+
compatible = "rockchip,gpio-bank";
416
+
reg = <0xff640000 0x100>;
417
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
418
+
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
419
+
gpio-controller;
420
+
#gpio-cells = <2>;
421
+
interrupt-controller;
422
+
#interrupt-cells = <2>;
423
+
};
424
+
425
+
gpio4: gpio@ff650000 {
426
+
compatible = "rockchip,gpio-bank";
427
+
reg = <0xff650000 0x100>;
428
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
429
+
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
430
+
gpio-controller;
431
+
#gpio-cells = <2>;
432
+
interrupt-controller;
433
+
#interrupt-cells = <2>;
434
+
};
435
+
};
436
+
};
437
+
438
+
#include "rv1126-pinctrl.dtsi"