tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915: Remove i915_reg.h from g4x_dp.c

Move DE_IRQ_REGS to display header to make g4x_dp.c
free from i915_reg.h dependency. These registers are
only used by display and gvt.

v3: Drop a superfluous include (Jani)

v2: Move DE interrupt regs from common to display header (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-12-uma.shankar@intel.com

Uma Shankar 5504f1ac 85bba73b

+16 -16
-1
drivers/gpu/drm/i915/display/g4x_dp.c
··· 10 10 #include <drm/drm_print.h> 11 11 12 12 #include "g4x_dp.h" 13 - #include "i915_reg.h" 14 13 #include "intel_audio.h" 15 14 #include "intel_backlight.h" 16 15 #include "intel_connector.h"
+16
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 1049 1049 #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 1050 1050 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 1051 1051 1052 + #define DEISR _MMIO(0x44000) 1053 + #define DEIMR _MMIO(0x44004) 1054 + #define DEIIR _MMIO(0x44008) 1055 + #define DEIER _MMIO(0x4400c) 1056 + 1057 + #define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \ 1058 + DEIER, \ 1059 + DEIIR) 1060 + 1052 1061 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 1053 1062 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 1054 1063 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ ··· 1800 1791 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 1801 1792 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 1802 1793 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 1794 + 1795 + /* PCH */ 1796 + 1797 + #define SDEISR _MMIO(0xc4000) 1798 + #define SDEIMR _MMIO(0xc4004) 1799 + #define SDEIIR _MMIO(0xc4008) 1800 + #define SDEIER _MMIO(0xc400c) 1803 1801 1804 1802 #define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \ 1805 1803 SDEIER, \
-15
drivers/gpu/drm/i915/i915_reg.h
··· 727 727 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 728 728 #define MASTER_INTERRUPT_ENABLE (1 << 31) 729 729 730 - #define DEISR _MMIO(0x44000) 731 - #define DEIMR _MMIO(0x44004) 732 - #define DEIIR _MMIO(0x44008) 733 - #define DEIER _MMIO(0x4400c) 734 - 735 - #define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \ 736 - DEIER, \ 737 - DEIIR) 738 - 739 730 #define GTISR _MMIO(0x44010) 740 731 #define GTIMR _MMIO(0x44014) 741 732 #define GTIIR _MMIO(0x44018) ··· 854 863 #define MASK_WAKEMEM REG_BIT(13) 855 864 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 856 865 857 - /* PCH */ 858 - 859 - #define SDEISR _MMIO(0xc4000) 860 - #define SDEIMR _MMIO(0xc4004) 861 - #define SDEIIR _MMIO(0xc4008) 862 - #define SDEIER _MMIO(0xc400c) 863 866 864 867 /* Icelake PPS_DATA and _ECC DIP Registers. 865 868 * These are available for transcoders B,C and eDP.